CET 486 – 586 Hardware Description Language: Hardware Description Language: VHDL VHDL Introduction to hardware description languages using VHDL. Techniques for modeling and simulating small digital systems using a VHDL simulator C. Sisterna Spring 2003 ECET – CET 486
26
Embed
CET 486 – 586 Hardware Description Language:Hardware Description Language: VHDLdea.unsj.edu.ar/sisdig2/Introduccion a VHDL.pdf · VHDL Flow Design Specifications Synthesis & VHDL
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
CET 486 – 586 Hardware Description Language:Hardware Description Language:
VHDLVHDL
Introduction to hardware description languages using VHDL. Techniques for modeling and simulating small digital systems
using a VHDL simulator
C. Sisterna Spring 2003
ECET – CET 486
Textbooks
“A VHDL Primer” by J. Bhasker, Prentice Hall, Third Edition Required textEdition. Required text“The Designer’s Guide to VHDL” by Peter Ashenden,Morgan Kaufman Reference textMorgan Kaufman. Reference text“VHDL for Designers” by Sjoholm and Lindh. PrenticeHall Reference textHall. Reference text“VHDL for Logic Synthesis. An introductory guide for
hi i D i R i t ” b A d R htachieving Design Requirements” by Andrew Rushton. McGraw Hill. Reference text
• V Hi h S d IC H d D i ti L• Very High Speed IC Hardware Description Language• The design is technologically independent• Allow to design generic components• Standard component already coded in VHDLp y• Timing verification• The designer concern is the functionality• The designer concern is the functionality • Portability: VHDL is an IEEE standard
VHDL S ti l L C t L• VHDL = Sequential Language + Concurrent Language + Net-List + Timing Constraints + Waveform Generation
C. Sisterna Spring 2003
ECET – CET 486
VHDL – Features (cont’)
• Flexible design methodology: top down bottom up• Flexible design methodology: top-down, bottom-up • It is not proprietary• There is no limit for the design to be described in VHDL• Allow description of delay time (minimum and
maximum), hold time, setup time• Very short development timey p• Allow different levels of abstraction (Assembler, C, C++)
C. Sisterna Spring 2003
ECET – CET 486
VHDL Flow Design
Specifications Synthesis & p
VHDL C d
yOptimization
VHDL CodePlace & Route
CompilationTiming
VerificationSimulation & Verification
Verification
Back-end ToolsFront-end Tools
C. Sisterna Spring 2003
ECET – CET 486
VHDL – General ViewVHDL General View
Introduction to VHDL
C. Sisterna Spring 2003
ECET – CET 486
Entity
• A hardware abstraction of a Digital System is an entity• A hardware abstraction of a Digital System is an entity
• Five VHDL design units describe an entity– Entity declaration– Architecture body– Configuration declaration– Package declaration– Package body
C. Sisterna Spring 2003
ECET – CET 486
Entity declaration
• Describe the external view of an entity The input and• Describe the external view of an entity. The input and output signal names:--===================================================------ entity declaration syntax----===================================================--
• Contains the internal description of the entity--====================================================------ architecture body syntax----====================================================--
architecture <architecture_name> of <entity_name> is[architecture_declarations]
beginconcurrent_statements;
[process_statementblock_statement
t d ll t t tconcurrent_procedure_call_statementconcurrent_assertion_statementconcurrent_signal_assignment_statementcomponent instantiation statementcomponent_instantiation_statementgenerate_statement]