capacitor balance in anpc.pdf

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 3, MARCH 2015 1147

Capacitor Voltage Balancing of a Five-Level ANPCConverter Using Phase-Shifted PWM

Kui Wang, Member, IEEE, Lie Xu, Member, IEEE, Zedong Zheng, Member, IEEE, and Yongdong Li, Member, IEEE

AbstractFive-level active neutral-point clamped (5L-ANPC)converter is an attractive topology for high-power medium-voltagemotor drives. This paper presents a capacitor voltage-balancingmethod for the 5L-ANPC converter, including the voltage balanc-ing of dc-link capacitors and flying capacitors. In order to ensurethat the series-connected or high-voltage switches of the 5L-ANPCconverter are operated at fundamental frequency and the otherswitches are operated at a constant switching frequency, phase-shifted pulse width modulation is used to control this converter. Therelationship between the average neutral-point current and zero-sequence voltage is investigated, and an optimum zero-sequencevoltage is calculated to regulate the neutral-point potential. Thevoltage across the flying capacitor is also regulated by adjustingthe switching duty cycles of two PWM signals, which varies theoperation time of redundant switching states in each switching pe-riod. Simulation and experimental results are presented to verifythe validity of this method.

Index TermsActive neutral-point clamped (ANPC), capacitorvoltage balancing, multilevel converter, phase-shifted pulse widthmodulation (PWM), zero-sequence voltage.

I. INTRODUCTION

MULTILEVEL converters have been widely used inhigh-voltage high-power applications since 1981 [1].Among the existing multilevel converters, neutral-point-clamped (NPC), flying-capacitor (FC), and cascaded H-bridge(CHB) multilevel converters are three classical multileveltopologies that are the most widely used in the industry [2][7].However, when the number of voltage levels increases, not onlythe complexity to control the voltage across the dc-link capaci-tors in the NPC converter and the FCs in the FC converter, butalso the number of clamping diodes in the NPC converter, FCsin the FC converter, and isolated transformer windings in theCHB converter is greatly increased [8][10].

Modular multilevel converter (MMC) is an emerging mul-tilevel converter topology which gains increasing attentions in

Manuscript received December 31, 2013; revised March 9, 2014; acceptedApril 17, 2014. Date of publication April 29, 2014; date of current versionOctober 15, 2014. This paper was presented in part at the IEEE Energy Con-version Congress and Exposition, Denver, CO, USA, September 1519, 2013.Recommended for publication by Associate Editor F. H. Khan.

K. Wang, L. Xu, and Z. Zheng are with the State Key Laboratory ofPower System, Department of Electrical Engineering, Tsinghua University,Beijing 100084, China (e-mail: [email protected]; [email protected]; [email protected]).

Y. Li is with the Department of Electrical Engineering, Tsinghua University,Beijing, China, and also with the School of Electrical Engineering, XinjiangUniversity, Urumqi 830046, China (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2014.2320985

recent years [11][17]. It is comprised of a number of cascadedhalf-bridges without transformer and the output voltage canreach to hundreds of kilovolts. The most successful commercialapplication of MMC is in high-voltage direct-current (HVDC)transmissions [15][17]. When used in medium-voltage motordrives, it suffers from low-frequency fluctuation in the floatingcapacitors [12]. Therefore, the MMC would not be suitable forconstant-torque loads that require the rated torque in a low-speedregion.

Five-level active neutral-point clamped (ANPC) converter isan attractive multilevel topology, which is more suitable forhigh-performance medium-voltage motor drives [18][25]. Itsdc-link is subdivided into two parts and only four switches andone FC are needed for clamping per phase; hence, the costs, vol-ume, and control complexity can be reduced. The main problemof this topology is the unequal voltage stresses of switches andvoltage balancing of the dc-link and FCs [19][23].

A new four-quadrant medium-voltage drive using this five-level ANPC topology is described in [19]. The direct torquecontrol method based on space-vector PWM (SVPWM) is usedto control this converter. A proper combination of three-phaseswitching states is selected to produce the voltage vectors toregulate the desired output voltage and balance the neutral-point (NP) potential and FC voltages while maintaining thesame line voltage. However, the large number of redundantvoltage vectors and redundant switching states makes the controlmethod fairly complex. A five-level virtual-flux direct powercontrol for the five-level ANPC converter was implementedin [20]. The switching frequency of the series-connected orhigh-voltage switches is higher than the fundamental frequency,which will increase the switching losses.

A phase-disposition PWM (PD-PWM) with zero-sequencevoltage injection method was proposed in [21] to control the NPpotential of the 5L-ANPC converter. The redundant switchingstates are utilized to control the voltages across the FCs. How-ever, the calculation and selection of zero-sequence voltage isvery complex and the switching frequency is not constant forthe outside switches with PD-PWM. In [22], a control strategybased on selective harmonic elimination PWM was proposedand the voltage across the FCs was balanced by swapping theswitching patterns. The NP voltage was regulated by addingor subtracting a relatively small pulse to the switching pulsesignals [22], [23]. This method is very suitable for the high-power and low switching-frequency applications. However, thevoltage regulation ability is not strong due to the low switchingfrequency and the capacitor voltage ripple will be high.

This paper focuses on the voltage-balancing issue of the 5L-ANPC converter, including the voltage balancing of dc-link

0885-8993 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

1148 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 30, NO. 3, MARCH 2015

Fig. 1. Single phase of the 5L-ANPC converter.

capacitors and FCs. The series-connected or high-voltageswitches are operated at fundamental frequency and the otherswitches are controlled with PS-PWM, which can minimize thehigher silicon demand of the converter and lower the switchinglosses. In order to balance the NP potential, the relationship be-tween the average NP current and zero-sequence voltage underPS-PWM is discussed and an optimal zero-sequence voltagecan be obtained easily. The voltage balancing of the FCs is alsoachieved by adjusting the switching duty cycles of two PWMsignals slightly, which essentially varies the operation time ofthe redundant switching states in each switching period. Withthis method, the voltage-balancing control of the NP and FCs aredecoupled. The NP potential and FC voltages can be controlledto a given value precisely and rapidly.

This paper is organized in the following way. In Section II,the operating principles of the 5L-ANPC converter and the mod-ulation method are introduced first. The NP potential-balancingmethod based on zero-sequence voltage injection is discussedin Section III, and the voltage balancing of FCs is discussedin Section IV. In Section V, simulation and experimental re-sults are presented to validate the proposed method, and finally,conclusions are summarized in Section VI.

II. OPERATING PRINCIPLES AND MODULATION METHOD

A single phase of the 5L-ANPC converter is shown in Fig. 1.Each phase of this converter consists of eight switches and anFC. If the voltage across the FC is assumed constant and isequal to Uc , then the voltages across the upper and lower dc-link capacitors are 2Uc . So Sx3 , Sx3 , Sx4 , and S

x4 require two

switches connected in series or high-voltage switches to bear ahigher voltage 2Uc . All the switching states V0V7 are listedin Table I, where x represents phase (a, b, or c), if x and iNPxare the corresponding FC current and NP current and iox is thephase current. Since (Sx1 , Sx1), (Sx2 , S

x2), (Sx3 , S

x3), and (Sx4 ,

Sx4) are complementary switch pairs and Sx3 and Sx4 requirethe same switching signal, only Sx1Sx4 are given in Table I.The NP of the dc-link is referred as the zero potential.

From Table I, it can be seen that Sx3 and Sx4 are turnedOFF when the output voltage is negative and turned ON whenthe output voltage is positive. So the series-connected or high-voltage switch pairs (Sx3 , Sx3) and (Sx4 , S

x4) can be operated

at fundamental frequency based on the polarity of the phasevoltage. The other switch pairs (Sx1 , Sx1), (Sx2 , S

x2) together

TABLE ISWITCHING STATES OF THE 5L-ANPC CONVERTER

with FC Cfx can be regarded as a three-level FC converterphase, so classic PS-PWM can be used to control the switchpairs (Sx1 , Sx1) and (Sx2 , S

x2).

Defining the switching functions of switches Sx1Sx3 beSfx1Sfx3 , respectively, the instantaneous output voltage Voxcan be written as

Vox = [2 (Sfx3 1) + Sfx2 + Sfx1 ] Uc . (1)

If Uc is selected as the base voltage value, then the range ofthe output phase voltage is [2, 2]. In order to operate Sx3 atfundamental frequency, Sfx3 can be decided as follows:

Sfx3 =

{1, 0 uox 20, 2 uox 0

(2)

where uox is the reference output phase voltage. Then the refer-ence modulation voltage urefx of (Sx1 , Sx1) and (Sx2 , S

x2) can

be written as follows:

urefx =

{uox/2, Sf x3 = 1

(uox + 2)/2, Sf x3 = 0.(3)

The diagram of PS-PWM used for the 5L-ANPC converteris shown in Fig. 2. The carrier signals for switches Sx1 and Sx2are two triangular waves phase shifted by 180o . The resultingPWM signals are switching functions Sfx1 and Sfx2 to controlthe corresponding switches.

III. VOLTAGE BALANCING OF THE DC-LINK CAPACITORS

A. Modeling of the Average NP Current

From Fig. 1 and Table I, it can be seen that the load currentflows out of the NP when Sx3 and Sx2 are switched ON or Sx3and Sx2 are switched ON. So the instantaneous NP current iNPxcan be written as

iNPx =

{(1 Sfx2) iox , Sf x3 = 1Sfx2 iox , Sf x3 = 0

(4)

If the carrier frequency is higher enough than the fundamen-tal frequency, then the reference modulation voltage and phasecurrent can be assumed constant in a carrier period. So the dutyratio of Sfx1 and Sfx2 in a carrier period is equal to the ref-erence modulation voltage urefx . Based on (2)(4), the average

WANG et al.: CAPACITOR VOLTAGE BALANCING OF A FIVE-LEVEL ANPC CONVERTER USING PHASE-SHIFTED PWM 1149

Fig. 2. Diagram of PS-PWM used for the 5L-ANPC converter.

NP current of a single phase in a carrier period can be writtenas

iNPx =

{(1 uox/2) iox , 0 uox 2(1 + uox/2) iox , 2 uox 0.

(5)

Then, the total average NP current is

iNP = iNPa + iNPb + iNPc

= (ioa + iob + ioc) (|uoa | ioa + |uob | iob + |uoc | ioc)/2.(6)

For a three-phase three-wire system, there exists ioa + iob +ioc = 0. So (6) can be written as

iNP = (|uoa | ioa + |uob | iob + |uoc | ioc)/2. (7)

B. NP Potential-Balancing Method

As a most important freedom degree in the carrier-basedPWM, zero-sequence voltage does not influence the output linevoltage and current. It leads to different pulse patterns and soresults to different NP currents [26]. If a zero-sequence voltageuz is injected into the three-phase reference voltages, the actualphase voltage and reference modulation voltage can be writtenas {

uox = uox + uz

urefx = urefx + uz/2.(8)

In order to operate the series-connected or high-voltageswitches at fundamental frequency, the polarity of the initialthree-phase voltages cannot be changed after zero-sequencevoltage injection. Defining the minimal, medium, and max-imal values of uoa , uob , and uoc be umin , umid , and umax ,respectively, since umax + umid + umin = 0, there must existumax > 0 and umin < 0, only the polarity of umid is uncertain.

If umid > 0, then (7) can be written as

iNP = (umax imax + umid imid umin imin)/2 (9)

where imin , imid , and imax are the phase currents correspondingto umin , umid , and umax .

After zero-sequence voltage injection, the average NP currentcan be written as

iNP = (umax imax + umid imid umin imin)/2

= iNP (imax + imid imin) uz/2. (10)

If umid < 0, then (7) can be written as

iNP = (umax imax umid imid umin imin)/2. (11)

After zero-sequence voltage injection, the average NP currentcan be written as

iNP = (umax imax umid imid umin imin)/2

= iNP (imax imid imin) uz/2. (12)

According to (10) and (12), the average NP current is lin-early proportion to the zero-sequence voltage. In order to en-sure the polarity of the three-phase voltages unchanged afterzero-sequence voltage injection, according to (8), the region ofzero-sequence voltages is limited to

uref ,min uz/2 1 uref ,max (13)

where uref ,min and uref ,max are the minimal and maximal valuesof urefa , uref b , and urefc , respectively. Then, the maximal andminimal values of uz are{

uzmax = 2(1 uref ,max)uzmin = 2uref ,min .

(14)

The two boundary values of average NP current after zero-sequence voltage injection can be calculated by plugging uzmaxand uzmin into (10) or (12). According to the actual upper andlower dc-link capacitor voltages, the demanded NP current thatis used to balance the NP potential can also be calculated easily[21]

INP ,ref = Cd udc2 udc1

Ts(15)

where Cd is the upper/lower dc-link capacitor and Ts is the car-rier period. Suppose that the two boundary values correspondingto uzmax and uzmin are INP ,max and INP ,min . Then, an optimumzero-sequence voltage uz ref can be calculated by adopting thelinear interpolation algorithm

uzref =uzmax uzmin

INP ,max INP ,min INP ,ref

+uzmin INP ,max uzmax INP ,min

INP ,max INP ,min. (16)

With this optimum zero-sequence voltage uz ref , the NP po-tential can be balanced effectively with the most appropriateNP current. The control block diagram of the NP potential-balancing method is shown in Fig. 3.


Fig. 3. Control block diagram of the NP potential-balancing method.

IV. VOLTAGE BALANCING OF THE FCS

In order to balance the FC voltages, another freedom degreeof the 5L-ANPC converter is used: redundant switching states.From Table I, it can be seen that the redundant switching statesfor voltage levels Uc and Uc have different effects on the FCs.The load current flows out of the FC when Sx2 and Sx1 areswitched ON and into it when Sx2 and Sx1 are switched ON. Sothe instantaneous FC currents if x can be written as

if x = (Sfx1 Sfx2) iox . (17)

The average FC current in a carrier period is

if x = (dx1 dx2) iox (18)

where dx1 and dx2 are the duty cycles of Sfx1 and Sfx2 in a car-rier period, respectively. When using classic PS-PWM, dx1 anddx2 are equal. So, under ideal and steady-state conditions, theaverage FC current is zero and the FC voltage can be naturallybalanced. This characteristic can also be easily obtained in theFC multilevel converter when PS-PWM is used [27][30]. How-ever, it also may diverge under nonideal and dynamic conditionsif not controlled.

According to (18), a way to regulate the average FC currentis to adjust the duty cycles of Sfx1 and Sfx2 , which varies theoperation time of redundant switching states (V1, V2) or (V5,V6) essentially. So the PS-PWM method should be modifiedslightly to achieve this goal.

Taking Ufx > Uc and iox > 0 as an example, the FC needs tobe discharged. As shown in Fig. 4, there are two cases that shouldbe considered respectively: 0 urefx 1/2 and 1/2 urefx 1, but the consequences are the same. If the duty cycle of Sfx1is decreased by t symmetrically, and the duty cycle of Sfx2is increased by t symmetrically, the output voltage remainsunchanged, but the average FC current becomes negative and

Fig. 4. Voltage balancing of FCs: (a) 0 urefx 1/2 and (b) 1/2 urefx 1.

can be written as

if x = 2tTs

iox . (19)


TABLE IICIRCUIT PARAMETERS USED FOR SIMULATION

Fig. 5. Simulation results: (a) phase voltage and (b) line voltage.

It is similar for Ufx < Uc or iox < 0. If the duty cycle ofSfx1 is increased by t symmetrically, and the duty cycle ofSfx2 is decreased by t symmetrically, the average FC currentis positive

if cx =2tTs

iox . (20)

The time width t is very small and can be controlled by aPI regulator or a hysteresis comparator. With this method, theFC voltage can be balanced easily.

Fig. 6. Simulation results of m = 0.2: (a) dc-link capacitor voltages and(b) FC voltages.

Fig. 7. Simulation results of m = 0.8: (a) dc-link capacitor voltages and(b) FC voltages.


Fig. 8. Simulation waveforms of zero-sequence voltage and reference modu-lation voltages: (a) m = 0.2; (b) m = 1.15.

V. SIMULATION AND EXPERIMENTAL RESULTS

A. Simulation Results

Simulation results using MATLAB/Simulink are presentedto verify the proposed voltage-balancing method. The circuitparameters used for simulation are summarized in Table II.

Figs. 58 show the performance of the proposed capacitorvoltage-balancing method under steady states with differentmodulation indices. Fig. 5 shows the phase voltage and linevoltage with the modulation index m = 0.8. The phase voltagehas five levels and the line voltage has nine levels. Fig. 6 showsthe voltages across the dc-link capacitors and FCs withm = 0.2,and Fig. 7 shows the voltages across the dc-link capacitors andFCs with m = 0.8. The capacitor voltages under different con-ditions are all balanced with the proposed voltage-balancingmethod.

Fig. 8 shows the waveforms of zero-sequence voltage andreference modulation voltages before and after zero-sequencevoltage injection. When the modulation index is very small,according to (13), the span of the zero-sequence voltage is verywide. When the modulation index reaches to the maximal valueof 1.15, the span of the available uz is very small and the primary

Fig. 9. Dynamic simulation results with m = 0.2: (a) dc-link capacitor volt-ages and (b) three-phase FC voltages.

role of the zero-sequence voltage is to avoid overmodulation,which will make the voltage-balancing effect not so well.

In order to demonstrate the dynamic performance of thevoltage-balancing method, Figs. 9 and 10 give the simula-tion results under dynamic states with m = 0.2 and m = 0.8,respectively.

As can be seen from Figs. 9(a) and 10(a), the upper andlower dc-link capacitor voltages are controlled balanced firstand, suddenly at t = 2 s, are set to 5% higher and lower thanthe nominal value. The two voltages diverge and stabilize at thegiven values rapidly. At t = 6 s, the dc-link capacitor voltagesare controlled back to the nominal value and balanced again.

The situation is similar for the FCs. The three-phase FC volt-ages are controlled to 1/4 of the dc-link voltage at first and,suddenly at t = 2 s, are set to 20% higher than, equal to, and20% lower than the nominal value, respectively. As shown inFigs. 9(b) and 10(b), the three voltages diverge and graduallystabilize at the new given values. At t = 6 s, the three voltagesare controlled and balanced again.


Fig. 10. Dynamic simulation results with m = 0.8: (a) dc-link capacitor volt-ages and (b) three-phase FC voltages.

B. Experimental Results

A low-power three-phase 5L-ANPC converter prototype hasbeen built up to verify the proposed control method, as shownin Fig. 11. The circuit parameters are the same as the simulationparameters in Table II. In the experiments, the capacitor voltagecontrol method is investigated with various modulation indices.For the voltage-balancing control of FCs, the time width t isset to 20% of the initial time width in the experiments.

Fig. 12 shows the experimental results of the phase voltage,line voltage, and phase current with modulation index m = 0.8.Figs. 13 and 14 present the steady-state voltage waveforms ofdc-link capacitors and FCs with modulation indices m = 0.2and m = 0.8, respectively. It can be seen that the voltages ofdc-link capacitors and FCs are all well balanced. The voltageripples increase with the load current.

Fig. 15 shows the dynamic-state waveforms of load changesfrom full load to half load and then to full load again withm = 0.2 and m = 0.8. It can be seen that the dc-link and FCvoltages remain stable during the whole process.

Fig. 16 shows the dynamic-state waveforms when the ca-pacitor voltages are controlled to different values. The voltagesof dc-link capacitors and FCs are controlled balanced at the

Fig. 11. Experimental prototype.

Fig. 12. Experimental results of (a) phase voltage (100 V/div), (b) phase tophase voltage (200 V/div), and (c) phase current (5 A/div).


Fig. 13. Experimental results of (a) dc-link capacitor voltages (2.5 V/div) and(b) three-phase FC voltages (1 V/div) with m = 0.2.

Fig. 14. Experimental results of (a) dc-link capacitor voltages (2.5 V/div) and(b) three-phase FC voltages (1 V/div) with m = 0.8.

Fig. 15. Experimental results of load step changes with (a) m = 0.2 and(b) m = 1.0. From top to bottom: phase current (10 A/div), dc-link capacitorvoltages (25 V/div), and FC voltages (25 V/div).

Fig. 16. Dynamic experimental results of dc-link capacitor voltages (5 V/div)and three-phase FC voltages (10 V/div) with (a) m = 0.2 and (b) m = 0.8.


beginning. At t = 2 s, the upper and lower dc-link capacitorvoltages are set to 5% higher and 5% lower than the nominalvalue. The FC voltages are set to 20% higher than, equal to, and20% lower than the nominal value. All the capacitor voltagesgradually stabilize at the new given values. At about t = 6.5 s,all the capacitor voltages are set back to the nominal values andbalanced again with the proposed voltage-balancing method.

The above simulation and experimental results demonstratethat the proposed voltage-balancing method has an effective andpowerful control to the NP potential and FC voltages.

VI. CONCLUSION

A capacitor voltage-balancing method for the 5L-ANPC con-verter using PS-PWM is proposed in this paper. The series-connected or high-voltage switches can be operated at funda-mental frequency and the other switches are operated at thesame constant switching frequency. The voltage balancing ofdc-link capacitors is achieved by zero-sequence voltage injec-tion. The relationship between the average NP current and thezero-sequence voltage is discussed, and it can be concluded thatthe average NP current is linearly proportional to the zero-sequence voltage under PS-PWM. So, an optimum zero-sequence voltage can be calculated to regulate the dc-link ca-pacitor voltages. The voltages across the FCs are regulated byadjusting the duty cycles of the PWM signals, which essentiallyvaries the operation time of redundant switching states in eachswitching period. Simulation and experimental results verify thevalidity of this method.

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[29] A. Ruderman and B. Reznikov, Five-level single-leg flying capacitorconverter voltage balance dynamics analysis, in Proc. Conf. Rec. IEEE35th Annu. Conf. Ind. Electron., 2009, pp. 486491.

[30] C. Feng, J. Liang, and V. G. Agelidis, Modified phase-shifted PWMcontrol for flying capacitor multilevel converters, IEEE Trans. PowerElectron., vol. 22, no. 1, pp. 178185, Jan. 2007.


Kui Wang (M11) was born in Hubei, China, in 1984.He received the B.S. and Ph.D. degrees in electricalengineering from the Department of Electrical Engi-neering, Tsinghua University, Beijing, China, in 2006and 2011, respectively.

He is currently a Faculty Member with theDepartment of Electrical Engineering, TsinghuaUniversity. His research interests include multi-level converters, control of power converters, andadjustable-speed drives.

Lie Xu (M11) was born in Beijing, China, in 1980.He received the B.S. degree in electrical and elec-tronic engineering from the Beijing University ofAeronautics and Astronautics, Beijing, in 2003, andthe M.S. and Ph.D. degrees from The University ofNottingham, Nottingham, U.K., in 2004 and 2008,respectively.

From 2008 to 2010, he was a Research Fellow withthe Department of Electrical and Electronic Engineer-ing, The University of Nottingham. He is currentlya Faculty Member with the Department of Electrical

Engineering, Tsinghua University, Beijing. His research interests include mul-tilevel techniques, multilevel converters, direct acac power conversion, andmultilevel matrix converter.

Zedong Zheng (M09) was born in Shandong, China,in 1980. He received the B.S. and Ph.D. degreesin electrical engineering from the Department ofElectrical Engineering, Tsinghua University, Beijing,China, in 2003 and 2008, respectively.

He is currently a Faculty Member with the Depart-ment of Electrical Engineering, Tsinghua University.His research interests include power electronics con-verters and high-performance motor control systems.

Yongdong Li (M08) was born in Hebei, China, in1962. He received the B.S. degree from the Harbin In-stitute of Technology, Harbin, China, in 1982, and theM.S. and Ph.D. degrees from the Department of Elec-trical Engineering, Institut National Polytechniquede Toulouse, Toulouse, France, in 1984 and 1987,respectively.

Since 1996, he has been a Professor with the De-partment of Electrical Engineering, Tsinghua Univer-sity, Beijing, China. He was also an Invited Professorwith the Institut National Polytechnique de Toulouse

and the Dean of the School of Electrical Engineering, Xinjiang University,Urumqi, China. His research interests include power electronics, machine con-trol, and wind power generation.

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