Calorimeter upgrade meeting – CERN – December 10 th 2010 Analog FE ASIC: first test results Upgrade of the front end electronics of the LHCb calorimeter E. Picatoste , A. Sanuy, D. Gascón Universitat de Barcelona Institut de Ciències del Cosmos ICC-UB
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Calorimeter upgrade meeting – CERN – December 10 th 2010
Analog FE ASIC: first test results Upgrade of the front end electronics of the LHCb calorimeter. E. Picatoste , A. Sanuy, D. Gascón Universitat de Barcelona Institut de Ciències del Cosmos ICC-UB. Calorimeter upgrade meeting – CERN – December 10 th 2010. Outline. Introduction - PowerPoint PPT Presentation
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Calorimeter upgrade meeting – CERN – December 10th 2010
Analog FE ASIC: first test results
Upgrade of the front end electronics of the LHCb calorimeter
E. Picatoste, A. Sanuy, D. Gascón
Universitat de Barcelona
Institut de Ciències del Cosmos ICC-UB
10/December/2010 LHCb Upgrade 2
Outline
(1) Introduction(2) Key tests on the first prototype(3) Test set-up(4) Offset(5) Noise(6) Input impedance(7) Linearity(8) Flatness: jitter of clock vs input signal
10/December/2010 LHCb Upgrade 3
Introduction
• ECAL analogue FE IC: channel architecture
MP2MP1
Q1
Re
Ib1 MN2
MP4MP3
MN1
Rf
Vee
Vcc
1 : K : mK : mK
Ib2
Ii
Io ∫
∫
I I
Current amplifier (mirrors)
TH
TH
AnalogueMultiplexer
Drv
ADC driver
Switched integrator
Track and Hold
First Prototype
10/December/2010 LHCb Upgrade 4
Introduction
• IC sent: ICECAL
Current preamp
Integrators
10/December/2010 LHCb Upgrade 5
Introduction: Current mode preamplifier
• Pros:– “Natural” current processing
– Lower supply voltage
– All low impedance nodes:
• Pickup rejection
– No external components
– No extra pad
• Cons:– Trade-off in current mirrors: linearity
vs bandwidth
• Low voltage– Only 1 Vbe for the super common
base input stage
• Better in terms of ESD:– No input pad connected to any
transistor gate or base
MP2MP1
Q1
Re
Ib1 MN2
MP4MP3
MN1
Rf
Vee
Vcc
1 : K : mK : mK
Ib2
Ii
Io ∫
∫
I I
Current amplifier (mirrors)
TH
TH
AnalogueMultiplexer
Drv
ADC driver
Inner loop: lower input impedance
Outer loop: control input impedance
fem
i mRK
K
K
RgZ
11
1 1
10/December/2010 LHCb Upgrade 6
Introduction: Integrator
• Switched integrator architecture
+
-
-
+
In+
In-Out+
Out-
FDOA
FDOA specifications
Parameter Value
Gain bandwidth
500 MHz
Phase margin > 65º
Slew rate > 2 V/μs
VCM 1.65 V
CMOS switches
10/December/2010 LHCb Upgrade 7
M
M
Vin+
M
Vcas
VrefCE
Vout+
M
M
M
M
Vin-
M
Vcas
VrefCE
Vout-
M
MM
M
Vcmref
M
M
Vb1
Vb2 Vb2Vb2
Vb1
Vb2
Introduction: FDOA design
• Fully differential Operational Amplifier
Folded cascode
NPN CE amp
Pole compensation
RDegenertion
Common Mode
Feedback
10/December/2010 LHCb Upgrade 8
Key tests on the first prototype
• The purpose of this prototype is to test key points of a novel circuit idea:– Input impedance control by current feedback
– Low noise performance
– Dynamic range:
• Linearity
• Also to test critical aspects of a switched solution:– Offset between subchannels
– Noise
– “Flatness” of the integrator output• Effect of jitter on clock versus signal
• Finally, the two key building blocks are prototyped separately in order to be characterized: – Current preamplifier
– Fully differential OpAmp
10/December/2010 LHCb Upgrade 9
SCOPE
AWG2021 50 Ohms
50
cm
10m
IN OUT
ICECALDiff
ere
ntia
l P
robe
Differential Probe
50 Ohms
Test set-up
Tektronix AWG2021 Waveform Generator:
•250 MS/s•12 bit
50Ω || 50Ω = 25Ω ⇨ emulate clipping impedance
Tektronix TDS7154B Oscilloscope:
•BW = 1.7 GHz•20 GS/s•8 bit
Differential probe:•BW = 400 MHz•Cin = 1 pF
10/December/2010 LHCb Upgrade 10
Test set-up
AWG signal
50 470
1uF
1uF
ICECALIN
sbch1
sbch2
INT
INT_BAR
CLOCKPCB
Input circuit with AC coupling and Rpar
Integrator clock signals generated with comparator
Outputs are measured at ASIC outputs and after x10 amplification
10/December/2010 LHCb Upgrade 11
Test set-up
10/December/2010 LHCb Upgrade 12
Offset
Offset measurement:
V at cycle end
2 ns
V offset
Preamp current offset is integrated
=> Offset at output
10/December/2010 LHCb Upgrade 13
Offset
• About 5 % of the full scale range (2 V)• Slight asymmetry between subchanels (clock)
Distribution of the offset (12 chips)
0
1
2
3
4
5
6
7
-200 -160 -120 -80 -40 0 40 80 120 160 200
Offset [mV]
Entr
ies
Subch1Subch2Total
Subch Mean
[mV]
Std Dev
[mV]
1 27 20
2 34 35
5 % of dynamics
10/December/2010 LHCb Upgrade 14
Distribution of offset difference between subchannels
0
0,5
1
1,5
2
2,5
3
3,5
-100 -80 -60 -40 -20 0 20 40 60 80 100
Offset difference [mV]
Entr
ies
Diff Subch1-Subch2
ABS (Diff Subch1-Subch2)
Offset
• With AC coupling between ICECAL and ADC what really matters is the difference between the offset of the 2 subchannels
• Well below the 5 % of the full scale range (2 V)
• Zin a little higher than 50Ω • Rp used to fine tune Zin
10/December/2010 LHCb Upgrade 23
SCOPE
AWG2021
50 Ohms50
cm
10m
IN OUT
ICECALDiff
eren
tial
Pro
be
Differential Probe
50 Ohms
Input impedance
IC in
put s
igna
l
(PC
B)INT
Waveform Generator
Source signal
sbch
1sb
ch2
10/December/2010 LHCb Upgrade 24
SCOPE
AWG2021
50 Ohms50
cm
10m
IN OUT
ICECALDiff
eren
tial
Pro
be
Differential Probe
50 Ohms
Input impedance
IC in
put s
igna
l
(PC
B)INT
Waveform Generator
Source signal
sbch
1sb
ch2
ICECAL OFF
Large reflections
10/December/2010 LHCb Upgrade 25
Input impedance
Source (AWG)
IC input (PCB)
Out sbch1Out sbch2
INT
Reflection coefficients
Reflection Coefficients for source, IC input, and output signals.
Refl. Coeff. = 1st pulse integral / 2nd pulse integral
10/December/2010 LHCb Upgrade 26
Input impedance
• Optimal Rp is between 360 and 390 ohm• Dynamic variation of input impedance is << 1 % for full dynamic (50 pC)• Measurement error for second reflection is quite high for low amplitudes