1 Building Larger Circuits Building Larger Circuits Today: • First Hour: Combinational Building Combinational Building Blocks Blocks – Section 4.1 of Katz’s Textbook – In-class Activity #1 • Second Hour: Tri-state and Open Collector Gates, ROMs. • Section 4.2 of Katz’s Textbook – In-class Activity #2
Building Larger Circuits. Today: First Hour : Combinational Building Blocks Section 4.1 of Katz’s Textbook In-class Activity #1 Second Hour : Tri-state and Open Collector Gates, ROMs. Section 4.2 of Katz’s Textbook In-class Activity #2. - PowerPoint PPT Presentation
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Building Larger CircuitsBuilding Larger Circuits
Today:• First Hour: Combinational Building BlocksCombinational Building Blocks
– Section 4.1 of Katz’s Textbook
– In-class Activity #1
• Second Hour: Tri-state and Open Collector Gates, ROMs.
• Section 4.2 of Katz’s Textbook
– In-class Activity #2
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Recap:Recap:
• To simplify large Boolean functions, we use logic minimization software (espresso)
• We can use multi-level minimization when speed is not a problem.
• Use Programmable Logic Arrays to implement large circuits in an automated manner.
Today:
We’ll learn about another tool for building large circuits:
higher-level building blocks (modules).
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Building BlocksBuilding Blocks
MUX MUX
DEMUX
A B
Sum
A0 A1 B0 B1
Sa Sb
Ss
S0 S1
The Idea:Assemble your system using generic “building blocks.”
Examples:
PLA
Adder,
Multiplexor,
De-multiplexor,
Decoder,
Encoder
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A 2:1 MultiplexorA 2:1 Multiplexor
• TerminologyTerminology
– II00 and I and I11 are are input linesinput lines– Z is the Z is the output lineoutput line– A is the A is the control signalcontrol signal
2:1 MUX
I 0
I 1
A
Z
A Z
0 I0
1 I1
• Truth TableTruth Table
Boolean Function:
Z = A' I0 + A I1
Boolean Function:
Z = A' I0 + A I1
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Expanded Truth TableExpanded Truth Table
A Z
0 I0
1 I1
I1 I0 A Z
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
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Larger MUXesLarger MUXes2:1 MUX
I 0
I 1
A
Z
I 0
A
I 1 I 2 I 3
B
Z 4:1 MUX
I 0
A
I 1 I 2 I 3
B
Z 8:1
MUX
C
I 4 I 5 I 6
I 7
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Cascading MUXesCascading MUXes
4:1 MUX
4:1 MUX
8:1 MUX
2:1 MUX
0 1 2 3
0 1 2 3
S
S 1
S 0
S 1
S 0
Z
A C B
I 0
I 1
I 2
I 3
I 4
I 5
I 6
I 7
0
1
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Implementing Logic with MUXImplementing Logic with MUX
• 22n-1n-1 :1 :1 multiplexor can implement any Boolean function of nn variables
• needs n-1n-1 control variables; the remaining variable is used as a data input to the multiplexor
• Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1)
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ExampleExampleA 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
F 1 0 1 0 0 0 1 1
C
C
0
1 S1 S0
A B
4:1 MUX
0 1 2 3
C
C01
F
8:1 MUX
1 0 1 0 0 0 1 1
0 1 2 3 4 5 6 7 S2 S1 S0
A B C
F
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De-multiplexors (DMUX)De-multiplexors (DMUX)
• Decoder:Decoder: single data input, nn control inputs, 22nn outputs
• control inputs (called selects SS) represent binary binary indexindex of output to which the input is connected
• data input usually called "enable" (GG)
• Usually Enable = G = 1
Opposite of MUX, also called DecodersOpposite of MUX, also called Decoders
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2:4 DMUX2:4 DMUX
Select0 Select1
Output2
Output3
Output0
Enable
Output1
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DMUX as a Logic BlockDMUX as a Logic Block
3:8DMUX
(decoder)
0 1
2 3 4 5 6 7
A B C
Enable
A B C A B C A B C A B C A B C A B C
A B C A B C S 2 S 1 S 0
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ExampleExample
F1 = A B C D + A B C D + A B C DF2 = A B C D + A B CF3 = (A + B + C + D)
Implement the following 4-input, 3-output Boolean
function using a decoder (DMUX):
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A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D A B C D
A B C D A B C D A B C D A B C D
0 1 2 3 4 5 6 7 8 9
10 1 1 12 13 14 15
A
S 3 S 2 S 1 S 0
4:16 decoder
Enb = 1
B C D
F 1
F 3
F 2
DCBADCBADCBAF1
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Do Activity #1 NowDo Activity #1 Now
Get to know MUX and DMUX building Get to know MUX and DMUX building blocksblocks
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New Kinds of Gates, New Kinds of Gates, Read-only MemoryRead-only Memory
• New Kinds of Gates, “wired logic”:– 3-state output gates
The output of an open collector gate is like a switch connected to ground
output for logic “1”output for logic “1” output for logic “0”output for logic “0”
I.C.I.C. I.C.I.C.
Note: If you put a logic probe on an unconnected open-collector pin, it will indicate a logic 0 or nothing.
Note: If you put a logic probe on an unconnected open-collector pin, it will indicate a logic 0 or nothing.
Another way to connect multiple gates to the same output wireAnother way to connect multiple gates to the same output wire
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Pull-up ResistorsPull-up Resistors
I.C.
+5V
Resistors: 1 - 10 k typical
I.C.
+5V
Y = 0Y = 1
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Two Gates and a ResistorTwo Gates and a Resistor
Y becomes 0 when any one switch is closedY becomes 0 when any one switch is closedY becomes 0 when any one switch is closedY becomes 0 when any one switch is closed
+5V
Y
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Wired LogicWired Logic
If A and B are If A and B are 11, Output is actively pulled low, Output is actively pulled low
If C and D are If C and D are 11, Output is actively pulled low, Output is actively pulled low
If one gate is low and the other high, then If one gate is low and the other high, then low winslow wins
If both gates are If both gates are 11, the , the Output floatsOutput floats. Pull it high with a . Pull it high with a resistorresistor
If A and B are If A and B are 11, Output is actively pulled low, Output is actively pulled low
If C and D are If C and D are 11, Output is actively pulled low, Output is actively pulled low
If one gate is low and the other high, then If one gate is low and the other high, then low winslow wins
If both gates are If both gates are 11, the , the Output floatsOutput floats. Pull it high with a . Pull it high with a resistorresistor
Special symbol on OC gates: output
bar
Special symbol on OC gates: output
bar
OutputA
B
C
D
+5V
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Output = (A B + C D)'
= (A B)' (C D)'
= (A' + B')(C' +D')
= A' C' + A' D' + B' C' +B' D'
So What’s the Big Idea??So What’s the Big Idea??
Wired Logic !! What is Output(A,B,C,D)?
Click for answer
Wired Logic !! What is Output(A,B,C,D)?
Click for answer
If A and B are If A and B are 11, Output is actively pulled low, Output is actively pulled low
If C and D are If C and D are 11, Output is actively pulled low, Output is actively pulled low
If one gate is low and the other high, then If one gate is low and the other high, then low winslow wins
If both gates are If both gates are 11, the , the Output is pulled up to logic 1Output is pulled up to logic 1. .
If A and B are If A and B are 11, Output is actively pulled low, Output is actively pulled low
If C and D are If C and D are 11, Output is actively pulled low, Output is actively pulled low
If one gate is low and the other high, then If one gate is low and the other high, then low winslow wins
If both gates are If both gates are 11, the , the Output is pulled up to logic 1Output is pulled up to logic 1. .
OutputA
B
C
D
+5V
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Another Practical IssueAnother Practical IssueUseful for lighting Light Emitting Diodes (LEDs)Useful for lighting Light Emitting Diodes (LEDs)
X
+5V
R
I.C.I.C.
What happens to the LED What happens to the LED when X = 1?when X = 1?
When X = 0? When X = 0?
Click for the answerClick for the answer
What happens to the LED What happens to the LED when X = 1?when X = 1?
When X = 0? When X = 0?
Click for the answerClick for the answer
No current = OFFNo current = OFF
Current = ONCurrent = ON
No current = OFFNo current = OFF
Current = ONCurrent = ON
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Read-Only MemoriesRead-Only Memories
Memory Array
2nwords by m bits
m outputlines
n addresslines
Decoder 2n wordlines
Sort of like a PLAstructure with afully decodedfully decoded
AND array!
Sort of like a PLAstructure with afully decodedfully decoded
AND array!
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Applications of ROMsApplications of ROMs
Store data in a non-volatilenon-volatile manner
Like PLA’s, you can buy programmable ROMs (PROMs)
Implement combinational functions
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ROM vs. PLA ROM vs. PLA
ROM advantageous whenROM advantageous when • design time is short (no need to minimize output functions)• most input combinations are needed (e.g., code converters)• little sharing of product terms among output functions
Downside:Downside: • size doubles for each additional input• can't use don't cares
PLA advantageous whenPLA advantageous when• design tool like espresso is available• there are relatively few unique minterm combinations• many shared minterms among the output functions
Downside:Downside: constrained fan-ins on OR arrays
combinational functionscombinational functions
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Questions:Questions:
• How many words?
• How many bits in each word?
• How many bits overall?
• Click for answer
Questions:Questions:
• How many words?
• How many bits in each word?
• How many bits overall?
• Click for answer
ROM ExampleROM Example2764
A0A1A2A3A4A5A6A7A8A9
O0O1O2O3O4O5O6O7
OECS
PGM
A10A11A12
A0A1A2A3A4A5A6A7A8A9
O0O1O2O3O4O5O6O7
OECS
PGMVPP
A10A11A12
DATADATALINESLINES(tri-state)(tri-state)
ADDRESSLINES
OUTPUT ENABLE
CHIP SELECT
213 = 8K = 8 192
8
216 = 64K = 65 536
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Choices, choices ...Choices, choices ...You can implement logic functions many ways:You can implement logic functions many ways:
Existence of alternatives no clear winnerExistence of alternatives no clear winner
Discrete gatesAND/ORNAND/NAND
PLAs or PALsMuxesDemuxes (decoders)ROMs
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Do Activity #2 NowDo Activity #2 NowDue: End of Class Today
RETAIN THE LAST PAGE (#3)!!
For Next Class:• Bring Randy Katz Textbook, & TTL Data Book
• Required Reading:– Sec 5.1 of Katz
• This reading is necessary for getting points in the Studio Activity!