1 ECE 3445 Computer Architecture Lecture 10 & 11 Building a Single-Cycle MIPS Processor: Datapth Dr. X. Wang ECE@Villanova 2 Three Classic Components of a Computer The Big Picture: What is Coming? Control Datapath Memory Processor Input Output 4 7 1001010010110000 0010100101010001 0111011101100110 1000010100110000 1001010010110000 1001010010110000 0011001011110000 1011011101100110 1001010010110000 1111011101100110 1001010010110000 1111011101100110 5 1011011101100110 6 • datapath deals with moving data around • Control generates signals to control proper operation of datapath
Lecture about Single-Cycle MIPS processors. Provides detailed overview of the datapath. Great resource for computer and electrical engineering students.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
• datapath deals with moving data around • Control generates signals to control proper operation
of datapath
2
Formal Definition: Datapath and Control Unit
3
Control Unit The component that decodes instructions and generates control signals to command proper operations of datapath, memory, and I/O devices
Datapath The collection of state elements, computation elements, and interconnections that together provide a conduit for the flow and transformation of data in the processor during execution
4
Overview of Chapter 4
q Implementation of the MIPS Processor: DataPath and Control Unit – We’ve built a small ALU – How the processor is designed and implemented to execute
instructions q Datapath and control
– Three different implementations will be examined • A single-cycle processor • A multi-cycle processor (not included in the 4th edition of textbook) • A pipelined processor
q Outcome of this chapter – You will be able to design and implement your own
processor that executes your own instructions
3
5
General Processor Operation Steps (von Neumann model)
q A processor uses 3 steps to execute an instruction: 1. Use the program counter (PC) to supply the instruction address and fetch
the instruction from memory (and update the PC) 2. Decode the instruction (and read registers) in the processor 3. Execute the instruction in the processor
1. Analyze instruction set -> datapath requirements – meaning of each instruction is given by the register transfer operations – datapath must include storage elements for ISA registers – datapath must support each register transfer
2. Select a set of datapath components and establish clocking methodology
3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to
determine setting of control points that effects the register transfer.
5. Design the control logic unit
8
Step 1a: Analyze the MIPS Instruction Subset (Use Handout 2)
1. ADD and SUB – addu rd, rs, rt – subu rd, rs, rt
2. OR Immediate: – ori rt, rs, imm16
3. LOAD and STORE – lw rt, imm16(rs) – sw rt, imm16(rs)
4. BRANCH: – beq rs, rt, imm16
5. Jump – j imm26
op rs rt rd shamt funct 0 6 11 16 21 26 31
6 bits 6 bits 5 bits 5 bits 5 bits 5 bits
op rs rt immediate 0 16 21 26 31
6 bits 16 bits 5 bits 5 bits
op rs rt immediate 0 16 21 26 31
6 bits 16 bits 5 bits 5 bits
op target address
0 26 31
6 bits 26 bits
op rs rt immediate 0 16 21 26 31
6 bits 16 bits 5 bits 5 bits
(rd)
5
9
Step 1b: Logical Register Transfers q All start by fetching the instruction
Instruction <- MEM[PC]
q Execution
Instr. Register Transfers ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4
SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4
AND R[rd] <– R[rs] & R[rt]; PC <– PC + 4
ORI R[rt] <– R[rs] | zero_ext(Imm16); PC <– PC + 4
LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4
STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4
BEQ if ( R[rs]==R[rt]) then PC <– PC+4+sign_ext(Imm16)||00 else
q Memory – Store and supply instructions (instruction memory)
– Read and Write Data (data memory)
q PC (program counter)
q Registers - 32 – read (from rs field in instruction) – read (from rt field in instruction)
– write (from rd or rt field in instruction)
q Sign Extender q Add, Subtract, OR, AND (register values) -> ALU q Add 4 or extended immediate to PC
Combinational Logic: Outputs are always just a logic function of its inputs (with some delay) No clock
Sequential Circuits: input written at the rising or falling edge of a clock cycle.
6
11
Step 2: Select Datapath Components: Memory and PC
q Memory
q PC (Program Counter)
Address Instruction
Instruction Memory
Address Read Data
Write Data
MemWrite
MemRead
Data Memory
PC ***Blue signals represent control
signals from control unit
12
Step 2: Select Datapath Components: Registers q Similar to the D Flip Flop except
– N-bit input and output – Write Enable input
• invalid (deasserted): Data Out will not change • valid (asserted): Data Out will become Data In on the
clock edge
Clk
Data In
Write Enable
N N Data Out
7
13
Step 2: Select Datapath Components: Register File
q 32 registers in MIPS are organized as a group called register file
q Register file consists of 32 regs: – Two 32-bit output busses: Read data 1 and Read data 2 (why?) – One 32-bit input bus: Write Data
q Register is selected by: – 5-bit Read reg. 1 (number) selects the register to output on Read data 1 – 5-bit Read reg. 2 (number) selects the register to output on Read data 2 – 5-bit Write reg. (number) selects the register to be written
via Write Data when RegWrite is 1
Read Register1
Read Register2
Write Register
Read Data1
Read Data2
Write Data
RegWrite Clock
5
5
5
32
32
32
Read Port
14
Write Port
8
15
Step 2: Selecting Datapath Components: more q ALU
q Sign Extender
q Add 4 or extended immediate to PC q Multiplexers
32 B
32 A
32 ALU Result
ALU Operation
ALU
Zero
4
16 32 Sign
extend
Adder"
32
32 ADD
4
Overflow
Carryout Negative
16
Step 3: Assemble DataPath Meeting Requirements
q We need to “glue” the components together to construct a datapath that allows data to move around among the components according the needs of the instruction.
q The data moving around in datapath include: – Register values – Memory values – ALU results – The program counter
q We combine the function units with wires and multiplexers q How? Trace the instructions and resolve conflicts
9
17
Fetching Instructions
q Fetching instructions involves 1. Reading an instruction from the Instruction Memory
2. Updating the PC to hold the address of the next instruction
Instruction Memory
Read Address Instruction PC
register
Add
4
Updated every cycle; no need for an explicit write signal
– Sending the fetched instruction’s opcode and function field bits to the control unit
– Reading two values from the Register File • Register File addresses are contained in the instruction
Instruction (from the fectch stage) Write Data
Read Addr 1
Read Addr 2
Write Addr
Register File
Read Data 1
Read Data 2
Control Unit
op rs rt rd shamt funct
10
19
Execution Stage q The action depends on the instruction class:
– Similarities across instruction classes:
– e.g., all instructions (except j) use the ALU after reading the registers.
• Memory-reference: use ALU to calculate addresses • Arithmetic: operation execution • Branches: comparison
– Simplicity and regularity of instructions simplifies the implementation of a processor
– After using the ALU, actions differ… • Memory-reference: access data memory • Arithmetic: write result back to register file • Branches: may need to update the PC with the final address based on
1. Analyze instruction set -> datapath requirements – the meaning of each instruction is given by the register transfers – datapath must include storage element for ISA registers – datapath must support each register transfer
2. Select a set of datapath components and establish clocking methodology
3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to
determine setting of control points that effects the register transfer.