05 MIPS CPU Simple Datapath - Washington State University

CptS 260Intro to Computer Architecture

Week 5.1Mon 2013/09/16

MIPS CPU:

Simple Datapath

MIPS CPU: Simple Datapath

• 1 cycle perinstruction

Reading Assignment

• [P&H12] Chapter 4 The Processor

– §4.1 Introduction– §4.2 Logic Design Conventions– §4.3 Building a Datapath– §4.4 A Simple Implementation Scheme

MIPS Assembly:Instruction Bitfields and Instruction Types

• R-type arithmetic-logical add, sub, srl, sll“3-register” and, or, xor

• I-type arithmetic-logical addi, ori, …“immediate” branch beq, bne, …

load / store lw/lh/lb, sw/sh/sb• J-type jump j, jal, jalr

bits

type 6 5 5 5 5 6

R-type op rs rt rd shamt funct

I-type op rs rt 16-bit immediate

J-type op 26-bit address

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

Simple Datapath : Program Counter $pc

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

• Default action:$pc += 4 (bytes)

• Instruction memory “separate from”data memory

Instruction Types Imply the Datapath

6 5 5 5 5 6

R op rs rt rd shamt funct

I (arith) op rs rt 16-bit immediate

I (ld/st) op rs rt 16-bit immediate

I (branch) op rs rt 16-bit immediate

J op 26-bit address

MIPS Memory Layout

Registers

MemorySegments

(layout)

directives

Memory

.data

$pc

$ra

$t0 – $t9

$s0 – $s7user

Bit storage

instructions

address

0x0040 0000

0x1001 0000

0x8000 0180

0xFFFF 0000

.text

value

.data

.text

.kernel

0x7FFF EFFC stacklocals $sp

…

MIPS Segments and Directives

0x0040 0000

0x1001 0000

.data

.text

.dataA: .word 0B: .byte ‘b’

.textnop…

.dataQ: .word 0

.textsw $sp, Q # save……

.data…

.text……

In your .asm :• Interleave freely

In the .exe:• Compiler

rearranges (automatically)

• “Next available address”

• Contiguous(with alignment)

your.asm

MIPS Segments and Memory

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

.data

.text

.kernel

stack

Program Counter $pc (Is a Pointer!)

$pc

if (t1 == t2)++t2;

else--t1;

nop;

bne $t1, $t2, Elseaddi $t2, $t2, 1j Eh

Else:addi $t1, $t1, –1

Eh:nop

bne0000

0x0040:

addi0004

j0008

000c

0x0040 0010

$t1 $t2 +0xc (bytes)

$t2$t2 0x0001

addi $t1$t1 0xffff

0010 nop

0x0040 0008

32 bits

• Changing $pc is ���� a jump! (goto)• And vice versa

.text

Munging $pc: Jump and Branch

bne0000

addi0004

j0008

000c

0x0040 0010

$t1 $t2 +0xc (bytes)

$t2$t2 0x0001

addi $t1$t1 0xffff

0010 nop

• default $pc += 4 bytes• jump $pc = 26-bit address

• branch $pc += 16-bit offset .text

CptS 260Intro to Computer Architecture

Week 5.2Wed 2013/09/18

MIPS CPU:

Simple Datapath

R-type: 3 registers

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

• 2 ALU operands• 1 dest. register

• funct field determines ALU operation

1000

001

control line must be ‘1’to set multiplexor

rsrt

rd

funct

I-type: Arithmetic

• addi rt, rs, imm

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

(shown in class!)

I-type: Load/Store

lw $ rt , imm ($rs)• rt ����Write register• MemRead• MemToReg, RegWrite

sw $ rt , imm ($rs)• rt ���� Read register 2• Read data 2 ���� DM• MemWrite

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

00

1/01/0

0/11

1/0

rsrt

large dots are electrical junctions

(choice points)

16-bit offset(2nd operand)

no dot meansdisconnected

lwsw

I-type: Branch

beq rs, rt, LABEL• same for b, ble/bge,

blt/bgt, beqz/bnez, etc.

• LABEL is 16-bit offset relative to ($pc + 4)���� branch limited to16-bit range

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

0100

000

rsrt

16-bit LABEL

( )

( )

CptS 260Intro to Computer Architecture

Week 5.3Fri 2013/09/20

MIPS CPU:

Main Control and ALU Control

MIPS CPU: Implementing the Control

• [P&H12] Chapter 4 The Processor– §4.4 A Simple Implementation Scheme

Simple Implementation Scheme:ALU Control

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

(caveat: for a subset of MIPS)

ALUcontrol Function

0000 AND

0001 OR

0010 add

0110 subtract

0111 set on less than

1100 NOR

else “not in book”

6 5 5 5 5 6

R op rs rt rd shamt funct

I op rs rt 16-bit immediate

J op 26-bit address

Simple Implementation Scheme:Main Control

op ALUop funct ALU ALUctrl

R add 10 100000 + 0010

R (arith.) 10 (B-10) … (p.316)

I (arith.) ? … (p.316)

I load 00 + 0010

I store 00 + 0010

I branch 01 – 0110

J jump