-
8-bit Microcontroller with 4/8/16/32K Bytes
In-SystemProgrammable Flash
ATmega48PAATmega88PAATmega168PAATmega328P
Rev. 8161DAVR10/09Features High Performance, Low Power AVR 8-Bit
Microcontroller Advanced RISC Architecture
131 Powerful Instructions Most Single Clock Cycle Execution 32 x
8 General Purpose Working Registers Fully Static Operation Up to 20
MIPS Throughput at 20 MHz On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments 4/8/16/32K Bytes of
In-System Self-Programmable Flash progam memory
(ATmega48PA/88PA/168PA/328P) 256/512/512/1K Bytes EEPROM
(ATmega48PA/88PA/168PA/328P) 512/1K/1K/2K Bytes Internal SRAM
(ATmega48PA/88PA/168PA/328P) Write/Erase Cycles: 10,000
Flash/100,000 EEPROM Data retention: 20 years at 85C/100 years at
25C(1) Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot ProgramTrue
Read-While-Write Operation
Programming Lock for Software Security Peripheral Features
Two 8-bit Timer/Counters with Separate Prescaler and Compare
Mode One 16-bit Timer/Counter with Separate Prescaler, Compare
Mode, and Capture
Mode Real Time Counter with Separate Oscillator Six PWM Channels
8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement 6-channel 10-bit ADC in PDIP Package
Temperature Measurement Programmable Serial USART Master/Slave
SPI Serial Interface Byte-oriented 2-wire Serial Interface (Philips
I2C compatible) Programmable Watchdog Timer with Separate On-chip
Oscillator On-chip Analog Comparator Interrupt and Wake-up on Pin
Change
Special Microcontroller Features Power-on Reset and Programmable
Brown-out Detection Internal Calibrated Oscillator External and
Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise
Reduction, Power-save, Power-down, Standby,
and Extended Standby I/O and Packages
23 Programmable I/O Lines 28-pin PDIP, 32-lead TQFP, 28-pad
QFN/MLF and 32-pad QFN/MLF
Operating Voltage: 1.8 - 5.5V for ATmega48PA/88PA/168PA/328P
Temperature Range: -40C to 85C
Speed Grade: 0 - 20 MHz @ 1.8 - 5.5V
Low Power Consumption at 1 MHz, 1.8V, 25C for
ATmega48PA/88PA/168PA/328P: Active Mode: 0.2 mA Power-down Mode:
0.1 A Power-save Mode: 0.75 A (Including 32 kHz RTC)
-
ATmega48PA/88PA/168PA/328P1. Pin ConfigurationsFigure 1-1.
Pinout ATmega48PA/88PA/168PA/328P
12345678
2423222120191817
(PCINT19/OC2B/INT1) PD3(PCINT20/XCK/T0) PD4
GNDVCCGNDVCC
(PCINT6/XTAL1/TOSC1) PB6(PCINT7/XTAL2/TOSC2) PB7
PC1 (ADC1/PCINT9)PC0 (ADC0/PCINT8)ADC7GNDAREFADC6AVCCPB5
(SCK/PCINT5)
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
(PCI
NT21
/OC0
B/T1
) PD5
(PCI
NT22
/OC0
A/AI
N0) P
D6(P
CINT
23/A
IN1)
PD7
(PCI
NT0/C
LKO
/ICP1
) PB0
(PCI
NT1/O
C1A)
PB1
(PCI
NT2/S
S/OC
1B) P
B2(P
CINT
3/OC2
A/MO
SI) P
B3(P
CINT
4/MIS
O) P
B4
PD2
(INT0
/PCI
NT18
)PD
1 (T
XD/P
CINT
17)
PD0
(RXD
/PCI
NT16
)PC
6 (R
ESET
/PCI
NT14
)PC
5 (A
DC5/S
CL/P
CINT
13)
PC4
(ADC
4/SDA
/PCI
NT12
)PC
3 (A
DC3/P
CINT
11)
PC2
(ADC
2/PCI
NT10
)
TQFP Top View
1234567891011121314
2827262524232221201918171615
(PCINT14/RESET) PC6(PCINT16/RXD) PD0(PCINT17/TXD)
PD1(PCINT18/INT0) PD2
(PCINT19/OC2B/INT1) PD3(PCINT20/XCK/T0) PD4
VCCGND
(PCINT6/XTAL1/TOSC1) PB6(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5(PCINT22/OC0A/AIN0) PD6
(PCINT23/AIN1) PD7(PCINT0/CLKO/ICP1) PB0
PC5 (ADC5/SCL/PCINT13)PC4 (ADC4/SDA/PCINT12)PC3
(ADC3/PCINT11)PC2 (ADC2/PCINT10)PC1 (ADC1/PCINT9)PC0
(ADC0/PCINT8)GNDAREFAVCCPB5 (SCK/PCINT5)PB4 (MISO/PCINT4)PB3
(MOSI/OC2A/PCINT3)PB2 (SS/OC1B/PCINT2)PB1 (OC1A/PCINT1)
PDIP
12345678
2423222120191817
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
32 MLF Top View
(PCINT19/OC2B/INT1) PD3(PCINT20/XCK/T0) PD4
GNDVCCGNDVCC
(PCINT6/XTAL1/TOSC1) PB6(PCINT7/XTAL2/TOSC2) PB7
PC1 (ADC1/PCINT9)PC0 (ADC0/PCINT8)ADC7GNDAREFADC6AVCCPB5
(SCK/PCINT5)
(PCI
NT21
/OC0
B/T1
) PD5
(PCI
NT22
/OC0
A/AI
N0) P
D6(P
CINT
23/A
IN1)
PD7
(PCI
NT0/C
LKO
/ICP1
) PB0
(PCI
NT1/O
C1A)
PB1
(PCI
NT2/S
S/OC
1B) P
B2(P
CINT
3/OC2
A/MO
SI) P
B3(P
CINT
4/MIS
O) P
B4
PD2
(INT0
/PCI
NT18
)PD
1 (T
XD/P
CINT
17)
PD0
(RXD
/PCI
NT16
)PC
6 (R
ESET
/PCI
NT14
)PC
5 (A
DC5/S
CL/P
CINT
13)
PC4
(ADC
4/SDA
/PCI
NT12
)PC
3 (A
DC3/P
CINT
11)
PC2
(ADC
2/PCI
NT10
)
NOTE: Bottom pad should be soldered to ground.
1234567
21201918171615
28 27 26 25 24 23 22
8 9 10 11 12 13 14
28 MLF Top View
(PCINT19/OC2B/INT1) PD3(PCINT20/XCK/T0) PD4
VCCGND
(PCINT6/XTAL1/TOSC1) PB6(PCINT7/XTAL2/TOSC2) PB7
(PCINT21/OC0B/T1) PD5
(PCI
NT22
/OC0
A/AI
N0) P
D6(P
CINT
23/A
IN1)
PD7
(PCI
NT0/C
LKO
/ICP1
) PB0
(PCI
NT1/O
C1A)
PB1
(PCI
NT2/S
S/OC
1B) P
B2(P
CINT
3/OC2
A/MO
SI) P
B3(P
CINT
4/MIS
O) P
B4
PD2
(INT0
/PCI
NT18
)PD
1 (T
XD/P
CINT
17)
PD0
(RXD
/PCI
NT16
)PC
6 (R
ESET
/PCI
NT14
)PC
5 (A
DC5/S
CL/P
CINT
13)
PC4
(ADC
4/SDA
/PCI
NT12
)PC
3 (A
DC3/P
CINT
11)
PC2 (ADC2/PCINT10)PC1 (ADC1/PCINT9)PC0
(ADC0/PCINT8)GNDAREFAVCCPB5 (SCK/PCINT5)
NOTE: Bottom pad should be soldered to ground.28161DAVR10/09
-
ATmega48PA/88PA/168PA/328P1.1 Pin Descriptions
1.1.1 VCCDigital supply voltage.
1.1.2 GNDGround.
1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2Port B is an 8-bit
bi-directional I/O port with internal pull-up resistors (selected
for each bit). ThePort B output buffers have symmetrical drive
characteristics with both high sink and sourcecapability. As
inputs, Port B pins that are externally pulled low will source
current if the pull-upresistors are activated. The Port B pins are
tri-stated when a reset condition becomes active,even if the clock
is not running.
Depending on the clock selection fuse settings, PB6 can be used
as input to the inverting Oscil-lator amplifier and input to the
internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used
as output from the invertingOscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock
source, PB7..6 is used as TOSC2..1input for the Asynchronous
Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in
Alternate Functions of Port B on page82 and System Clock and Clock
Options on page 26.
1.1.4 Port C (PC5:0)Port C is a 7-bit bi-directional I/O port
with internal pull-up resistors (selected for each bit). ThePC5..0
output buffers have symmetrical drive characteristics with both
high sink and sourcecapability. As inputs, Port C pins that are
externally pulled low will source current if the pull-upresistors
are activated. The Port C pins are tri-stated when a reset
condition becomes active,even if the clock is not running.
1.1.5 PC6/RESETIf the RSTDISBL Fuse is programmed, PC6 is used
as an I/O pin. Note that the electrical char-acteristics of PC6
differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset
input. A low level on this pinfor longer than the minimum pulse
length will generate a Reset, even if the clock is not running.The
minimum pulse length is given in Table 28-3 on page 318. Shorter
pulses are not guaran-teed to generate a Reset.
The various special features of Port C are elaborated in
Alternate Functions of Port C on page85.
1.1.6 Port D (PD7:0)Port D is an 8-bit bi-directional I/O port
with internal pull-up resistors (selected for each bit). ThePort D
output buffers have symmetrical drive characteristics with both
high sink and sourcecapability. As inputs, Port D pins that are
externally pulled low will source current if the pull-upresistors
are activated. The Port D pins are tri-stated when a reset
condition becomes active,even if the clock is not
running.38161DAVR10/09
-
ATmega48PA/88PA/168PA/328PThe various special features of Port D
are elaborated in Alternate Functions of Port D on page88.
1.1.7 AVCCAVCC is the supply voltage pin for the A/D Converter,
PC3:0, and ADC7:6. It should be externallyconnected to VCC, even if
the ADC is not used. If the ADC is used, it should be connected to
VCCthrough a low-pass filter. Note that PC6..4 use digital supply
voltage, VCC.
1.1.8 AREFAREF is the analog reference pin for the A/D
Converter.
1.1.9 ADC7:6 (TQFP and QFN/MLF Package Only)In the TQFP and
QFN/MLF package, ADC7:6 serve as analog inputs to the A/D
converter.These pins are powered from the analog supply and serve
as 10-bit ADC channels.48161DAVR10/09
-
ATmega48PA/88PA/168PA/328P2. OverviewThe
ATmega48PA/88PA/168PA/328P is a low-power CMOS 8-bit
microcontroller based on theAVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle,
theATmega48PA/88PA/168PA/328P achieves throughputs approaching 1
MIPS per MHz allowingthe system designer to optimize power
consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general
purpose working registers. All the32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two
independentregisters to be accessed in one single instruction
executed in one clock cycle. The resulting
PORT C (7)PORT B (8)PORT D (8)
USART 0
8bit T/C 2
16bit T/C 18bit T/C 0 A/D Conv.
InternalBandgap
AnalogComp.
SPI TWI
SRAMFlash
EEPROM
WatchdogOscillator
WatchdogTimer
OscillatorCircuits /
ClockGeneration
PowerSupervisionPOR / BOD &
RESET
VCC
GND
PROGRAMLOGIC
debugWIRE
2
GND
AREF
AVCC
DATA
BUS
ADC[6..7]PC[0..6]PB[0..7]PD[0..7]
6
RESET
XTAL[1..2]
CPU58161DAVR10/09
-
ATmega48PA/88PA/168PA/328Parchitecture is more code efficient
while achieving throughputs up to ten times faster than
con-ventional CISC microcontrollers.
The ATmega48PA/88PA/168PA/328P provides the following features:
4K/8K bytes of In-SystemProgrammable Flash with Read-While-Write
capabilities, 256/512/512/1K bytes EEPROM,512/1K/1K/2K bytes SRAM,
23 general purpose I/O lines, 32 general purpose working
registers,three flexible Timer/Counters with compare modes,
internal and external interrupts, a serial pro-grammable USART, a
byte-oriented 2-wire Serial Interface, an SPI serial port, a
6-channel 10-bitADC (8 channels in TQFP and QFN/MLF packages), a
programmable Watchdog Timer withinternal Oscillator, and five
software selectable power saving modes. The Idle mode stops theCPU
while allowing the SRAM, Timer/Counters, USART, 2-wire Serial
Interface, SPI port, andinterrupt system to continue functioning.
The Power-down mode saves the register contents butfreezes the
Oscillator, disabling all other chip functions until the next
interrupt or hardware reset.In Power-save mode, the asynchronous
timer continues to run, allowing the user to maintain atimer base
while the rest of the device is sleeping. The ADC Noise Reduction
mode stops theCPU and all I/O modules except asynchronous timer and
ADC, to minimize switching noise dur-ing ADC conversions. In
Standby mode, the crystal/resonator Oscillator is running while the
restof the device is sleeping. This allows very fast start-up
combined with low power consumption.
The device is manufactured using Atmels high density
non-volatile memory technology. TheOn-chip ISP Flash allows the
program memory to be reprogrammed In-System through an SPIserial
interface, by a conventional non-volatile memory programmer, or by
an On-chip Boot pro-gram running on the AVR core. The Boot program
can use any interface to download theapplication program in the
Application Flash memory. Software in the Boot Flash section
willcontinue to run while the Application Flash section is updated,
providing true Read-While-Writeoperation. By combining an 8-bit
RISC CPU with In-System Self-Programmable Flash on amonolithic
chip, the Atmel ATmega48PA/88PA/168PA/328P is a powerful
microcontroller thatprovides a highly flexible and cost effective
solution to many embedded control applications.
The ATmega48PA/88PA/168PA/328P AVR is supported with a full
suite of program and systemdevelopment tools including: C
Compilers, Macro Assemblers, Program Debugger/Simulators,In-Circuit
Emulators, and Evaluation kits.
2.2 Comparison Between ATmega48PA, ATmega88PA, ATmega168PA and
ATmega328PThe ATmega48PA, ATmega88PA, ATmega168PA and ATmega328P
differ only in memorysizes, boot loader support, and interrupt
vector sizes. Table 2-1 summarizes the different mem-ory and
interrupt vector sizes for the three devices.
ATmega88PA, ATmega168PA and ATmega328P support a real
Read-While-Write Self-Pro-gramming mechanism. There is a separate
Boot Loader Section, and the SPM instruction canonly execute from
there. In ATmega48PA, there is no Read-While-Write support and no
sepa-rate Boot Loader Section. The SPM instruction can execute from
the entire Flash.
Table 2-1. Memory Size SummaryDevice Flash EEPROM RAM Interrupt
Vector Size
ATmega48PA 4K Bytes 256 Bytes 512 Bytes 1 instruction
word/vectorATmega88PA 8K Bytes 512 Bytes 1K Bytes 1 instruction
word/vectorATmega168PA 16K Bytes 512 Bytes 1K Bytes 2 instruction
words/vectorATmega328P 32K Bytes 1K Bytes 2K Bytes 2 instruction
words/vector68161DAVR10/09
-
ATmega48PA/88PA/168PA/328P3. Resources A comprehensive set of
development tools, application notes and datasheets are available
fordownload on http://www.atmel.com/avr.Note: 1.
4. Data RetentionReliability Qualification results show that the
projected data retention failure rate is much lessthan 1 PPM over
20 years at 85C or 100 years at 25C.
5. About Code Examples This documentation contains simple code
examples that briefly show how to use various parts ofthe device.
These code examples assume that the part specific header file is
included beforecompilation. Be aware that not all C compiler
vendors include bit definitions in the header filesand interrupt
handling in C is compiler dependent. Please confirm with the C
compiler documen-tation for more details.
For I/O Registers located in extended I/O map, IN, OUT, SBIS,
SBIC, CBI, and SBIinstructions must be replaced with instructions
that allow access to extended I/O. TypicallyLDS and STS combined
with SBRS, SBRC, SBR, and CBR.78161DAVR10/09
-
ATmega48PA/88PA/168PA/328P6. AVR CPU Core
6.1 OverviewThis section discusses the AVR core architecture in
general. The main function of the CPU coreis to ensure correct
program execution. The CPU must therefore be able to access
memories,perform calculations, control peripherals, and handle
interrupts.
Figure 6-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a
Harvard architecture withseparate memories and buses for program
and data. Instructions in the program memory areexecuted with a
single level pipelining. While one instruction is being executed,
the next instruc-tion is pre-fetched from the program memory. This
concept enables instructions to be executedin every clock cycle.
The program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general
purpose working registers with a singleclock cycle access time.
This allows single-cycle Arithmetic Logic Unit (ALU) operation. In
a typ-
FlashProgramMemory
InstructionRegister
InstructionDecoder
ProgramCounter
Control Lines
32 x 8GeneralPurpose
Registrers
ALU
Statusand Control
I/O Lines
EEPROM
Data Bus 8-bit
DataSRAM
Dire
ct A
ddre
ssin
g
Indi
rect
Add
ress
ing
InterruptUnit
SPIUnit
WatchdogTimer
AnalogComparator
I/O Module 2
I/O Module1
I/O Module n88161DAVR10/09
-
ATmega48PA/88PA/168PA/328Pical ALU operation, two operands are
output from the Register File, the operation is executed,and the
result is stored back in the Register File in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect
address register pointers for DataSpace addressing enabling
efficient address calculations. One of the these address
pointerscan also be used as an address pointer for look up tables
in Flash program memory. Theseadded function registers are the
16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between
registers or between a constant anda register. Single register
operations can also be executed in the ALU. After an arithmetic
opera-tion, the Status Register is updated to reflect information
about the result of the operation.
Program flow is provided by conditional and unconditional jump
and call instructions, able todirectly address the whole address
space. Most AVR instructions have a single 16-bit word for-mat.
Every program memory address contains a 16- or 32-bit
instruction.
Program Flash memory space is divided in two sections, the Boot
Program section and theApplication Program section. Both sections
have dedicated Lock bits for write and read/writeprotection. The
SPM instruction that writes into the Application Flash memory
section mustreside in the Boot Program section.
During interrupts and subroutine calls, the return address
Program Counter (PC) is stored on theStack. The Stack is
effectively allocated in the general data SRAM, and consequently
the Stacksize is only limited by the total SRAM size and the usage
of the SRAM. All user programs mustinitialize the SP in the Reset
routine (before subroutines or interrupts are executed). The
StackPointer (SP) is read/write accessible in the I/O space. The
data SRAM can easily be accessedthrough the five different
addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and
regular memory maps.
A flexible interrupt module has its control registers in the I/O
space with an additional GlobalInterrupt Enable bit in the Status
Register. All interrupts have a separate Interrupt Vector in
theInterrupt Vector table. The interrupts have priority in
accordance with their Interrupt Vector posi-tion. The lower the
Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral
functions as Control Regis-ters, SPI, and other I/O functions. The
I/O Memory can be accessed directly, or as the DataSpace locations
following those of the Register File, 0x20 - 0x5F. In addition,
theATmega48PA/88PA/168PA/328P has Extended I/O space from 0x60 -
0xFF in SRAM whereonly the ST/STS/STD and LD/LDS/LDD instructions
can be used.
6.2 ALU Arithmetic Logic UnitThe high-performance AVR ALU
operates in direct connection with all the 32 general
purposeworking registers. Within a single clock cycle, arithmetic
operations between general purposeregisters or between a register
and an immediate are executed. The ALU operations are dividedinto
three main categories arithmetic, logical, and bit-functions. Some
implementations of thearchitecture also provide a powerful
multiplier supporting both signed/unsigned multiplicationand
fractional format. See the Instruction Set section for a detailed
description.
6.3 Status RegisterThe Status Register contains information
about the result of the most recently executed arithme-tic
instruction. This information can be used for altering program flow
in order to performconditional operations. Note that the Status
Register is updated after all ALU operations, as98161DAVR10/09
-
ATmega48PA/88PA/168PA/328Pspecified in the Instruction Set
Reference. This will in many cases remove the need for using
thededicated compare instructions, resulting in faster and more
compact code.
The Status Register is not automatically stored when entering an
interrupt routine and restoredwhen returning from an interrupt.
This must be handled by software.
6.3.1 SREG AVR Status RegisterThe AVR Status Register SREG is
defined as:
Bit 7 I: Global Interrupt EnableThe Global Interrupt Enable bit
must be set for the interrupts to be enabled. The individual
inter-rupt enable control is then performed in separate control
registers. If the Global Interrupt EnableRegister is cleared, none
of the interrupts are enabled independent of the individual
interruptenable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set bythe RETI instruction to enable
subsequent interrupts. The I-bit can also be set and cleared bythe
application with the SEI and CLI instructions, as described in the
instruction set reference.
Bit 6 T: Bit Copy StorageThe Bit Copy instructions BLD (Bit
LoaD) and BST (Bit STore) use the T-bit as source or desti-nation
for the operated bit. A bit from a register in the Register File
can be copied into T by theBST instruction, and a bit in T can be
copied into a bit in a register in the Register File by theBLD
instruction.
Bit 5 H: Half Carry Flag The Half Carry Flag H indicates a Half
Carry in some arithmetic operations. Half Carry Is usefulin BCD
arithmetic. See the Instruction Set Description for detailed
information.
Bit 4 S: Sign Bit, S = N VThe S-bit is always an exclusive or
between the Negative Flag N and the Twos ComplementOverflow Flag V.
See the Instruction Set Description for detailed information.
Bit 3 V: Twos Complement Overflow FlagThe Twos Complement
Overflow Flag V supports twos complement arithmetics. See
theInstruction Set Description for detailed information.
Bit 2 N: Negative FlagThe Negative Flag N indicates a negative
result in an arithmetic or logic operation. See theInstruction Set
Description for detailed information.
Bit 1 Z: Zero FlagThe Zero Flag Z indicates a zero result in an
arithmetic or logic operation. See the InstructionSet Description
for detailed information.
Bit 0 C: Carry FlagThe Carry Flag C indicates a carry in an
arithmetic or logic operation. See the Instruction SetDescription
for detailed information.
Bit 7 6 5 4 3 2 1 00x3F (0x5F) I T H S V N Z C SREGRead/Write
R/W R/W R/W R/W R/W R/W R/W R/WInitial Value 0 0 0 0 0 0 0
0108161DAVR10/09
-
ATmega48PA/88PA/168PA/328P6.4 General Purpose Register FileThe
Register File is optimized for the AVR Enhanced RISC instruction
set. In order to achievethe required performance and flexibility,
the following input/output schemes are supported by theRegister
File:
One 8-bit output operand and one 8-bit result input Two 8-bit
output operands and one 8-bit result input Two 8-bit output
operands and one 16-bit result input One 16-bit output operand and
one 16-bit result inputFigure 6-2 shows the structure of the 32
general purpose working registers in the CPU.
Figure 6-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have
direct access to all registers, andmost of them are single cycle
instructions.
As shown in Figure 6-2, each register is also assigned a data
memory address, mapping themdirectly into the first 32 locations of
the user Data Space. Although not being physically imple-mented as
SRAM locations, this memory organization provides great flexibility
in access of theregisters, as the X-, Y- and Z-pointer registers
can be set to index any register in the file.
7 0 Addr.
R0 0x00R1 0x01R2 0x02
R13 0x0DGeneral R14 0x0EPurpose R15 0x0FWorking R16
0x10Registers R17 0x11
R26 0x1A X-register Low ByteR27 0x1B X-register High ByteR28
0x1C Y-register Low ByteR29 0x1D Y-register High ByteR30 0x1E
Z-register Low ByteR31 0x1F Z-register High Byte118161DAVR10/09
-
ATmega48PA/88PA/168PA/328P6.4.1 The X-register, Y-register, and
Z-registerThe registers R26..R31 have some added functions to their
general purpose usage. These reg-isters are 16-bit address pointers
for indirect addressing of the data space. The three
indirectaddress registers X, Y, and Z are defined as described in
Figure 6-3.
Figure 6-3. The X-, Y-, and Z-registers
In the different addressing modes these address registers have
functions as fixed displacement,automatic increment, and automatic
decrement (see the instruction set reference for details).
6.5 Stack PointerThe Stack is mainly used for storing temporary
data, for storing local variables and for storingreturn addresses
after interrupts and subroutine calls. Note that the Stack is
implemented asgrowing from higher to lower memory locations. The
Stack Pointer Register always points to thetop of the Stack. The
Stack Pointer points to the data SRAM Stack area where the
Subroutineand Interrupt Stacks are located. A Stack PUSH command
will decrease the Stack Pointer.
The Stack in the data SRAM must be defined by the program before
any subroutine calls areexecuted or interrupts are enabled. Initial
Stack Pointer value equals the last address of theinternal SRAM and
the Stack Pointer must be set to point above start of the SRAM, see
Table 7-3 on page 18.
See Table 6-1 for Stack Pointer details.
The AVR Stack Pointer is implemented as two 8-bit registers in
the I/O space. The number ofbits actually used is implementation
dependent. Note that the data space in some implementa-tions of the
AVR architecture is so small that only SPL is needed. In this case,
the SPH Registerwill not be present.
15 XH XL 0
X-register 7 0 7 0R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0R29 (0x1D) R28 (0x1C)15 ZH ZL 0
Z-register 7 0 7 0R31 (0x1F) R30 (0x1E)
Table 6-1. Stack Pointer instructionsInstruction Stack pointer
DescriptionPUSH Decremented by 1 Data is pushed onto the
stackCALLICALLRCALL
Decremented by 2Return address is pushed onto the stack with a
subroutine call or interrupt
POP Incremented by 1 Data is popped from the stack
RETRETI
Incremented by 2 Return address is popped from the stack with
return from subroutine or return from interrupt128161DAVR10/09
-
ATmega48PA/88PA/168PA/328P6.5.1 SPH and SPL Stack Pointer High
and Stack Pointer Low Register
6.6 Instruction Execution TimingThis section describes the
general access timing concepts for instruction execution. The
AVRCPU is driven by the CPU clock clkCPU, directly generated from
the selected clock source for thechip. No internal clock division
is used.
Figure 6-4 shows the parallel instruction fetches and
instruction executions enabled by the Har-vard architecture and the
fast-access Register File concept. This is the basic pipelining
conceptto obtain up to 1 MIPS per MHz with the corresponding unique
results for functions per cost,functions per clocks, and functions
per power-unit.
Figure 6-4. The Parallel Instruction Fetches and Instruction
Executions
Figure 6-5 shows the internal timing concept for the Register
File. In a single clock cycle an ALUoperation using two register
operands is executed, and the result is stored back to the
destina-tion register.
Figure 6-5. Single Cycle ALU Operation
Bit 15 14 13 12 11 10 9 80x3E (0x5E) SP15 SP14 SP13 SP12 SP11
SP10 SP9 SP8 SPH0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
7 6 5 4 3 2 1 0Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/WInitial Value RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
clk
1st Instruction Fetch1st Instruction Execute
2nd Instruction Fetch2nd Instruction Execute
3rd Instruction Fetch3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU138161DAVR10/09
-
ATmega48PA/88PA/168PA/328P6.7 Reset and Interrupt HandlingThe
AVR provides several different interrupt sources. These interrupts
and the separate ResetVector each have a separate program vector in
the program memory space. All interrupts areassigned individual
enable bits which must be written logic one together with the
Global InterruptEnable bit in the Status Register in order to
enable the interrupt. Depending on the ProgramCounter value,
interrupts may be automatically disabled when Boot Lock bits BLB02
or BLB12are programmed. This feature improves software security.
See the section Memory Program-ming on page 294 for details.
The lowest addresses in the program memory space are by default
defined as the Reset andInterrupt Vectors. The complete list of
vectors is shown in Interrupts on page 57. The list alsodetermines
the priority levels of the different interrupts. The lower the
address the higher is thepriority level. RESET has the highest
priority, and next is INT0 the External Interrupt Request0. The
Interrupt Vectors can be moved to the start of the Boot Flash
section by setting the IVSELbit in the MCU Control Register
(MCUCR). Refer to Interrupts on page 57 for more information.The
Reset Vector can also be moved to the start of the Boot Flash
section by programming theBOOTRST Fuse, see Boot Loader Support
Read-While-Write Self-Programming,ATmega88PA, ATmega168PA and
ATmega328P on page 277.
When an interrupt occurs, the Global Interrupt Enable I-bit is
cleared and all interrupts are dis-abled. The user software can
write logic one to the I-bit to enable nested interrupts. All
enabledinterrupts can then interrupt the current interrupt routine.
The I-bit is automatically set when aReturn from Interrupt
instruction RETI is executed.
There are basically two types of interrupts. The first type is
triggered by an event that sets theInterrupt Flag. For these
interrupts, the Program Counter is vectored to the actual Interrupt
Vec-tor in order to execute the interrupt handling routine, and
hardware clears the correspondingInterrupt Flag. Interrupt Flags
can also be cleared by writing a logic one to the flag bit
position(s)to be cleared. If an interrupt condition occurs while
the corresponding interrupt enable bit iscleared, the Interrupt
Flag will be set and remembered until the interrupt is enabled, or
the flag iscleared by software. Similarly, if one or more interrupt
conditions occur while the Global InterruptEnable bit is cleared,
the corresponding Interrupt Flag(s) will be set and remembered
until theGlobal Interrupt Enable bit is set, and will then be
executed by order of priority.
The second type of interrupts will trigger as long as the
interrupt condition is present. Theseinterrupts do not necessarily
have Interrupt Flags. If the interrupt condition disappears before
theinterrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to
the main program and execute onemore instruction before any pending
interrupt is served.
Note that the Status Register is not automatically stored when
entering an interrupt routine, norrestored when returning from an
interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the
interrupts will be immediately disabled.No interrupt will be
executed after the CLI instruction, even if it occurs
simultaneously with theCLI instruction. The following example shows
how this can be used to avoid interrupts during thetimed EEPROM
write sequence.148161DAVR10/09
-
ATmega48PA/88PA/168PA/328PWhen using the SEI instruction to
enable interrupts, the instruction following SEI will be exe-cuted
before any pending interrupts, as shown in this example.
6.7.1 Interrupt Response TimeThe interrupt execution response
for all the enabled AVR interrupts is four clock cycles mini-mum.
After four clock cycles the program vector address for the actual
interrupt handling routineis executed. During this four clock cycle
period, the Program Counter is pushed onto the Stack.The vector is
normally a jump to the interrupt routine, and this jump takes three
clock cycles. Ifan interrupt occurs during execution of a
multi-cycle instruction, this instruction is completedbefore the
interrupt is served. If an interrupt occurs when the MCU is in
sleep mode, the interruptexecution response time is increased by
four clock cycles. This increase comes in addition to thestart-up
time from the selected sleep mode.
A return from an interrupt handling routine takes four clock
cycles. During these four clockcycles, the Program Counter (two
bytes) is popped back from the Stack, the Stack Pointer
isincremented by two, and the I-bit in SREG is set.
Assembly Code Examplein r16, SREG ; store SREG valuecli ;
disable interrupts during timed sequencesbi EECR, EEMPE ; start
EEPROM writesbi EECR, EEPEout SREG, r16 ; restore SREG value
(I-bit)
C Code Examplechar cSREG;cSREG = SREG; /* store SREG value *//*
disable interrupts during timed sequence */_CLI(); EECR |= (1
-
ATmega48PA/88PA/168PA/328P7. AVR Memories
7.1 OverviewThis section describes the different memories in the
ATmega48PA/88PA/168PA/328P. The AVRarchitecture has two main memory
spaces, the Data Memory and the Program Memory space.In addition,
the ATmega48PA/88PA/168PA/328P features an EEPROM Memory for data
stor-age. All three memory spaces are linear and regular.
7.2 In-System Reprogrammable Flash Program Memory The
ATmega48PA/88PA/168PA/328P contains 4/8/16/32K bytes On-chip
In-System Repro-grammable Flash memory for program storage. Since
all AVR instructions are 16 or 32 bitswide, the Flash is organized
as 2/4/8/16K x 16. For software security, the Flash Program mem-ory
space is divided into two sections, Boot Loader Section and
Application Program Section inATmega88PA and ATmega168PA. See
SELFPRGEN description in section SPMCSR StoreProgram Memory Control
and Status Register on page 292 for more details.
The Flash memory has an endurance of at least 10,000 wri
te/erase cycles. TheATmega48PA/88PA/168PA/328P Program Counter (PC)
is 11/12/13/14 bits wide, thus address-ing the 2/4/8/16K program
memory locations. The operation of Boot Program section
andassociated Boot Lock bits for software protection are described
in detail in Self-Programmingthe Flash, ATmega48PA on page 269 and
Boot Loader Support Read-While-Write Self-Pro-gramming, ATmega88PA,
ATmega168PA and ATmega328P on page 277. MemoryProgramming on page
294 contains a detailed description on Flash Programming in SPI-
orParallel Programming mode.
Constant tables can be allocated within the entire program
memory address space (see the LPM Load Program Memory instruction
description).Timing diagrams for instruction fetch and execution
are presented in Instruction Execution Tim-ing on page
13.168161DAVR10/09
-
ATmega48PA/88PA/168PA/328PFigure 7-1. Program Memory Map
ATmega48PA
Figure 7-2. Program Memory Map ATmega88PA, ATmega168PA and
ATmega328P
0x0000
0x7FF
Program Memory
Application Flash Section
0x0000
0x0FFF/0x1FFF/0x3FFF
Program Memory
Application Flash Section
Boot Flash Section178161DAVR10/09
-
ATmega48PA/88PA/168PA/328P7.3 SRAM Data MemoryFigure 7-3 shows
how the ATmega48PA/88PA/168PA/328P SRAM Memory is organized.
The ATmega48PA/88PA/168PA/328P is a complex microcontroller with
more peripheral unitsthan can be supported within the 64 locations
reserved in the Opcode for the IN and OUTinstructions. For the
Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD
andLD/LDS/LDD instructions can be used.
The lower 768/1280/1280/2303 data memory locations address both
the Register File, the I/Omemory, Extended I/O memory, and the
internal data SRAM. The first 32 locations address theRegister
File, the next 64 location the standard I/O memory, then 160
locations of Extended I/Omemory, and the next 512/1024/1024/2048
locations address the internal data SRAM.
The five different addressing modes for the data memory cover:
Direct, Indirect with Displace-ment, Indirect, Indirect with
Pre-decrement, and Indirect with Post-increment. In the
RegisterFile, registers R26 to R31 feature the indirect addressing
pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations
from the base address givenby the Y- or Z-register.
When using register indirect addressing modes with automatic
pre-decrement and post-incre-ment, the address registers X, Y, and
Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160
Extended I/O Registers, andthe 512/1024/1024/2048 bytes of internal
data SRAM in the ATmega48PA/88PA/168PA/328Pare all accessible
through all these addressing modes. The Register File is described
in Gen-eral Purpose Register File on page 11.
Figure 7-3. Data Memory Map
32 Registers64 I/O Registers
Internal SRAM(512/1024/1024/2048 x 8)
0x0000 - 0x001F0x0020 - 0x005F
0x04FF/0x04FF/0x0FF/0x08FF
0x0060 - 0x00FF
Data Memory
160 Ext I/O Reg.0x0100188161DAVR10/09
-
ATmega48PA/88PA/168PA/328P7.3.1 Data Memory Access TimesThis
section describes the general access timing concepts for internal
memory access. Theinternal data SRAM access is performed in two
clkCPU cycles as described in Figure 7-4.
Figure 7-4. On-chip Data SRAM Access Cycles
7.4 EEPROM Data MemoryThe ATmega48PA/88PA/168PA/328P contains
256/512/512/1K bytes of data EEPROM mem-ory. It is organized as a
separate data space, in which single bytes can be read and written.
TheEEPROM has an endurance of at least 100,000 write/erase cycles.
The access between theEEPROM and the CPU is described in the
following, specifying the EEPROM Address Regis-ters, the EEPROM
Data Register, and the EEPROM Control Register.
Memory Programming on page 294 contains a detailed description
on EEPROM Programmingin SPI or Parallel Programming mode.
7.4.1 EEPROM Read/Write AccessThe EEPROM Access Registers are
accessible in the I/O space.
The write access time for the EEPROM is given in Table 7-2. A
self-timing function, however,lets the user software detect when
the next byte can be written. If the user code contains
instruc-tions that write the EEPROM, some precautions must be
taken. In heavily filtered powersupplies, VCC is likely to rise or
fall slowly on power-up/down. This causes the device for someperiod
of time to run at a voltage lower than specified as minimum for the
clock frequency used.See Preventing EEPROM Corruption on page 20
for details on how to avoid problems in thesesituations.
In order to prevent unintentional EEPROM writes, a specific
write procedure must be followed.Refer to the description of the
EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles
before the next instruction isexecuted. When the EEPROM is written,
the CPU is halted for two clock cycles before the nextinstruction
is executed.
clk
WR
RD
Data
Data
Address Address valid
T1 T2 T3
Compute Address
Rea
dW
rite
CPU
Memory Access Instruction Next Instruction198161DAVR10/09
-
ATmega48PA/88PA/168PA/328P7.4.2 Preventing EEPROM
CorruptionDuring periods of low VCC, the EEPROM data can be
corrupted because the supply voltage istoo low for the CPU and the
EEPROM to operate properly. These issues are the same as forboard
level systems using EEPROM, and the same design solutions should be
applied.
An EEPROM data corruption can be caused by two situations when
the voltage is too low. First,a regular write sequence to the
EEPROM requires a minimum voltage to operate correctly. Sec-ondly,
the CPU itself can execute instructions incorrectly, if the supply
voltage is too low.
EEPROM data corruption can easily be avoided by following this
design recommendation:
Keep the AVR RESET active (low) during periods of insufficient
power supply voltage. This canbe done by enabling the internal
Brown-out Detector (BOD). If the detection level of the internalBOD
does not match the needed detection level, an external low VCC
reset Protection circuit canbe used. If a reset occurs while a
write operation is in progress, the write operation will be
com-pleted provided that the power supply voltage is
sufficient.
7.5 I/O MemoryThe I/O space definition of the
ATmega48PA/88PA/168PA/328P is shown in Register Sum-mary on page
423.
All ATmega48PA/88PA/168PA/328P I/Os and peripherals are placed
in the I/O space. All I/Olocations may be accessed by the
LD/LDS/LDD and ST/STS/STD instructions, transferring databetween
the 32 general purpose working registers and the I/O space. I/O
Registers within theaddress range 0x00 - 0x1F are directly
bit-accessible using the SBI and CBI instructions. Inthese
registers, the value of single bits can be checked by using the
SBIS and SBIC instructions.Refer to the instruction set section for
more details. When using the I/O specific commands INand OUT, the
I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as dataspace using LD and ST instructions, 0x20 must be
added to these addresses. TheATmega48PA/88PA/168PA/328P is a
complex microcontroller with more peripheral units thancan be
supported within the 64 location reserved in Opcode for the IN and
OUT instructions. Forthe Extended I/O space from 0x60 - 0xFF in
SRAM, only the ST/STS/STD and LD/LDS/LDDinstructions can be
used.
For compatibility with future devices, reserved bits should be
written to zero if accessed.Reserved I/O memory addresses should
never be written.
Some of the Status Flags are cleared by writing a logical one to
them. Note that, unlike mostother AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can
thereforebe used on registers containing such Status Flags. The CBI
and SBI instructions work with reg-isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later
sections.
7.5.1 General Purpose I/O RegistersThe
ATmega48PA/88PA/168PA/328P contains three General Purpose I/O
Registers. Theseregisters can be used for storing any information,
and they are particularly useful for storingglobal variables and
Status Flags. General Purpose I/O Registers within the address
range 0x00- 0x1F are directly bit-accessible using the SBI, CBI,
SBIS, and SBIC instructions.208161DAVR10/09
-
ATmega48PA/88PA/168PA/328P7.6 Register Description
7.6.1 EEARH and EEARL The EEPROM Address Register
Bits 15..9 Res: Reserved BitsThese bits are reserved bits in the
ATmega48PA/88PA/168PA/328P and will always read aszero.
Bits 8..0 EEAR8..0: EEPROM AddressThe EEPROM Address Registers
EEARH and EEARL specify the EEPROM address in the256/512/512/1K
bytes EEPROM space. The EEPROM data bytes are addressed
linearlybetween 0 and 255/511/511/1023. The initial value of EEAR
is undefined. A proper value mustbe written before the EEPROM may
be accessed.
EEAR8 is an unused bit in ATmega48PA and must always be written
to zero.
7.6.2 EEDR The EEPROM Data Register
Bits 7..0 EEDR7.0: EEPROM DataFor the EEPROM write operation,
the EEDR Register contains the data to be written to theEEPROM in
the address given by the EEAR Register. For the EEPROM read
operation, theEEDR contains the data read out from the EEPROM at
the address given by EEAR.
7.6.3 EECR The EEPROM Control Register
Bits 7..6 Res: Reserved BitsThese bits are reserved bits in the
ATmega48PA/88PA/168PA/328P and will always read aszero.
Bits 5, 4 EEPM1 and EEPM0: EEPROM Programming Mode BitsThe
EEPROM Programming mode bit setting defines which programming
action that will be trig-gered when writing EEPE. It is possible to
program data in one atomic operation (erase the oldvalue and
program the new value) or to split the Erase and Write operations
in two differentoperations. The Programming times for the different
modes are shown in Table 7-1. While EEPE
Bit 15 14 13 12 11 10 9 80x22 (0x42) EEAR8 EEARH0x21 (0x41)
EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
7 6 5 4 3 2 1 0Read/Write R R R R R R R R/W
R/W R/W R/W R/W R/W R/W R/W R/WInitial Value 0 0 0 0 0 0 0 X
X X X X X X X X
Bit 7 6 5 4 3 2 1 00x20 (0x40) MSB LSB EEDRRead/Write R/W R/W
R/W R/W R/W R/W R/W R/WInitial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 00x1F (0x3F) EEPM1 EEPM0 EERIE EEMPE EEPE EERE
EECRRead/Write R R R/W R/W R/W R/W R/W R/WInitial Value 0 0 X X 0 0
X 0218161DAVR10/09
-
ATmega48PA/88PA/168PA/328Pis set, any write to EEPMn will be
ignored. During reset, the EEPMn bits will be reset to 0b00unless
the EEPROM is busy programming.
Bit 3 EERIE: EEPROM Ready Interrupt EnableWriting EERIE to one
enables the EEPROM Ready Interrupt if the I bit in SREG is set.
WritingEERIE to zero disables the interrupt. The EEPROM Ready
interrupt generates a constant inter-rupt when EEPE is cleared. The
interrupt will not be generated during EEPROM write or SPM.
Bit 2 EEMPE: EEPROM Master Write EnableThe EEMPE bit determines
whether setting EEPE to one causes the EEPROM to be written.When
EEMPE is set, setting EEPE within four clock cycles will write data
to the EEPROM at theselected address If EEMPE is zero, setting EEPE
will have no effect. When EEMPE has beenwritten to one by software,
hardware clears the bit to zero after four clock cycles. See
thedescription of the EEPE bit for an EEPROM write procedure.
Bit 1 EEPE: EEPROM Write EnableThe EEPROM Write Enable Signal
EEPE is the write strobe to the EEPROM. When addressand data are
correctly set up, the EEPE bit must be written to one to write the
value into theEEPROM. The EEMPE bit must be written to one before a
logical one is written to EEPE, other-wise no EEPROM write takes
place. The following procedure should be followed when writingthe
EEPROM (the order of steps 3 and 4 is not essential):1. Wait until
EEPE becomes zero.2. Wait until SELFPRGEN in SPMCSR becomes zero.3.
Write new EEPROM address to EEAR (optional).4. Write new EEPROM
data to EEDR (optional).5. Write a logical one to the EEMPE bit
while writing a zero to EEPE in EECR.6. Within four clock cycles
after setting EEMPE, write a logical one to EEPE.The EEPROM can not
be programmed during a CPU write to the Flash memory. The
softwaremust check that the Flash programming is completed before
initiating a new EEPROM write.Step 2 is only relevant if the
software contains a Boot Loader allowing the CPU to program
theFlash. If the Flash is never being updated by the CPU, step 2
can be omitted. See Boot LoaderSupport Read-While-Write
Self-Programming, ATmega88PA, ATmega168PA andATmega328P on page 277
for details about Boot programming.
Caution: An interrupt between step 5 and step 6 will make the
write cycle fail, since theEEPROM Master Write Enable will
time-out. If an interrupt routine accessing the EEPROM
isinterrupting another EEPROM access, the EEAR or EEDR Register
will be modified, causing theinterrupted EEPROM access to fail. It
is recommended to have the Global Interrupt Flag clearedduring all
the steps to avoid these problems.
Table 7-1. EEPROM Mode Bits
EEPM1 EEPM0Programming
Time Operation
0 0 3.4 ms Erase and Write in one operation (Atomic Operation)0
1 1.8 ms Erase Only
1 0 1.8 ms Write Only1 1 Reserved for future
use228161DAVR10/09
-
ATmega48PA/88PA/168PA/328PWhen the write access time has
elapsed, the EEPE bit is cleared by hardware. The user soft-ware
can poll this bit and wait for a zero before writing the next byte.
When EEPE has been set,the CPU is halted for two cycles before the
next instruction is executed.
Bit 0 EERE: EEPROM Read EnableThe EEPROM Read Enable Signal EERE
is the read strobe to the EEPROM. When the correctaddress is set up
in the EEAR Register, the EERE bit must be written to a logic one
to trigger theEEPROM read. The EEPROM read access takes one
instruction, and the requested data isavailable immediately. When
the EEPROM is read, the CPU is halted for four cycles before
thenext instruction is executed.
The user should poll the EEPE bit before starting the read
operation. If a write operation is inprogress, it is neither
possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses.
Table 7-2 lists the typical pro-gramming time for EEPROM access
from the CPU.
The following code examples show one assembly and one C function
for writing to theEEPROM. The examples assume that interrupts are
controlled (e.g. by disabling interrupts glob-ally) so that no
interrupts will occur during execution of these functions. The
examples alsoassume that no Flash Boot Loader is present in the
software. If such code is present, theEEPROM write function must
also wait for any ongoing SPM command to finish.
Table 7-2. EEPROM Programming TimeSymbol Number of Calibrated RC
Oscillator Cycles Typ Programming TimeEEPROM write (from CPU)
26,368 3.3 ms238161DAVR10/09
-
ATmega48PA/88PA/168PA/328PAssembly Code ExampleEEPROM_write:;
Wait for completion of previous writesbic EECR,EEPErjmp
EEPROM_write ; Set up address (r18:r17) in address registerout
EEARH, r18out EEARL, r17
; Write data (r16) to Data Registerout EEDR,r16; Write logical
one to EEMPEsbi EECR,EEMPE; Start eeprom write by setting EEPEsbi
EECR,EEPEret
C Code Examplevoid EEPROM_write(unsigned int uiAddress, unsigned
char ucData){/* Wait for completion of previous write */while(EECR
& (1
-
ATmega48PA/88PA/168PA/328PThe next code examples show assembly
and C functions for reading the EEPROM. The exam-ples assume that
interrupts are controlled so that no interrupts will occur during
execution ofthese functions.
7.6.4 GPIOR2 General Purpose I/O Register 2
7.6.5 GPIOR1 General Purpose I/O Register 1
7.6.6 GPIOR0 General Purpose I/O Register 0
Assembly Code ExampleEEPROM_read:; Wait for completion of
previous writesbic EECR,EEPErjmp EEPROM_read; Set up address
(r18:r17) in address registerout EEARH, r18out EEARL, r17; Start
eeprom read by writing EEREsbi EECR,EERE; Read data from Data
Registerin r16,EEDRret
C Code Exampleunsigned char EEPROM_read(unsigned int
uiAddress){/* Wait for completion of previous write */while(EECR
& (1
-
ATmega48PA/88PA/168PA/328P8. System Clock and Clock Options
8.1 Clock Systems and their DistributionFigure 8-1 presents the
principal clock systems in the AVR and their distribution. All of
the clocksneed not be active at a given time. In order to reduce
power consumption, the clocks to modulesnot being used can be
halted by using different sleep modes, as described in Power
Manage-ment and Sleep Modes on page 39. The clock systems are
detailed below.
Figure 8-1. Clock Distribution
8.1.1 CPU Clock clkCPUThe CPU clock is routed to parts of the
system concerned with operation of the AVR core.Examples of such
modules are the General Purpose Register File, the Status Register
and thedata memory holding the Stack Pointer. Halting the CPU clock
inhibits the core from performinggeneral operations and
calculations.
8.1.2 I/O Clock clkI/OThe I/O clock is used by the majority of
the I/O modules, like Timer/Counters, SPI, and USART.The I/O clock
is also used by the External Interrupt module, but note that some
external inter-rupts are detected by asynchronous logic, allowing
such interrupts to be detected even if the I/Oclock is halted. Also
note that start condition detection in the USI module is carried
out asynchro-nously when clkI/O is halted, TWI address recognition
in all sleep modes.
8.1.3 Flash Clock clkFLASHThe Flash clock controls operation of
the Flash interface. The Flash clock is usually active
simul-taneously with the CPU clock.
General I/OModules
AsynchronousTimer/Counter CPU Core RAM
clkI/O
clkASY
AVR ClockControl Unit
clkCPU
Flash andEEPROM
clkFLASH
Source clock
Watchdog Timer
WatchdogOscillator
Reset Logic
ClockMultiplexer
Watchdog clock
Calibrated RCOscillator
Timer/CounterOscillator
CrystalOscillator
Low-frequencyCrystal OscillatorExternal Clock
ADC
clkADC
System ClockPrescaler268161DAVR10/09
-
ATmega48PA/88PA/168PA/328P8.1.4 Asynchronous Timer Clock
clkASYThe Asynchronous Timer clock allows the Asynchronous
Timer/Counter to be clocked directlyfrom an external clock or an
external 32 kHz clock crystal. The dedicated clock domain
allowsusing this Timer/Counter as a real-time counter even when the
device is in sleep mode.
8.1.5 ADC Clock clkADCThe ADC is provided with a dedicated clock
domain. This allows halting the CPU and I/O clocksin order to
reduce noise generated by digital circuitry. This gives more
accurate ADC conversionresults.
8.2 Clock SourcesThe device has the following clock source
options, selectable by Flash Fuse bits as shownbelow. The clock
from the selected source is input to the AVR clock generator, and
routed to theappropriate modules.
Note: 1. For all fuses 1 means unprogrammed while 0 means
programmed.
8.2.1 Default Clock SourceThe device is shipped with internal RC
oscillator at 8.0MHz and with the fuse CKDIV8 pro-grammed,
resulting in 1.0MHz system clock. The startup time is set to
maximum and time-outperiod enabled. (CKSEL = "0010", SUT = "10",
CKDIV8 = "0"). The default setting ensures thatall users can make
their desired clock source setting using any available programming
interface.
8.2.2 Clock Startup SequenceAny clock source needs a sufficient
VCC to start oscillating and a minimum number of oscillatingcycles
before it can be considered stable.
To ensure sufficient VCC, the device issues an internal reset
with a time-out delay (tTOUT) afterthe device reset is released by
all other reset sources. System Control and Reset on page
46describes the start conditions for the internal reset. The delay
(tTOUT) is timed from the WatchdogOscillator and the number of
cycles in the delay is set by the SUTx and CKSELx fuse bits.
The
Table 8-1. Device Clocking Options Select(1)
Device Clocking Option CKSEL3..0Low Power Crystal Oscillator
1111 - 1000Full Swing Crystal Oscillator 0111 - 0110Low Frequency
Crystal Oscillator 0101 - 0100Internal 128 kHz RC Oscillator
0011Calibrated Internal RC Oscillator 0010
External Clock 0000Reserved 0001278161DAVR10/09
-
ATmega48PA/88PA/168PA/328Pselectable delays are shown in Table
8-2. The frequency of the Watchdog Oscillator is voltagedependent
as shown in Typical Characteristics on page 326.
Main purpose of the delay is to keep the AVR in reset until it
is supplied with minimum VCC. Thedelay will not monitor the actual
voltage and it will be required to select a delay longer than
theVCC rise time. If this is not possible, an internal or external
Brown-Out Detection circuit should beused. A BOD circuit will
ensure sufficient VCC before it releases the reset, and the
time-out delaycan be disabled. Disabling the time-out delay without
utilizing a Brown-Out Detection circuit isnot recommended.
The oscillator is required to oscillate for a minimum number of
cycles before the clock is consid-ered stable. An internal ripple
counter monitors the oscillator output clock, and keeps the
internalreset active for a given number of clock cycles. The reset
is then released and the device willstart to execute. The
recommended oscillator start-up time is dependent on the clock
type, andvaries from 6 cycles for an externally applied clock to
32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out
delay and the start-up time whenthe device starts up from reset.
When starting up from Power-save or Power-down mode, VCC isassumed
to be at a sufficient level and only the start-up time is
included.
8.3 Low Power Crystal OscillatorPins XTAL1 and XTAL2 are input
and output, respectively, of an inverting amplifier which can
beconfigured for use as an On-chip Oscillator, as shown in Figure
8-2 on page 29. Either a quartzcrystal or a ceramic resonator may
be used.
This Crystal Oscillator is a low power oscillator, with reduced
voltage swing on the XTAL2 out-put. It gives the lowest power
consumption, but is not capable of driving other clock inputs,
andmay be more susceptible to noise in noisy environments. In these
cases, refer to the Full SwingCrystal Oscillator on page 30.
C1 and C2 should always be equal for both crystals and
resonators. The optimal value of thecapacitors depends on the
crystal or resonator in use, the amount of stray capacitance, and
theelectromagnetic noise of the environment. Some initial
guidelines for choosing capacitors foruse with crystals are given
in Table 8-3 on page 29. For ceramic resonators, the capacitor
val-ues given by the manufacturer should be used.
Table 8-2. Number of Watchdog Oscillator CyclesTyp Time-out (VCC
= 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles
0 ms 0 ms 0
4.1 ms 4.3 ms 512
65 ms 69 ms 8K (8,192)288161DAVR10/09
-
ATmega48PA/88PA/168PA/328PFigure 8-2. Crystal Oscillator
Connections
The Low Power Oscillator can operate in three different modes,
each optimized for a specific fre-quency range. The operating mode
is selected by the fuses CKSEL3..1 as shown in Table 8-3on page
29.
Notes: 1. This is the recommanded CKSEL settings for the
difference frenquency ranges.2. This option should not be used with
crystals, only with ceramic resonators.3. If 8 MHz frequency
exceeds the specification of the device (depends on VCC), the
CKDIV8
Fuse can be programmed in order to divide the internal frequency
by 8. It must be ensured that the resulting divided clock meets the
frequency specification of the device.
The CKSEL0 Fuse together with the SUT1..0 Fuses select the
start-up times as shown in Table8-4.
Table 8-3. Low Power Crystal Oscillator Operating Modes(3)
Frequency Range(MHz)
Recommended Range for Capacitors C1 and C2 (pF) CKSEL3..1(1)
0.4 - 0.9 100(2)
0.9 - 3.0 12 - 22 101
3.0 - 8.0 12 - 22 110
8.0 - 16.0 12 - 22 111
Table 8-4. Start-up Times for the Low Power Crystal Oscillator
Clock Selection
Oscillator Source / Power Conditions
Start-up Time from Power-down and
Power-save
Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0
Ceramic resonator, fast rising power 258 CK 14CK + 4.1 ms
(1) 0 00
Ceramic resonator, slowly rising power 258 CK 14CK + 65 ms
(1) 0 01
Ceramic resonator, BOD enabled 1K CK 14CK
(2) 0 10
Ceramic resonator, fast rising power 1K CK 14CK + 4.1 ms
(2) 0 11
Ceramic resonator, slowly rising power 1K CK 14CK + 65 ms
(2) 1 00
XTAL2 (TOSC2)
XTAL1 (TOSC1)
GND
C2
C1298161DAVR10/09
-
ATmega48PA/88PA/168PA/328PNotes: 1. These options should only be
used when not operating close to the maximum frequency of the
device, and only if frequency stability at start-up is not
important for the application. These options are not suitable for
crystals.
2. These options are intended for use with ceramic resonators
and will ensure frequency stability at start-up. They can also be
used with crystals when not operating close to the maximum
fre-quency of the device, and if frequency stability at start-up is
not important for the application.
8.4 Full Swing Crystal OscillatorPins XTAL1 and XTAL2 are input
and output, respectively, of an inverting amplifier which can
beconfigured for use as an On-chip Oscillator, as shown in Figure
8-2 on page 29. Either a quartzcrystal or a ceramic resonator may
be used.
This Crystal Oscillator is a full swing oscillator, with
rail-to-rail swing on the XTAL2 output. This isuseful for driving
other clock inputs and in noisy environments. The current
consumption ishigher than the Low Power Crystal Oscillator on page
28. Note that the Full Swing CrystalOscillator will only operate
for VCC = 2.7 - 5.5 volts.
C1 and C2 should always be equal for both crystals and
resonators. The optimal value of thecapacitors depends on the
crystal or resonator in use, the amount of stray capacitance, and
theelectromagnetic noise of the environment. Some initial
guidelines for choosing capacitors foruse with crystals are given
in Table 8-6 on page 31. For ceramic resonators, the capacitor
val-ues given by the manufacturer should be used.
The operating mode is selected by the fuses CKSEL3..1 as shown
in Table 8-5.
Notes: 1. If 8 MHz frequency exceeds the specification of the
device (depends on VCC), the CKDIV8 Fuse can be programmed in order
to divide the internal frequency by 8. It must be ensured that the
resulting divided clock meets the frequency specification of the
device.
Crystal Oscillator, BOD enabled 16K CK 14CK 1 01
Crystal Oscillator, fast rising power 16K CK 14CK + 4.1 ms 1
10
Crystal Oscillator, slowly rising power 16K CK 14CK + 65 ms 1
11
Table 8-4. Start-up Times for the Low Power Crystal Oscillator
Clock Selection (Continued)
Oscillator Source / Power Conditions
Start-up Time from Power-down and
Power-save
Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0
Table 8-5. Full Swing Crystal Oscillator operating
modesFrequency Range(1)
(MHz)Recommended Range for Capacitors C1 and C2 (pF)
CKSEL3..1
0.4 - 20 12 - 22 011308161DAVR10/09
-
ATmega48PA/88PA/168PA/328PFigure 8-3. Crystal Oscillator
Connections
Notes: 1. These options should only be used when not operating
close to the maximum frequency of the device, and only if frequency
stability at start-up is not important for the application. These
options are not suitable for crystals.
2. These options are intended for use with ceramic resonators
and will ensure frequency stability at start-up. They can also be
used with crystals when not operating close to the maximum
fre-quency of the device, and if frequency stability at start-up is
not important for the application.
Table 8-6. Start-up Times for the Full Swing Crystal Oscillator
Clock Selection
Oscillator Source / Power Conditions
Start-up Time from Power-down and
Power-save
Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0
Ceramic resonator, fast rising power 258 CK 14CK + 4.1 ms
(1) 0 00
Ceramic resonator, slowly rising power 258 CK 14CK + 65 ms
(1) 0 01
Ceramic resonator, BOD enabled 1K CK 14CK
(2) 0 10
Ceramic resonator, fast rising power 1K CK 14CK + 4.1 ms
(2) 0 11
Ceramic resonator, slowly rising power 1K CK 14CK + 65 ms
(2) 1 00
Crystal Oscillator, BOD enabled 16K CK 14CK 1 01
Crystal Oscillator, fast rising power 16K CK 14CK + 4.1 ms 1
10
Crystal Oscillator, slowly rising power 16K CK 14CK + 65 ms 1
11
XTAL2 (TOSC2)
XTAL1 (TOSC1)
GND
C2
C1318161DAVR10/09
-
ATmega48PA/88PA/168PA/328P8.5 Low Frequency Crystal
OscillatorThe Low-frequency Crystal Oscillator is optimized for use
with a 32.768 kHz watch crystal.When selecting crystals, load
capasitance and crystals Equivalent Series Resistance, ESRmust be
taken into consideration. Both values are specified by the crystal
vendor.ATmega48PA/88PA/168PA/328P oscillator is optimized for very
low power consumption, andthus when selecting crystals, see Table
8-7 on page 32 for maximum ESR recommendations on6.5 pF, 9.0 pF and
12.5 pF crystals
Table 8-7. Maximum ESR Recommendation for 32.768 kHz Crystal
Oscillator
Note: 1. Maximum ESR is typical value based on
characterizationThe Low-frequency Crystal Oscillator provides an
internal load capacitance at each TOSC pinas specified in the Table
8-8 on page 32.
The external capacitance (C) needed at each TOSC pin can be
calculated by using:
where CL is the load capacitance for a 32.768 kHz crystal
specified by the crystal vendor and CSis the total stray
capacitance for one TOSC pin.
Crystals specifying load capacitance (CL) higher than the ones
given in the Table 8-8 on page32, require external capacitors
applied as described in Figure 8-2 on page 29.
The Low-frequency Crystal Oscillator must be selected by setting
the CKSEL Fuses to 0110 or0111, as shown in Table 8-10. Start-up
times are determined by the SUT Fuses as shown inTable 8-9.
Crystal CL (pF) Max ESR [k](1)6.5 75
9.0 65
12.5 30
Table 8-8. Capacitance for Low-Frequency Crystal
OscillatorDevice 32 kHz Osc. Type Cap (Xtal1/Tosc1) Cap
(Xtal2/Tosc2)
ATmega48PA/88PA/168PA/328P System Osc. 18 pF 8 pFTimer Osc. 18
pF 8 pF
Table 8-9. Start-up Times for the Low-frequency Crystal
Oscillator Clock SelectionSUT1..0 Additional Delay from Reset (VCC
= 5.0V) Recommended Usage
00 4 CK Fast rising power or BOD enabled01 4 CK + 4.1 ms Slowly
rising power10 4 CK + 65 ms Stable frequency at start-up11
Reserved
C 2 CL Cs=328161DAVR10/09
-
ATmega48PA/88PA/168PA/328PNote: 1. This option should only be
used if frequency stability at start-up is not important for the
application
8.6 Calibrated Internal RC OscillatorBy default, the Internal RC
Oscillator provides an approximate 8.0 MHz clock. Though voltageand
temperature dependent, this clock can be very accurately calibrated
by the user. See Table28-1 on page 317 for more details. The device
is shipped with the CKDIV8 Fuse programmed.See System Clock
Prescaler on page 35 for more details.
This clock may be selected as the system clock by programming
the CKSEL Fuses as shown inTable 8-11. If selected, it will operate
with no external components. During reset, hardware loadsthe
pre-programmed calibration value into the OSCCAL Register and
thereby automatically cal-ibrates the RC Oscillator. The accuracy
of this calibration is shown as Factory calibration inTable 28-1 on
page 317.
By changing the OSCCAL register from SW, see OSCCAL Oscillator
Calibration Register onpage 37, it is possible to get a higher
calibration accuracy than by using the factory calibration.The
accuracy of this calibration is shown as User calibration in Table
28-1 on page 317.
When this Oscillator is used as the chip clock, the Watchdog
Oscillator will still be used for theWatchdog Timer and for the
Reset Time-out. For more information on the pre-programmed
cali-bration value, see the section Calibration Byte on page
298.
Notes: 1. The device is shipped with this option selected.2. If
8 MHz frequency exceeds the specification of the device (depends on
VCC), the CKDIV8
Fuse can be programmed in order to divide the internal frequency
by 8.When this Oscillator is selected, start-up times are
determined by the SUT Fuses as shown inTable 8-12 on page 33.
Note: 1. If the RSTDISBL fuse is programmed, this start-up time
will be increased to 14CK + 4.1 ms to ensure programming mode can
be entered.
2. The device is shipped with this option selected.
Table 8-10. Start-up Times for the Low-frequency Crystal
Oscillator Clock Selection
CKSEL3..0Start-up Time from
Power-down and Power-save Recommended Usage0100(1) 1K CK
0101 32K CK Stable frequency at start-up
Table 8-11. Internal Calibrated RC Oscillator Operating
ModesFrequency Range(2) (MHz) CKSEL3..0
7.3 - 8.1 0010(1)
Table 8-12. Start-up times for the internal calibrated RC
Oscillator clock selection
Power ConditionsStart-up Time from Power-
down and Power-saveAdditional Delay from
Reset (VCC = 5.0V) SUT1..0BOD enabled 6 CK 14CK(1) 00Fast rising
power 6 CK 14CK + 4.1 ms 01Slowly rising power 6 CK 14CK + 65 ms(2)
10
Reserved 11338161DAVR10/09
-
ATmega48PA/88PA/168PA/328P8.7 128 kHz Internal OscillatorThe 128
kHz internal Oscillator is a low power Oscillator providing a clock
of 128 kHz. The fre-quency is nominal at 3V and 25C. This clock may
be select as the system clock byprogramming the CKSEL Fuses to 11
as shown in Table 8-13.
Note: 1. Note that the 128 kHz oscillator is a very low power
clock source, and is not designed for high accuracy.
When this clock source is selected, start-up times are
determined by the SUT Fuses as shown inTable 8-14.
Note: 1. If the RSTDISBL fuse is programmed, this start-up time
will be increased to 14CK + 4.1 ms to ensure programming mode can
be entered.
8.8 External ClockTo drive the device from an external clock
source, XTAL1 should be driven as shown in Figure8-4 on page 34. To
run the device on an external clock, the CKSEL Fuses must be
programmedto 0000 (see Table 8-15).
Figure 8-4. External Clock Drive Configuration
When this clock source is selected, start-up times are
determined by the SUT Fuses as shown inTable 8-16.
Table 8-13. 128 kHz Internal Oscillator Operating ModesNominal
Frequency(1) CKSEL3..0
128 kHz 0011
Table 8-14. Start-up Times for the 128 kHz Internal
Oscillator
Power ConditionsStart-up Time from Power-
down and Power-saveAdditional Delay from
Reset SUT1..0BOD enabled 6 CK 14CK(1) 00Fast rising power 6 CK
14CK + 4 ms 01Slowly rising power 6 CK 14CK + 64 ms 10
Reserved 11
Table 8-15. Crystal Oscillator Clock FrequencyFrequency
CKSEL3..00 - 20 MHz 0000
NC
EXTERNALCLOCKSIGNAL
XTAL2
XTAL1
GND348161DAVR10/09
-
ATmega48PA/88PA/168PA/328PWhen applying an external clock, it is
required to avoid sudden changes in the applied clock fre-quency to
ensure stable operation of the MCU. A variation in frequency of
more than 2% fromone clock cycle to the next can lead to
unpredictable behavior. If changes of more than 2% isrequired,
ensure that the MCU is kept in Reset during the changes.
Note that the System Clock Prescaler can be used to implement
run-time changes of the internalclock frequency while still
ensuring stable operation. Refer to System Clock Prescaler on
page35 for details.
8.9 Clock Output BufferThe device can output the system clock on
the CLKO pin. To enable the output, the CKOUTFuse has to be
programmed. This mode is suitable when the chip clock is used to
drive other cir-cuits on the system. The clock also will be output
during reset, and the normal operation of I/Opin will be overridden
when the fuse is programmed. Any clock source, including the
internal RCOscillator, can be selected when the clock is output on
CLKO. If the System Clock Prescaler isused, it is the divided
system clock that is output.
8.10 Timer/Counter OscillatorATmega48PA/88PA/168PA/328P uses the
same crystal oscillator for Low-frequency Oscillatorand
Timer/Counter Oscillator. See Low Frequency Crystal Oscillator on
page 32 for details onthe oscillator and crystal requirements.
ATmega48PA/88PA/168PA/328P share the Timer/Counter Oscillator
Pins (TOSC1 and TOSC2)with XTAL1 and XTAL2. When using the
Timer/Counter Oscillator, the system clock needs to befour times
the oscillator frequency. Due to this and the pin sharing, the
Timer/Counter Oscillatorcan only be used when the Calibrated
Internal RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK
in the ASSR Register iswritten to logic one. See Asynchronous
Operation of Timer/Counter2 on page 155 for furtherdescription on
selecting external clock as input instead of a 32.768 kHz watch
crystal.
8.11 System Clock PrescalerThe ATmega48PA/88PA/168PA/328P has a
system clock prescaler, and the system clock canbe divided by
setting the CLKPR Clock Prescale Register on page 377. This feature
can beused to decrease the system clock frequency and the power
consumption when the requirementfor processing power is low. This
can be used with all clock source options, and it will affect
theclock frequency of the CPU and all synchronous peripherals.
clkI/O, clkADC, clkCPU, and clkFLASHare divided by a factor as
shown in Table 28-3 on page 318.
Table 8-16. Start-up Times for the External Clock Selection
Power ConditionsStart-up Time from Power-
down and Power-saveAdditional Delay from
Reset (VCC = 5.0V) SUT1..0BOD enabled 6 CK 14CK 00Fast rising
power 6 CK 14CK + 4.1 ms 01Slowly rising power 6 CK 14CK + 65 ms
10
Reserved 11358161DAVR10/09
-
ATmega48PA/88PA/168PA/328PWhen switching between prescaler
settings, the System Clock Prescaler ensures that noglitches occurs
in the clock system. It also ensures that no intermediate frequency
is higher thanneither the clock frequency corresponding to the
previous setting, nor the clock frequency corre-sponding to the new
setting. The ripple counter that implements the prescaler runs at
thefrequency of the undivided clock, which may be faster than the
CPU's clock frequency. Hence, itis not possible to determine the
state of the prescaler - even if it were readable, and the
exacttime it takes to switch from one clock division to the other
cannot be exactly predicted. From thetime the CLKPS values are
written, it takes between T1 + T2 and T1 + 2 * T2 before the
newclock frequency is active. In this interval, 2 active clock
edges are produced. Here, T1 is the pre-vious clock period, and T2
is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special
write procedure must befollowed tochange the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one
and all other bitsin CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while
writing a zero to CLKPCE.Interrupts must be disabled when changing
prescaler setting to make sure the write procedure isnot
interrupted.368161DAVR10/09
-
ATmega48PA/88PA/168PA/328P8.12 Register Description
8.12.1 OSCCAL Oscillator Calibration Register
Bits 7..0 CAL7..0: Oscillator Calibration ValueThe Oscillator
Calibration Register is used to trim the Calibrated Internal RC
Oscillator toremove process variations from the oscillator
frequency. A pre-programmed calibration value isautomatically
written to this register during chip reset, giving the Factory
calibrated frequency asspecified in Table 28-1 on page 317. The
application software can write this register to changethe
oscillator frequency. The oscillator can be calibrated to
frequencies as specified in Table 28-1 on page 317. Calibration
outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write
accesses, and these writetimes will be affected accordingly. If the
EEPROM or Flash are written, do not calibrate to morethan 8.8 MHz.
Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the
oscillator. Setting this bit to 0 gives thelowest frequency range,
setting this bit to 1 gives the highest frequency range. The two
fre-quency ranges are overlapping, in other words a setting of
OSCCAL = 0x7F gives a higherfrequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the
selected range. A setting of 0x00gives the lowest frequency in that
range, and a setting of 0x7F gives the highest frequency in
therange.
8.12.2 CLKPR Clock Prescale Register
Bit 7 CLKPCE: Clock Prescaler Change EnableThe CLKPCE bit must
be written to logic one to enable change of the CLKPS bits. The
CLKPCEbit is only updated when the other bits in CLKPR are
simultaneously written to zero. CLKPCE iscleared by hardware four
cycles after it is written or when CLKPS bits are written.
Rewriting theCLKPCE bit within this time-out period does neither
extend the time-out period, nor clear theCLKPCE bit.
Bits 3..0 CLKPS3..0: Clock Prescaler Select Bits 3 - 0These bits
define the division factor between the selected clock source and
the internal systemclock. These bits can be written run-time to
vary the clock frequency to suit the applicationrequirements. As
the divider divides the master clock input to the MCU, the speed of
all synchro-nous peripherals is reduced when a division factor is
used. The division factors are given inTable 8-17 on page 38.
Bit 7 6 5 4 3 2 1 0(0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1
CAL0 OSCCALRead/Write R/W R/W R/W R/W R/W R/W R/W R/WInitial Value
Device Specific Calibration Value
Bit 7 6 5 4 3 2 1 0(0x61) CLKPCE CLKPS3 CLKPS2 CLKPS1 CLKPS0
CLKPRRead/Write R/W R R R R/W R/W R/W R/WInitial Value 0 0 0 0 See
Bit Description378161DAVR10/09
-
ATmega48PA/88PA/168PA/328PThe CKDIV8 Fuse determines the initial
value of the CLKPS bits. If CKDIV8 is unprogrammed,the CLKPS bits
will be reset to 0000. If CKDIV8 is programmed, CLKPS bits are
reset to0011, giving a division factor of 8 at start up. This
feature should be used if the selected clocksource has a higher
frequency than the maximum frequency of the device at the present
operat-ing conditions. Note that any value can be written to the
CLKPS bits regardless of the CKDIV8Fuse setting. The Application
software must ensure that a sufficient division factor is chosen
ifthe selected clock source has a higher frequency than the maximum
frequency of the device atthe present operating conditions. The
device is shipped with the CKDIV8 Fuse programmed.
Table 8-17. Clock Prescaler SelectCLKPS3 CLKPS2 CLKPS1 CLKPS0
Clock Division Factor
0 0 0 0 1
0 0 0 1 2
0 0 1 0 4
0 0 1 1 8
0 1 0 0 16
0 1 0 1 32
0 1 1 0 64
0 1 1 1 128
1 0 0 0 256
1 0 0 1 Reserved
1 0 1 0 Reserved
1 0 1 1 Reserved
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved388161DAVR10/09
-
ATmega48PA/88PA/168PA/328P9. Power Management and Sleep
ModesSleep modes enable the application to shut down unused modules
in the MCU, thereby savingpower. The AVR provides various sleep
modes allowing the user to tailor the power consump-tion to the
applications requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the
power supply voltage duringthe sleep periods. To further save
power, it is possible to disable the BOD in some sleep modes.See
BOD Disable on page 40 for more details.
9.1 Sleep ModesF igure 8 -1 on page 26 p resen ts the d i f fe
ren t c lock sys tems in t heATmega48PA/88PA/168PA/328P, and their
distribution. The figure is helpful in selecting anappropriate
sleep mode. Table 9-1 shows the different sleep modes, their wake
up sources BODdisable ability.
Notes: 1. Only recommended with external crystal or resonator
selected as clock source.2. If Timer/Counter2 is running in
asynchronous mode.3. For INT1 and INT0, only level interrupt.
To enter any of the six sleep modes, the SE bit in SMCR must be
written to logic one and aSLEEP instruction must be executed. The
SM2, SM1, and SM0 bits in the SMCR Register selectwhich sleep mode
(Idle, ADC Noise Reduction, Power-down, Power-save, Standby, or
ExtendedStandby) will be activated by the SLEEP instruction. See
Table 9-2 on page 44 for a summary.If an enabled interrupt occurs
while the MCU is in a sleep mode, the MCU wakes up. The MCUis then
halted for four cycles in addition to the start-up time, executes
the interrupt routine, andresumes execution from the instruction
following SLEEP. The contents of the Register File andSRAM are
unaltered when the device wakes up from sleep. If a reset occurs
during sleep mode,the MCU wakes up and executes from the Reset
Vector.
Table 9-1. Active Clock Domains and Wake-up Sources in the
Different Sleep Modes.Active Clock Domains Oscillators Wake-up
Sources
Softw
are
BOD
Disa
ble
Sleep Mode clk C
PU
clk F
LASH
clk IO
clk A
DC
clk A
SY
Mai
n Cl
ock
So
urce
En
able
d
Tim
er O
scilla
tor
Enab
led
INT1
, IN
T0 and
Pin
Change
TWI A
ddre
ss
Mat
ch
Tim
er2
SPM
/EEP
ROM
Rea
dy
ADC
WD
T
Oth
er I/
O
Idle X X X X X(2) X X X X X X X
ADC NoiseReduction X X X X
(2) X(3) X X(2) X X X
Power-down X(3) X X X
Power-save X X(2) X(3) X X X X
Standby(1) X X(3) X X XExtended Standby X
(2) X X(2) X(3) X X X X398161DAVR10/09
-
ATmega48PA/88PA/168PA/328P9.2 BOD DisableWhen the Brown-out
Detector (BOD) is enabled by BODLEVEL fuses, Table 27-7 on page
296,the BOD is actively monitoring the power supply voltage during
a sleep period. To save power, itis possible to disable the BOD by
software for some of the sleep modes, see Table 9-1 on page39. The
sleep mode power consumption will then be at the same level as when
BOD is globallydisabled by fuses. If BOD is disabled in software,
the BOD function is turned off immediatelyafter entering the sleep
mode. Upon wake-up from sleep, BOD is automatically enabled
again.This ensures safe operation in case the VCC level has dropped
during the sleep period.
When the BOD has been disabled, the wake-up time from sleep mode
will be approximately 60s to ensure that the BOD is working
correctly before the MCU continues executing code.
BOD disable is controlled by bit 6, BODS (BOD Sleep) in the
control register MCUCR, seeMCUCR MCU Control Register on page 44.
Writing this bit to one turns off the BOD in rele-vant sleep modes,
while a zero in this bit keeps BOD active. Default setting keeps
BOD active,i.e. BODS set to zero.
Writing to the BODS bit is controlled by a timed sequence and an
enable bit, see MCUCR MCU Control Register on page 44.
9.3 Idle ModeWhen the SM2..0 bits are written to 000, the SLEEP
instruction makes the MCU enter Idlemode, stopping the CPU but
allowing the SPI, USART, Analog Comparator, ADC, 2-wire
SerialInterface, Timer/Counters, Watchdog, and the interrupt system
to continue operating. This sleepmode basically halts clkCPU and
clkFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered
interrupts as well as internalones like the Timer Overflow and
USART Transmit Complete interrupts. If wake-up from theAnalog
Comparator interrupt is not required, the Analog Comparator can be
powered down bysetting the ACD bit in the Analog Comparator Control
and Status Register ACSR. This willreduce power consumption in Idle
mode. If the ADC is enabled, a conversion starts automati-cally
when this mode is entered.
9.4 ADC Noise Reduction ModeWhen the SM2..0 bits are written to
001, the SLEEP instruction makes the MCU enter ADCNoise Reduction
mode, stopping the CPU but allowing the ADC, the external
interrupts, the 2-wire Serial Interface address watch,
Timer/Counter2(1), and the Watchdog to continue operating(if
enabled). This sleep mode basically halts clkI/O, clkCPU, and
clkFLASH, while allowing the otherclocks to run.
This improves the noise environment for the ADC, enabling higher
resolution measurements. Ifthe ADC is enabled, a conversion starts
automatically when this mode is entered. Apart from theADC
Conversion Complete interrupt, only an External Reset, a Watchdog
System Reset, aWatchdog Interrupt, a Brown-out Reset, a 2-wire
Serial Interface address match, aTimer/Counter2 interrupt, an
SPM/EEPROM ready interrupt, an external level interrupt on INT0or
INT1 or a pin change interrupt can wake up the MCU from ADC Noise
Reduction mode.Note: 1. Timer/Counter2 will only keep running in
asynchronous mode, see 8-bit Timer/Counter2 with
PWM and Asynchronous Operation on page 144 for
details.408161DAVR10/09
-
ATmega48PA/88PA/168PA/328P9.5 Power-down ModeWhen the SM2..0
bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the external Oscillator is stopped,
while the external interrupts, the 2-wire Serial Interface address
watch, and the Watchdog continue operating (if enabled). Only
anExternal Reset, a Watchdog System Reset, a Watchdog Interrupt, a
Brown-out Reset, a 2-wireSerial Interface address match, an
external level interrupt on INT0 or INT1, or a pin changeinterrupt
can wake up the MCU. This sleep mode basically halts all generated
clocks, allowingoperation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up
from Power-down mode, the changedlevel must be held for some time
to wake up the MCU. Refer to External Interrupts on page 70for
details.
When waking up from Power-down mode, there is a delay from the
wake-up condition occursuntil the wake-up becomes effective. This
allows the clock to restart and become stable afterhaving been
stopped. The wake-up period is defined by the same CKSEL Fuses that
define theReset Time-out period, as described in Clock Sources on
page 27.
9.6 Power-save ModeWhen the SM2..0 bits are written to 011, the
SLEEP instruction makes the MCU enter Power-save mode. This mode is
identical to Power-down, with one exception:
If Timer/Counter2 is enabled, it will keep running during sleep.
The device can wake up fromeither Timer Overflow or Output Compare
event from Timer/Counter2 if the correspondingTimer/Counter2
interrupt enable bits are set in TIMSK2, and the Global Interrupt
Enable bit inSREG is set.
If Timer/Counter2 is not running, Power-down mode is recommended
instead of Power-savemode.
The Timer/Counter2 can be clocked both synchronously and
asynchronously in Power-savemode. If Timer/Counter2 is not using
the asynchronous clock, the Timer/Counter Oscillator isstopped
during sleep. If Timer/Counter2 is not using the synchronous clock,
the clock source isstopped during sleep. Note that even if the
synchronous clock is running in Power-save, thisclock is only
available for Timer/Counter2.
9.7 Standby ModeWhen the SM2..0 bits are 110 and an external
crystal/resonator clock option is selected, theSLEEP instruction
makes the MCU enter Standby mode. This mode is identical to
Power-downwith the exception that the Oscillator is kept running.
From Standby mode, the device wakes upin six clock cycles.
9.8 Extended Standby ModeWhen the SM2..0 bits are 111 and an
external crystal/resonator clock option is selected, theSLEEP
instruction makes the MCU enter Extended Standby mode. This mode is
identical toPower-save with the exception that the Oscillator is
kept running. From Extended Standbymode, the device wakes up in six
clock cycles.418161DAVR10/09
-
ATmega48PA/88PA/168PA/328P9.9 Power Reduction RegisterThe Power
Reduction Register (PRR), see PRR Power Reduction Register on page
45, pro-vides a method to stop the clock to individual peripherals
to reduce power consumption. Thecurrent state of the peripheral is
frozen and the I/O registers can not be read or written.Resources
used by the peripheral when stopping the clock will remain
occupied, hence theperipheral should in most cases be disabled
before stopping the clock. Waking up a module,which is done by
clearing the bit in PRR, puts the module in the same state as
before shutdown.
Module shutdown can be used in Idle mode and Active mode to
significantly reduce the overallpower consumption. In all other
sleep modes, the clock is already stopped.
9.10 Minimizing Power ConsumptionThere are several possibilities
to consider when trying to minimize the power consumption in anAVR
controlled system. In general, sleep modes should be used as much
as possible, and thesleep mode should be