At91-Arm9 Board Design Faq 2006-08-30

8/3/2019 At91-Arm9 Board Design Faq 2006-08-30

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AT91 Microcontroller

April 2005 v1.0 2

AT91RM9200DKs Early Development Kit for the AT91RM9200

s Now replaced by the AT91RM9200EK

s Main differences- Less interfaces

- No buffering


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April 2005 v1.0 3

Designs based on the AT91RM9200DKs JTAG Reset

s Enabling Buffers on Databus

s CompactFlash Interface

s SSC incompatability with AC97s Pullups on MMC connector

s Limited speed on SPI bus in block mode (Errata #13).

s Initial USB Functionality

s

USB host port #2 not connected in TQFP package


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April 2005 v1.0 4

Jtag Resets The JTAG TRST reset pin must get a valid reset at startup

s If not the CPU may or may not boot properly.

s Freezing spray or heating up CPU may release CPU

- Real issue is lack of JTAG reset


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April 2005 v1.0 5

JTAGSEL Signals This signal allows to select the use of the JTAG Port:

s A low level on the JTAGSEL allows to select the ARM9's ICE

s A high level on the JTAGSEL allows to select the Boundary Scanfunction.


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April 2005 v1.0 6

NWAITs A low level input on NWAIT (PC6) disables the CPU clock.

s This does not depend on the PIO A setting.

s Setting PC6 in PIO Mode will not disable the NWAIT function

- see the AT91RM9200 errata


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April 2005 v1.0 7

Crystal on XIN/XOUTs If the crystal has a nominal frequency of less than 8 MHz, then

a 1 kohm series resistor should be connected to the XOUT pin.


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April 2005 v1.0 8

Reset Pulsewidths The CPU needs a power up reset pulse of 900 ms.

- This is to cover the 32 kHz oscillator startup.

s Warm reset (when 32 kHz oscillator is running) is 92 us.

s Most reset circuits generate less

s Reset Circuits with > 1 s, can generate up to 3 seconds- The MAX6390 used on the DK is 1120 .. 2420 ms.

s The DS1834AS on the AT91RM9200EK is outside the spec.- Known bug of the EK. (300 ms only).

- Typical oscillators starts up in 350 ms so it normally works anyway.

s ATtiny13 as system MCU?

s

Texas Instruments TPS3803?


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April 2005 v1.0 9

ATtiny13 can be used fors Power On Reset

- Precise Reset width

s Brownout protection

s Watchdogs Reset Button

- Debounce

- Short pulse (< 2 s) normal reset

- Medium Pulse (2..10 s) Turn On/Off Watchdog

- Long pulse (> 10 s) Set BMS high - force into Boot Monitor

s LED Status

s Larger AVRs can be used to increase functionality.

s Application code available from [email protected]


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April 2005 v1.0 10

ATtiny13 Block Diagram

ATtiny13

/RESET

BMS

WDOG_ENA

WDOG

+

+

LED

SWITCH


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April 2005 v1.0 12

Adress Bus 24s Not routed on the chip

s Maximum contiguos memory is 16 MB

s A 32 MB memory needs to use [A25,A23..A1]

- Will create a 16MB hole between two 16 MB memory areas


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April 2005 v1.0 13

BMS (Boot Mode Select) pin

s BMS = 0

- The CPU boots from external 16 bit Flash memory

- Can be jumpered to 1 during production/upgrade

Allows simple flash programming

s BMS = 1

- CPU boots from the internal bootROM

- No jumper needed for production programming


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April 2005 v1.0 14

SDRAM controller

s A2 on the CPU shall be connected to A0 on the SDRAM

s The SDRAM Controller datasheet shows A0 connected to SDRAM

A0

s The SDRAM controller is however routed through the External

Bus Interface which shifts the SDRAM controller A0 to the A2 pin

of the chip


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April 2005 v1.0 15

CompactFlash interfaces Only functional in memory mode on the DK.

s Buffers Enable need to take care of more signals

- See FAQ at http://www.atmel.com/

s Interrupts from card not supported on the DK,

Neccessary in most case

s Early AT91RM9200DKs had layout bugs on the CF interface

- /RD, /WR swapped etc.

s True-IDE requires extra decoding - not supported by CPU

- See IDE Application Note


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April 2005 v1.0 16

AC-97s AC-97 requires a clock speed of 24.xx MHz.

s The SSC cannot run that fast and only supports

one timeslot in each direction.

s Workaround is to use I2S codec with less functionality.

s AC-97 needs several timeslots. May be difficult to handle.

s Atmel is designing an AC97 controller for future chips.


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April 2005 v1.0 17

Pullup on MMC connectors The pullups on the DK are the wrong values for MMC_CMD

s Trig on the first low to high transition of the CMD signal, use

analog input on scope.

While the bus is in open-drain mode (and 400kHz clk), the CMDsignal looks like a RC low-pass filter with tau somewhere around

0.25 us, which is too slow.

s The most important issue was to pull-up the MMC_CMD line with

a rather small resistor. (my temporary fix is to use a 2k2 pull-up

resistor - this is probably NOT a good long term solution)s The EK and DK does not use the same signals for this mux

EK=PB22, DK=PB7


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April 2005 v1.0 18

Limited Speed of SPI in block modes Errata #13 causes the SPI chip select to go inactive if the PDC

does not get enough cycles.

s Only happens on block transfers

s

Never happens on 8/16 bit transferss Dataflashboot 1.02 siffers from the problem, needs update!

s Typically happens during heavy networking activity

- WLAN on Compactflash

s Workaround:

- Reduce the speed of SPI (4 Mbps seems OK)

- Force CS low using external H/W

s Errata #13 is fixed on new parts


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April 2005 v1.0 19

UART

s When using flow control, speed is limited to 750 kBAUD

s When Hardware Handshaking is used and if CTS goes low near

the end of the start bit of the transmitter, a character can be lost.

s

Problems CTS must not go low during a time slot occuring between 2

Master Clock periods before the starting bit and 16 Master Clock

periods after the rising edge of the starting bit.

s Fix/Workaround

- Use the Falling Edge of SCK to sync the CTS signal- Use the Falling Edge of TXD to clock a flip flop to assert

Connect the CTS to the asynch set/clear of the flipflop to deassert


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April 2005 v1.0 20

TWI

s The TWI Linux 2.4 driver has significant problems

s TWI under 2.6 is significantly better

s Still random errors occur

s Recommendation:- Solder two 10pF capacitors very next to the AT91RM9200

Between SDA and ground

Between SCL and ground


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April 2005 v1.0 21

Initial USB functionality in BootROMs The BootROM assumes that the CPU has an 18.432 MHz XTAL

s USB will not be functional with another XTAL frequency

- USB DFU is not available when another speed is used.

s UART download is OK, due to Autobaud feature.


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April 2005 v1.0 22

USB Host Port #2 not connecteds Only affected in TQFP version

s Linux 2.4 will report an error on host port #2

s Believe fixed in Linux-2.6

s S/W workaround


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April 2005 v1.0 23

USB Host Power Management

s Nothing Implemented on the EK.


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April 2005 v1.0 24

s Pull-up is active by default after reset (required by the boot application)

s No pull-down: DM is floating when the peripheral is disconnected

s The application shall monitor Vbus to remove the pull-up when the host

switches off

AT91RM9200EK schematics

1.5K

5V Vbus monitoring

Pull-up is active by default after reset

Capacitors

not needed


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April 2005 v1.0 25

USB Client

s Cannot be bus powered

s Required to handle pullup on USB bus within 100 ms

s Reset time is 900 ms.

s Also hard to handle suspend current of 500 uA.


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April 2005 v1.0 26

Recommended Layouts Atmel does not supply a recommended layout at this time.


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April 2005 v1.0 27

Recommended solder temp profile

s All our products are compliant with JEDEC J-STD-20 Reflow

profile, and the moisture sensitivity to this product is LEVEL 3

with 220C max reflow temperature.

s This is for CI parts (not RoHS)


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April 2005 v1.0 28

Battery Backup of RTCs RTC is not backed up.

s May need external RTC on the AT91RM9200.

Is fixed on later generation chips like the AT91SAM9261


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April 2005 v1.0 29

If the 32 KHz does not work!!!

s TST0,TST1 must be connected to Ground


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April 2005 v1.0 30

Ethernet Clock

s Using a clock generated by the onchip PLL is not advisable

s Use a separate crystal for the Ethernet PHY.

- Check with your PHY vendor


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April 2005 v1.0 31

AT91RM9200 Ethernet Packet Loss

s Some switches cannot handle 100 Mbit Full Duplex properly

s The problem only occurs when connecting through a low cost

Ethernet switch (D-Link DGS-1008 etc.)

s

Multicasting is especially problematic.

s They had set originally set the PHY to 100 Mbit Full Duplex.

s The switch starts auto-negotiation, detects the 100 Mbps speed

and configures itself as 100 Mbit Half-Duplex.The mismatch

betweent the AT91 FD and the switch HD results in packet loss.s Strapping the PHY to auto-negotiation or half-duplex seems to

resolve the problem.


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April 2005 v1.0 32

Flash

s The AT91RM9200 can work with Parallel or serial flash

s Serial Flash = Dataflash or Serial EEPROM.

s Serial EEPROM is not available on the AT91SAM9261.

s Dataflash has smaller footprint

s Available up to 64 Mbit today (August 2005).

128 Mbit soon to be released (2006?)

s 8 pin SO footprint (CASON package)

s Supported on U-boot/Linux 2.6.12 (JFFS2 support)

s Atmel has 32/64/128 Mbit parallel flash (also Strataflash 2nd

src)


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April 2005 v1.0 33

Investigating SDRAM problems

s Several problems can *appear* to be SDRAM related

- Actually isn't.

s

Symptom:- CPU sometimes getting bad data from the SDRAM.

- Setting the CPU/MCK ratio to 90/45 makes the problem go away.

s Crashing in random places:

- Some voltage or current supply is usually marginal.

- Something happens which causes the CPU to draw extra current


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April 2005 v1.0 34

Investigating SDRAM errors

s Check your CPU and PLL voltage supplies for glitches and

dropouts around the time of the error.

- We changed/removed an inductor near the PLL circuit and the

problem went away.

s Run all memory tests from the CPU's internal memory

- Perform full memory tests

(Needs modified Romboot/DataflashBoot to do this).

- Run at full speed, not the default 48 MHz master clock


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April 2005 v1.0 35

Investigating SDRAM problems

s If you based your board on the DK, then you would be initializing theSDRAM in ROMBOOT so you can transfer U-Boot from Dataflash to theSDRAM, and then run U-Boot from SDRAM. U-Boot should not configurethe SDRAM. Is this the case?

s Did you set/change your CPU/master_clock ratio correctly?

- usually is 180/60s Have you tried running at a slower speed?

- e.g. 90/45 is a good setting to try.You have to make the change in romboot and inu-boot/include/configs/yourboard.h

s Have you double checked you SDRAM clock? usually is 60MHzs Did you calculate SDRAMC_CR correctly?s Did you calculate SDRAMC_TR correctly?s Did you set the bus width correctly?s Does it always crash in the same place?

- if it does, then you can probably isolate it.s Do other boards crash in exactly the same place?


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April 2005 v1.0 36

Running the AT91RM9200 at full speed

s Program the PLL and enable it.

s Write to CP15 to switch from Fast Clock to Asynchronous Clock

s Enable the Instruction Cache

s Enable the MMU (Without the MMU, the Data cache is disabled)s Enable the Datacache

s Ensure that the MMU page table entries are cacheable.

s Ensure minimum waitstates are used

s NWAIT must not be floating


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April 2005 v1.0 37

Enabling cache

s If the PDC writes to an area of memory which is already inside the

datacache,

the PDC values will not be visible until the cache is flushed!

s Set the PDC buffers to be non-cacheable in the page tables.


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April 2005 v1.0 38

AT91SAM9261 JTAG Speed

s The AT91SAM9261 starts from 32 kHz

s The ARM926E core inside uses a synchronous JTAG Interface

- Max JTAG Speed (using J-Link) = CPU clock / 6

s

32.768 kHz / 6 = 5.45 kHz

s Only an issue if you do not use SAMBA BootROM and try to load

the initial program using JTAG


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April 2005 v1.0 39

ATSAM9261 BMS Pulldown

s The Boot Mode Select pin "Rpullup" has a typo in the datasheet

s (page 606).

s

It claims:Minimum: 70kOhm, Typical: 10kOhm, Maximum: 175kOhm...

s Early tests point to 15 kOhm.

s 1 kOhm pulldown was neccessary for one customer to force

booting from external memory


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April 2005 v1.0 40

AT91SAM9261 Watchdog

s The BootROM disables the Watchdog PERMANENTLY

s If the Watchdog is needed, then the BootROM cannot be used

- A possible workaround is to use an external Watchdog

s

This is an official Errata


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April 2005 v1.0 41

SAM9261 Battery backup

s The CPU needs to have ~1.2V operation.

s A clock battery is 1.5V


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April 2005 v1.0 42

SAM9261EK Embedded trace

s While the PCB supports the Embedded Trace, the connector is

not mounted on board


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April 2005 v1.0 43

AT91SAM9261EK Dataflashcard support

s If the jumper J21 is in the 1-2 position

- NPCS0 is connected to the internal dataflash

s If the Jumper J21 is in the 2-3 position

-NPCS0 is connected to the dataflashcard- It is ALSO connected to NPCS3

s When J21 2-3 is connected, the NPCS3 output must be disabled


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April 2005 v1.0 44

AT91SAM9261EK Dataflashcard support

s The AT91SAM9261 BootROM disables NPCS3

s Dataflashboot and U-Boot does NOT disabled NPCS3.

- It is currently not useful to connect J21 2-3

s Dataflashboot and U-Boot must reside on the internal flash

- Fix is simple though

s When J21 is 1-2, the Dataflashcard is available on NPCS3

- Address 0xD000_0000


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AT91SAM9261EK recommended

Dataflashcard connection

NPCS0

NPCS3

DF_CS

DFC_CS

NPCS0

NPCS3

DF_CS

DFC_CS

Current Implementation Proposed Implementation

At91-Arm9 Board Design Faq 2006-08-30

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