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    UM10139LPC214x User manual

    Rev. 4 23 April 2012 User manual

    Document information

    Info Content

    Keywords LPC2141, LPC2142, LPC2144, LPC2146, LPC2148, LPC2000, LPC214x,ARM, ARM7, embedded, 32-bit, microcontroller, USB 2.0, USB device

    Abstract LPC214x User Manual

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    UM10139 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved.

    User manual Rev. 4 23 April 2012 2 of 354

    Contact information

    For more information, please visit: http://www.nxp.com

    For sales office addresses, please send an email to: [email protected]

    NXP Semiconductors UM10139LPC2141/2/4/6/8

    Revision history

    Rev Date Description

    4 20120423 Modifications:

    Device revision register added (see Section 21.8.11). Bit PCUSB in the PCONP register must be set to one to access the USB SRAM (see

    Table 31).

    3 20101004 Modifications:

    New document template applied. I2C chapter: multiple errors corrected (Chapter 14 LPC214x I2C-bus interface

    I2C0/1).

    IAP call example updated (Section 21.9). WDFEED register description updated Section 16.4.3 Watchdog Feed register

    (WDFEED - 0xE000 0008).

    RTC usage note updated (Section 18.5 RTC usage notes). CTCR register bit description corrected (Section 18.4.4 Clock Tick Counter Register

    (CTCR - 0xE002 4004)). PINSEL2 register description updated (Section 6.4.3 Pin function Select register 2

    (PINSEL2 - 0xE002 C014)).

    PWM TCR register bit 3 description updated (Section 16.4.2 PWM Timer ControlRegister (PWMTCR - 0xE001 4004)).

    U0IER register bit description corrected (Section 10.3.6 UART0 Interrupt EnableRegister (U0IER - 0xE000 C004, when DLAB = 0)).

    U1IER register bit description corrected (Section 11.3.6 UART1 Interrupt EnableRegister (U1IER - 0xE001 0004, when DLAB = 0)).

    Pin description updated for VBAT, VREF, and RTCX1/2 (Section 5.2 Pin description forLPC2141/2/4/6/8).

    SSP CR0 register corrected (Section 13.4.1 SSP Control Register 0 (SSPCR0 -

    0xE006 8000)). ADC maximum voltage updated (Table 278 ADC pin description). Minimum DLL value for use with fractional divider corrected (Section 10.3.4 UART0

    Fractional Divider Register (U0FDR - 0xE000 C028) and Section 11.3.4 UART1Fractional Divider Register (U1FDR - 0xE001 0028)).

    CRP levels updated (Section 21.7 Code Read Protection (CRP)). Numerous editorial updates throughout the user manual.

    2 20061030 LPC2141/2/4/6/8 user manual

    1 20050815 Initial version

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    UM10139 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved.

    User manual Rev. 4 23 April 2012 3 of 354

    1.1 IntroductionThe LPC2141/2/4/6/8 microcontrollers are based on a 32/16 bit ARM7TDMI-S CPU with

    real-time emulation and embedded trace support, that combines the microcontroller with

    embedded high speed flash memory ranging from 32 kB to 512 kB. A 128-bit widememory interface and a unique accelerator architecture enable 32-bit code execution at

    the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb

    mode reduces code by more than 30 % with minimal performance penalty.

    Due to their tiny size and low power consumption, LPC2141/2/4/6/8 are ideal for

    applications where miniaturization is a key requirement, such as access control and

    point-of-sale. A blend of serial communications interfaces ranging from a USB 2.0 Full

    Speed device, multiple UARTs, SPI, SSP to I2Cs, and on-chip SRAM of 8 kB up to 40 kB,

    make these devices very well suited for communication gateways and protocolconverters, soft modems, voice recognition and low end imaging, providing both large

    buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s),

    10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive

    external interrupt pins make these microcontrollers particularly suitable for industrial

    control and medical systems.

    1.2 Features

    16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

    8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory.

    128 bit wide interface/accelerator enables high speed 60 MHz operation.

    In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms.

    EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with theon-chip RealMonitor software and high speed tracing of instruction execution.

    USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.

    In addition, the LPC2146/8 provide 8 kB of on-chip RAM accessible to USB by DMA.

    One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of 6/14analog inputs, with conversion times as low as 2.44 s per channel.

    Single 10-bit D/A converter provides variable analog output.

    Two 32-bit timers/external event counters (with four capture and four comparechannels each), PWM unit (six outputs) and watchdog.

    Low power real-time clock with independent power and dedicated 32 kHz clock input.

    Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.

    Vectored interrupt controller with configurable priorities and vector addresses.

    Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.

    Up to nine edge or level sensitive external interrupt pins available.

    UM10139Chapter 1: Introductory information

    Rev. 4 23 April 2012 User manual

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    UM10139 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved.

    User manual Rev. 4 23 April 2012 4 of 354

    NXP Semiconductors UM10139Chapter 1: Introductory information

    60 MHz maximum CPU clock available from programmable on-chip PLL with settlingtime of 100 s.

    On-chip integrated oscillator operates with an external crystal in range from 1 MHz to30 MHz and with an external oscillator up to 50 MHz.

    Power saving modes include Idle and Power-down.

    Individual enable/disable of peripheral functions as well as peripheral clock scaling foradditional power optimization.

    Processor wake-up from Power-down mode via external interrupt, USB, Brown-OutDetect (BOD) or Real-Time Clock (RTC).

    Single power supply chip with Power-On Reset (POR) and BOD circuits:

    CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/Opads.

    1.3 Applications

    Industrial control

    Medical systems

    Access control

    Point-of-sale

    Communication gateway

    Embedded soft modem

    General purpose applications

    1.4 Device information

    [1] While the USB DMA is the primary user of the additional 8 kB RAM, this RAM is also accessible at any time by the CPU as a general

    purpose RAM for data and code storage.

    1.5 Architectural overview

    The LPC2141/2/4/6/8 consists of an ARM7TDMI-S CPU with emulation support, the

    ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced

    High-performance Bus (AHB) for interface to the interrupt controller, and the ARM

    Table 1. LPC2141/2/4/6/8 device information

    Device Number

    of pins

    On-chip

    SRAM

    Endpoint

    USB RAM

    On-chip

    FLASH

    Number of

    10-bit ADC

    channels

    Number of

    10-bit DAC

    channels

    Note

    LPC2141 64 8 kB 2 kB 32 kB 6 - -

    LPC2142 64 16 kB 2 kB 64 kB 6 1 -

    LPC2144 64 16 kB 2 kB 128 kB 14 1 UART1 with fullmodem interface

    LPC2146 64 32 kB + 8 kB[1] 2 kB 256 kB 14 1 UART1 with fullmodem interface

    LPC2148 64 32 kB + 8 kB[1]

    2 kB 512 kB 14 1 UART1 with fullmodem interface

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    UM10139 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved.

    User manual Rev. 4 23 April 2012 5 of 354

    NXP Semiconductors UM10139Chapter 1: Introductory information

    Peripheral Bus (APB, a compatible superset of ARMs AMBA Advanced Peripheral Bus)

    for connection to on-chip peripheral functions. The LPC2141/24/6/8 configures the

    ARM7TDMI-S processor in little-endian byte order.

    AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the

    4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address spacewithin the AHB address space. LPC2141/2/4/6/8 peripheral functions (other than theinterrupt controller) are connected to the APB bus. The AHB to APB bridge interfaces the

    APB bus to the AHB bus. APB peripherals are also allocated a 2 megabyte range of

    addresses, beginning at the 3.5 gigabyte address point. Each APB peripheral is allocated

    a 16 kB address space within the APB address space.

    The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block

    (see chapter "Pin Connect Block" on page 58). This must be configured by software to fit

    specific application requirements for the use of peripheral functions and pins.

    1.6 ARM7TDMI-S processor

    The ARM7TDMI-S is a general purpose 32-bit microprocessor,

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