ARM Processor September 2005 Introduction The ARM processor core originates within a British computer company called Acorn. In the mid-1980s they were looking for replacement for the 6502 processor used in their BBC computer range, which were widely used in UK schools. None of the 16-bit architectures becoming available at that time met their requirements, so they designed their own 32-bit processor. Other companies became interested in this processor, including Apple who were looking for a processor for their PDA project (which became the Newton). After much discussion this led to Acorn’s processor design team splitting off from Acorn at the end of 1990 to become Advanced RISC Machines Ltd, now just ARM Ltd. Thus ARM Ltd now designs the ARM family of RISC processor cores, together with a range of other supporting technologies. One important point about ARM is that it does not fabricate silicon itself, but instead just produces the design. The ARM processor is a powerful low- cost, efficient, low-power (consumption, that is) RISC processor. Its design was originally for the Archimedes Dept. of Computer Science Model Engineering College 1
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ARM Processor September 2005
Introduction
The ARM processor core originates within a British computer
company called Acorn. In the mid-1980s they were looking for replacement for
the 6502 processor used in their BBC computer range, which were widely used
in UK schools. None of the 16-bit architectures becoming available at that time
met their requirements, so they designed their own 32-bit processor.
Other companies became interested in this processor, including
Apple who were looking for a processor for their PDA project (which became the
Newton). After much discussion this led to Acorn’s processor design team
splitting off from Acorn at the end of 1990 to become Advanced RISC Machines
Ltd, now just ARM Ltd.
Thus ARM Ltd now designs the ARM family of RISC processor
cores, together with a range of other supporting technologies. One important
point about ARM is that it does not fabricate silicon itself, but instead just
produces the design.
The ARM processor is a powerful low-cost, efficient, low-power
(consumption, that is) RISC processor. Its design was originally for the
Archimedes desktop computer, but somewhat ironically numerous factors about
its design make it unsuitable for use in a desktop machine (for example, the
MMU and cache are the wrong way around). However, many factors about its
design make it an exceptional choice for embedded applications. The ARM
architecture enjoys the widest choice of embedded operating systems (OS) for
system development. OS choice is critical in producing a winning system design
that meets the needs of the developer's chosen market. ARM enables choice by
partnering with many leading suppliers of embedded OS and development
environments. ARM offers a broad range of processor cores to address a wide
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variety of applications while delivering optimum performance, power consumption
and system cost. These cores are designed to meet the needs of three system
categories:
Embedded real-time systems
Embedded real-time systems for storage, automotive body and
power-train, industrial and networking applications
Application platforms
Devices running open operating systems including Linux, Palm OS,
Symbian OS and Windows CE in wireless, consumer entertainment
and digital imaging applications
Secure applications
Smart cards, SIM cards and payment terminals
ARM CPU cores cover a wide range of performance and features
enabling system designers to create solutions that meet their precise
requirements. ARM offers both synthesizable and hard macro products, together
with a range of coprocessors and debug facilities.
“ATAP” stands for ARM Technology Access Program. Creates a
network of independent design service companies and equips them to deliver
ARM-powered designs. Members get access to ARM technology, expertise and
support. Members sometimes referred to as “Approved Design Centers”.
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Why ARM
The main features of ARM processor that makes it outstanding are :-
Built-in architecture extensions - more efficient processing of algorithms to save
CPU overhead, memory and power.
Technologies it uses are
Thumb®2 -Greatly improved code density
DSP - signal process directly in the RISC core
Jazelle® - Java acceleration;
TrustZone™ - Hardware/Software environment for maximum security
Core performance - Through a wide range of functionality and power, parts
running from 1MHz to 1 GHz with architectural performance enhancements for
media and Java.
Tools of choice – ARM has the widest range of hardware and software tools
support of any 32 bit architecture.
Extensive ecosystem of networking ASICs and standard products/ASSPs - more
than 125 standard networking devices for quick time-to-market design cycles.
Wide support - ARM is the best supported microprocessor architecture available.
A wide range of OS, Middleware and tools support an extensive choice of
multimedia codec solutions optimized for ARM processors, are available from the
ARM Connected Community
Physical IP - leading edge for high performance systems
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Design notes
The ARM instruction set follows the 6502 in concept, but includes a number
of features designed to allow the CPU to better pipeline them for execution. In
keeping with traditional RISC concepts, this included tuning the commands to
execute in well-defined times, typically one cycle. A more interesting addition to
the ARM design is the use of a 4-bit condition code on the front of every
instruction, meaning that every instruction can be made a conditional.
This cuts down significantly on the space available for, for example,
displacements in memory access instructions, but on the other hand it does
make it possible to avoid branch instructions when generating code for small if
statements. The standard example of this is Euclid’s GCD algorithm:
(This example is in the C programming language)
int gcd(int i, int j)
{
while (i != j)
if (i > j)
i -= j;
else
j -= i;
return i;
}
Expressed in ARM assembly, the loop, with a little rotation, might look something
like
b test
loop subgt Ri,Ri,Rj
suble Rj,Rj,Ri
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test cmp Ri,Rj
bne loop
which avoids the branches around the then and else clause that one would
typically have to emit.
Another unique feature of the instruction set is the ability to fold shifts
and rotates into the "data processing" (arithmetic, logical, and register-register
move) instructions, so that, for example, the C statement "a += (j << 2);" could be
rendered as a single instruction on the ARM, register allocation permitting.
This results in the typical ARM program being denser than what would
normally be expected of a RISC processor. This implies that there is less need
for load/store operations and that the pipeline is being used more efficiently.
Even though the ARM runs at what many would consider to be low speeds, it
nevertheless competes quite well with much more complex CPU designs.
The ARM processor also has some features rarely seen on other
architectures that are considered RISC, such as PC-relative addressing (indeed,
on the ARM the PC is one of its 16 registers) and pre- and post-increment
addressing modes.
Another item of note is that the ARM has been around for a while, with
the instruction set increasing somewhat over time. Some early ARM processors
(prior to ARM7TDMI), for example, have no instruction to load a two-byte
quantity, so that, strictly speaking, for them it's not possible to generate code that
would behave the way one would expect for C objects of type "volatile short".
There are lots of things which determine the power consumption of a
processor. The most influential on transistor level are the supply voltage, clock-
speed, number of switching transistors and to a lesser extent the transistor
leakage. By lowering supply voltage, the power requirements drop dramatically.
The maximum work frequency drops as well, further lowering power. By only
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powering the parts of the chip that are actually doing some work, you save even
more. If you have a simple implementation with shallow pipelines, using low
amounts of transistors, you are in an even better position.
The low power consumption is because it has approximately 1/25th of
the number of gates of a Pentium. The high performance is because it's designed
better than the Pentium. It doesn't have all the excess baggage the Pentium
carries around with it to make it backwards-compatible with the 486, 386, 286,
186 and 8086. The 8086 was a CISC design anyway, as are all its successors,
whilst the ARM is a RISC design. RISC design is about implementing those
instructions that are used frequently and anything else can be synthesized from
them. CISC design is about throw in a kitchen sink instruction and anything else
you can think of just in case somebody might want to use them. With RISC
design you can make certain simplifications that speed things up - you can
design the instruction decode using hardwired gates but CISC is so complicated
that you have to use microcode which is inherently slower. As far as RISC goes,
the ARM has some wrinkles of its own that add to its performance. The ability to
place a conditional flag on any instruction and to determine whether instructions
can or cannot affect processor flags means that you can often avoid branches
which result in instruction stalls or other slowdowns (on processors that don't
have this ability then you have to add loads of power-consuming extra logic to try
and compensate for branch stalls).
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ARM Processor September 2005
Programmers Model
Data size and instruction sets
The ARM is a 32-bit architecture. The cause of confusion here is the
term “word” which will mean 16-bits to people with a 16-bit background. In the
ARM world 16-bits is a “half word” as the architecture is a 32-bit one, whereas
“word” means 32-bits.
Jazelle cores can also execute Java byte code Java byte codes are
8-bit instructions designed to be architecture independent. Jazelle
transparently executes most byte codes in hardware and some in highly
optimized ARM code. This is due to a tradeoff between hardware complexity
(power consumption & silicon area) and speed.
Most ARM’s implement two instruction sets - 32-bit ARM Instruction
Set and 16-bit Thumb Instruction Set
Processor Modes
The ARM has seven basic operating modes:
User: unprivileged mode under which most tasks run.
FIQ: entered when a high priority (fast) interrupt is raised.
IRQ: entered when a low priority (normal) interrupt is raised.
Supervisor: entered on reset and when a Software Interrupt instruction is executed.
Abort: used to handle memory access violations.
Undef: used to handle undefined instructions.
System: privileged mode using the same registers as user mode.
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Each key press will switch mode from user -> FIQ ->user -> IRQ ->
user ->SVC -> User -> Undef -> User -> Abort and then back to user.
The Programmers Model can be split into two elements - first of all,
the processor modes and secondly, the processor registers. So let’s start by
looking at the modes.
Now the typical application will run in an unprivileged mode know as
“User” mode, whereas the various exception types will be dealt with in one of the
privileged modes: Fast Interrupt, Supervisor, Abort, Normal Interrupt and
Undefined.
One question here is what is the difference between the privileged
and unprivileged modes? Well in reality very little really - the ARM core has an
output signal (nTRANS on ARM7TDMI, InTRANS, DnTRANS on 9, or encoded
as part of HPROT or BPROT in AMBA) which indicates whether the current mode
is privileged or unprivileged, and this can be used, for instance, by a memory
controller to only allow IO access in a privileged mode. In addition some
operations are only permitted in a privileged mode, such as directly changing the
mode and enabling of interrupts. All current ARM cores implement system mode
(added in architecture v4). This is simply a privileged version of user mode.
Important for re-entrant exceptions because no exceptions can cause system
mode to be entered.
The ARM Register Set
The ARM architecture provides a total of 37 registers, all of which are
32-bits long. 1 dedicated program counter, 1 dedicated current program status
register, 5 dedicated saved program status registers, 30 general purposes
registers .However these are arranged into several banks, with the accessible
bank being governed by the current processor mode. In summary though, in
each mode, the core can access: a particular set of 13 general purposes
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registers (r0 - r12), particular r13 - which is typically used as a stack pointer. This
will be a different r13 for each mode, so allowing each exception type to have its
own stack and particular r14 - which is used as a link (or return address) register.
Again this will be a different r14 for each mode.,r15 - whose only use is as the
Program counter.
The CPSR (Current Program Status Register) - this stores additional
information about the state of the processor: And finally in privileged modes
(except system), a particular SPSR (Saved Program Status Register). This stores
a copy of the previous CPSR value when an exception occurs. This combined
with the link register allows exceptions to return without corrupting processor
state.
Program Status Registers
Condition code flags
N = Negative result from ALU Z = Zero result from ALU
C = ALU operation Carried out V = ALU operation oVerflowed
Sticky Overflow flag - Q flag used to indicates if saturation has occurred
And used only in Architecture 5TE/J.
J bit used in Architecture 5TEJ only, and J = 1indicates that Processor in Jazelle
state.
Interrupt Disable bits.
I = 1: Disables the IRQ. F = 1: Disables the FIQ.
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31N Z C V Q
28 67
I F T mode16
23
815
5 4 024
f s x c
U n d e f i n e dJ
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ARM Processor September 2005
T Bit used in Architecture xT only, and T = 0: Processor in ARM state, T = 1:
Processor in Thumb state
Mode bits Specifies the processor mode.
Program Counter
ARM runs in three different states, which are ARM state, Thumb state and
Jazelle state.
ARM is designed to efficiently access memory using a single memory
access cycle. So word accesses must be on a word address boundary, half-
word accesses must be on a half-word address boundary. This includes
instruction fetches. Point out that strictly, the bottom bits of the PC simply do not
exist within the ARM core - hence they are ‘undefined’. Memory system must
ignore these for instruction fetches.
When the processor is executing in ARM state, All instructions are 32 bits
wide and All instructions must be word aligned .Therefore the pc value is stored
in bits [31:2] with bits [1:0] undefined (as instruction cannot be half word or byte
aligned).
When the processor is executing in Thumb state all instructions are 16 bits
wide, all instructions must be half-word aligned. Therefore the pc value is stored
in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned).
In Jazelle state, the processor doesn’t perform 8-bit fetches from memory.
Instead it does aligned 32-bit fetches (4-byte prefetching) which is more efficient.
Note we don’t mention the PC in Jazelle state because the ‘Jazelle PC’ is
actually stored in r14 - this is technical detail that is not relevant as it is
completely hidden by the Jazelle support code.
When the processor is executing in Jazelle state, all instructions are 8 bits
wide Processor performs a word access to read 4 instructions at once.
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Exception Handling
When an exception occurs, the ARM, Copies CPSR into
SPSR_<mode>,Sets appropriate CPSR bits ,Change to ARM state, Change
to exception mode ,Disable interrupts (if appropriate),Stores the return
address in LR_mode>,Sets PC to vector address
To return, exception handler needs to Restore CPSR from SPSR_<mode>
and Restore PC from LR_<mode>
This can only be done in ARM state.
Exception handling on the ARM is controlled through the use of an area of
memory called the vector table. This lives (normally) at the bottom of the memory
map from 0x0 to 0x1c. Within this table one word is allocated to each of the
various exception types.
This word will contain some form of ARM instruction that should perform a
branch. It does not contain an address.
Reset - executed on power on IRQ - normal interrupt
Undef - when an invalid instruction reaches the FIQ - fast interrupt
Execute stage of the pipeline
SWI - when a software interrupt instruction is
executed.
Prefetch - when an instruction is fetched from
memory that is invalid for some reason, if it
reaches the execute stage then this exception is
taken.
Data - if a load/store instruction tries to access an
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FIQIR
(Reserved)Data Abort
Prefetch AbortSoftware Interrupt
Undefined Instruction
Reset
Vector Table
ARM Processor September 2005
invalid memory location, then this exception is taken.
When one of these exceptions is taken, the ARM goes through a low-
overhead sequence of actions in order to invoke the appropriate exception
handler. The current instruction is always allowed to complete (except in case of
Reset).
IRQ is disabled on entry to all exceptions; FIQ is also disabled on entry to Reset
and FIQ.
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ARM Processor September 2005
System Design
Here is a very generic ARM based design that is actually fairly
representative of the designs that we see being done.
Figure – Example of an ARM based System
On-chip there will be an ARM core (obviously) together with a number
of system dependant peripherals. Also required will be some form of interrupt
controller which receives interrupts from the peripherals and raised the IRQ or
FIQ input to the ARM as appropriate. This interrupt controller may also provide
hardware assistance for prioritizing interrupts.
As far as memory is concerned there is likely to be some (cheap)
narrow off-chip ROM (or flash) used to boot the system from. There is also likely
to be some 16-bit wide RAM used to store most of the runtime data and perhaps
some code copied out of the flash. Then on-chip there may well be some 32-bit
memory used to store the interrupt handlers and perhaps stacks.
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16 bit RAM
8 bit ROM
32 bit RAM
ARMCore
Peripherals
InterruptController
nFIQnIRQ
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ARM Processor September 2005
Processor Types
ARM 1 (v1)
This was the very first ARM processor. Actually, when it was first
manufactured in April 1985, it was the very first commercial RISC processor.
Ever.As a testament to the design team, it was "working silicon" in it's first
incarnation, it exceeded it's design goals, and it used less than 25,000
transistors.
The ARM 1 was used in a few evaluation systems on the BBC
micro (Brazil - BBC interfaced ARM), and a PC machine (Springboard - PC
interfaced ARM).It is believed a large proportion of Arthur was developed on the
Brazil hardware. In essence, it is very similar to an ARM 2 - the differences being
that R8 and R9 are not banked in IRQ mode, there's no multiply instruction, no
LDR/STR with register-specified shifts, and no co-processor gubbins.
ARM evaluation system for BBC Master
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ARM 2 (v2)
Experience with the ARM 1 suggested improvements that could
be made. Such additions as the MUL and MLA instructions allowed for real-time
digital signal processing. Back then, it was to aid in generating sounds. Who
could have predicted exactly how suitable to DSP the ARM would be, some
fifteen years later?
In 1985, Acorn hit hard times which led to it being taken over by
Olivetti. It took two years from the arrival of the ARM to the launch of a computer
based upon it. When the first ARM-based machines rolled out, Acorn could gladly
announce to the world that they offered the fastest RISC processor around.
Indeed, the ARM processor kicked ass across the computing league tables, and
for a long time was right up there in the 'fastest processors' listings. But Acorn
faced numerous challenges. The computer market was in disarray, with some
people backing IBM's PC, some the Amiga, and all sorts of little itty-bitty things.
Then Acorn go and launch a machine offering Arthur (which was about as nice
as the first release of Windows) which had no user base, precious little software,
and not much third party support. But they succeeded. The ARM 2 processor
was the first to be used within the RISC OS platform, in the A305, A310, and
A4x0 range. It is an 8MHz processor that was used on all of the early machines,
including the A3000. The ARM 2 is clocked at 8MHz, which translates to
approximately four and a half million instructions per second (0.56 MIPS/MHz).
No current image
ARM 3 (v2as)
Launched in 1989, this processor built on the ARM 2 by offering
4K of cache memory and the SWP instruction. The desktop computers based
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upon it were launched in 1990.Internally, via the dedicated co-processor
interface; CP15 was 'created' to provide processor control and identification.
Several speeds of ARM 3 were produced. The A540 runs a
26MHz version, and the A4 laptop runs a 24MHz version. By far the most
common is the 25MHz version used in the A5000, though those with the 'alpha
variant' have a 33MHz version.
At 25MHz, with 12MHz memory (a la A5000), you can expect around
14 MIPS (0.56 MIPS/MHz).It is interesting to notice that the ARM3 doesn't
'perform' faster - both the ARM2 and the ARM3 average 0.56 MIPS/MHz. The
speed boost comes from the higher clock speed, and the cache.
And just to correct a common misunderstanding, the A4 is not a squashed down
version of the A5000. The A4 actually came first, and some of the design choices
were reflected in the later A5000 design.
ARM3 with FPU
ARM 250 (v2as)
The 'Electron' of ARM processors, this is basically a second level
revision of the ARM 3 design which removes the cache, and combines the
primary chipset (VIDC, IOC, and MEMC) into the one piece of silicon, making the
creation of a cheap'n'cheerful RISC OS computer a simple thing indeed. This
was clocked at 12MHz (the same as the main memory), and offers approximately
7 MIPS (0.58 MIPS/MHz).
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ARM Processor September 2005
This processor isn't as terrible as it might seem. That the A30x0 range
was built with the ARM250 was probably more a cost-cutting exercise than
intention. The ARM250 was designed for low power consumption and low cost,
both important factors in devices such as portables, PDAs, and organisers -
several of which were developed and, sadly, none of which actually made it to a
release.
No current image
ARM 250 mezzanine
This is not actually a processor. It is included here for historical
interest. It seems the machines that would use the ARM250 were ready before
the processor, so early releases of the machine contained a 'mezzanine' board
which held the ARM 2, IOC, MEMC, and VIDC.
ARM 4 and ARM 5
These processors do not exist.
More and more people began to be interested in the RISC
concept, as at the same sort of time common Intel (and clone) processors
showed a definite trend towards higher power consumption and greater need for
heat dissipation, neither of which are friendly to devices that are supposed to be
running off batteries. The ARM design was seen by several important players as
being the epitome of sleek, powerful RISC design. It was at this time a deal was
struck between Acorn, VLSI (long-time manufacturers of the ARM chipset), and
Apple. This lead to the death of the Acorn RISC Microprocessor, as Advanced
RISC Machines Ltd was born. This new company was committed to design and
support specifically for the processor, without the hassle and baggage of RISC
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OS (the main operating system for the processor and the desktop machines).
Both of those would be left to Acorn. In the change from being a part of Acorn to
being ARM Ltd in it's own right, the whole numbering scheme for the processors
was altered.
ARM 610 (v3)
This processor brought with it two important 'firsts'. The first 'first' was
full 32 bit addressing, and the second 'first' was the opening for a new generation
of ARM based hardware.
Acorn responded by making the RiscPC. In the past, critics were none-
too-keen on the idea of slot-in cards for things like processors and memory (as
used in the A540), and by this time many people were getting extremely annoyed
with the inherent memory limitations in the older hardware, the MEMC can only
address 4Mb of memory, and you can add more by daisy-chaining MEMCs - an
idea that not only sounds hairy, it is hairy!
The RiscPC brought back the slot-in processor with a vengeance.
Future 'better' processors were promised, and a second slot was provided for
alien processors such as the 80486 to be plugged in. As for memory, two SIMM
slots were provided, and the memory was expandable to 256Mb. This does not
sound much as modern PCs come with half that as standard. However you can
get a lot of mileage from a RiscPC fitted with a puny 16Mb of RAM. But, always,
we come back to the 32 bit. Because it has been with us and known about ever
since the first RiscPC rolled out, but few people noticed, or cared. Now as the
new generation of ARM processors drop the 26 bit 'emulation' modes, the RISC
OS users are faced with the option of getting ourselves sorted, or dying.
Ironically, the other mainstream operating systems for the RiscPC hardware -
namely ARMLinux and netbsd/arm32 are already fully 32 bit.
Several speeds were produced; 20MHz, 30Mhz, and the 33MHz part
used in the RiscPC. The ARM610 processor features an on-board MMU to
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ARM Processor September 2005
handle memory, a 4K cache, and it can even switch itseld from little-endian
operation to big-endian operation. The 33MHz version offers around 28MIPS
(0.84 MIPS/MHz)
.
The RiscPC ARM610 processor card
ARM 710 (v3)
As an enhancement of the ARM610, the ARM 710 offers an increased
cache size (8K rather than 4K), clock frequency increased to 40MHz, improved
write buffer and larger TLB in the MMU.
Additionally, it supports CMOS/TTL inputs, Fastbus, and 3.3V power
but these features are not used in the RiscPC.
Clocked at 40MHz, it offers about 36MIPS (0.9 MIPS/MHz); which
when combined with the additional clock speed, it runs an appreciable amount
faster than the ARM 610.
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ARM Processor September 2005
ARM710 side by side with an 80486, the coin is a British 10 pence coin.
ARM 7500
The ARM7500 is a RISC based single-chip computer with memory
and I/O control on-chip to minimise external components. The ARM7500 can
drive LCD panels/VDUs if required, and it features power management. The
video controller can output up to a 120MHz pixel rate, 32bit sound, and there are
four A/D convertors on-chip for connection of joysticks etc.
The processor core is basically an ARM710 with a smaller (4K) cache.
The video core is a VIDC2.The IO core is based upon the IOMD.
The memory/clock system is very flexible, designed for maximum uses
with minimum fuss. Setting up a system based upon the ARM7500 should be
fairly simple.
ARM 7500FE
A version of the ARM 7500 with hardware floating point support.
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ARM7500FE, as used in the Bush Internet box.
StrongARM / SA110 (v4)
The StrongARM took the RiscPC from around 40MHz to 200-
300MHz and showed a speed boost that was more than the hardware should
have been able to support. Still severely bottlednecked by the memory and I/O,
the StrongARM made the RiscPC fly. The processor was the first to feature
different instruction and data caches, and this caused quite a lot of self-modifying
code to fail including, amusingly, Acorn's own runtime compression system. But
on the whole, the incompatibilities were not more painful than an OS upgrade
(anybody remember the RISC OS 2 to RISC OS 3 upgrade, and all the programs
that used SYS OS_UpdateMEMC, 64, 64 for a speed boost froze the machine
solid!).
In instruction terms, the StrongARM can offer half-word loads and
stores, and signed half-word and byte loads and stores. Also provided are
instructions for multiplying two 32 bit values (signed or unsigned) and replying
with a 64 bit result. This is documented in the ARM assembler user guide as only
working in 32-bit mode, however experimentation will show you that they work in
26-bit mode as well.
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Later documentation confirms this. The cache has been split into
separate instruction and data cache (Harvard architecture), with both of these
caches being 16K, and the pipeline is now five stages instead of three.
In terms of performance... at 100MHz, it offers 11
A StrongARM mounted on a LART board.
In order to squeeze the maximum from a RiscPC, the Kinetic includes
fast RAM on the processor card itself, as well as a version of RISC OS that
installs itself on the card. Apparently it flies due to removing the memory
bottleneck, though this does cause 'issues' with DMA expansion cards.
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