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Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)
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Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Jan 04, 2016

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Page 1: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 1M

DIRECT MEMORY ACCESS MODULE

(DMA)

Page 2: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)
Page 3: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 3M

Module Objective

By the end of this module, you should be able to:

• Configure the DMA

• Service TIM, SPI and SCI interrupts via DMA

• Initiate DMA block data transfers

Module Exercise:

• Service TIM channel output compare via DMA

• Service SPI transmission complete via DMA

• Service SCI received data via DMA

• Initiate block data moves

Page 4: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 4M

DIRECT MEMORY ACCESS (DMA) MODULE

68HC08CPU

SystemIntegration

Module(SIM)

ClockGeneration

Module(CGM)

TimerInterfaceModule(TIM)

DirectMemoryAccessModule(DMA)

SerialCommunications

Interface(SCI)

Internal Bus (IBUS)

SerialPeripheralInterface

(SPI)

RandomAccess

Memory(RAM)

ElectronicallyProgrammable

Memory(EPROM)

LVI

COP

Monitor ROM

IRQ

BREAK

RESET

• Modular Architecture

• Service Request-Driven Operation Without CPU Intervention

• Three Independent Channels

• Byte or Word Transfer Capability

• Block Transfers and Loop Transfers

• CPU Interrupt Capability on Completion of Block Transfer or on Loop Restart

• Programmable DMA Bus Bandwidth (25%, 50%, 67%, or 100% of Total Bus Bandwidth)

• Programmable DMA Service Request/CPU Interrupt Request Priority

• Programmable DMA Enable during Wait Mode

• Block Transfers Up to 256 Bytes

• Expandable Architecture Up to Seven Channels and Eight Transfer Source Inputs

Page 5: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 5M

DMA Block Diagram

ALU

7 0

7

7

0

0

SYSTEMCONTROL

LOGIC

15

15

0

0

= BUS SWITCH

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 0

CHANNEL 1

CHANNEL 2

DESTINATION ADDRESSREGISTERS

SOURCE ADDRESSREGISTERS

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 0

CHANNEL 1

CHANNEL 2

BYTE COUNTREGISTERS

BLOCK LENGTHREGISTERS

CHANNEL CONTROLREGISTERS

INTERNAL BUS

TEM

PO

RA

RY

AD

DR

ES

S

TEM

PO

RA

RY

DAT

A

IN B

US

A

IN B

US

B

OU

T B

US

Page 6: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 6M

BUS Bandwidth & Interface

DMA uses same address/data lines as the CPU

• Small data transfers have little CPU impact

• Large data transfers will slow CPU activity– Control DMA/CPU bandwidth ratio– Select 25, 50, 67 or 100% DMA/CPU bus bandwidth

DMA interface

• Controls the R/W line, address bus and data bus

• CPU resumes control when DMA completes

• Bus cycles– requires 2 cycles to transfer an 8 bit byte– requires 4 cycles to transfer a 16 bit word

ADDRESS

CGMOUT

BUS

DATABUS

DMA (src) DMA (dest)

DMA (read) DMA (write)

CPU CPU

CPU CPU

Page 7: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 7M

Address Calculations

DMA arithmetic/logic unit (ALU) responsibilities:

• Calculates transfer source and destination addresses– May increment, decrement or remain static

• Increments byte count register

• Determines if transfer is complete– Stops transfer after a fixed number of bytes transfer– Begins transfer again ( looping )

Page 8: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 8M

Example Calculation 1

Source and destination address configured as increment

do

Repeat

Source Address = Source Base Address + Byte Count

Destination Address = Destination Base Address + Byte

Count

Add 1 to Byte Count

Until Byte Count = Block Length

Set transfer complete flag

If interrupt enabled, then generate interrupt request

Set Byte Count = 0

While Looping Enabled

Clear Channel Transfer Enable Bit

Page 9: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 9M

Example Calculation 2

Source address configured as decrement

Destination address configured as static

do

Repeat

Source Address = Source Base Address - Byte

Count

Destination Address = Destination Base Address

Add 1 to Byte Count

Until Byte Count = Block Length

Set transfer complete flag

If interrupt enabled then generate interrupt request

Set Byte Count = 0

While Looping Enabled

Clear Channel Transfer Enable Bit

Page 10: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 10M

DMA I/O Registers

Control and monitor registers

• DMA Control register (DC1)

• DMA Status and Control register (DSC)

• DMA Control register 2 (DC2)

Channel operation registers

• DMA channel Source address registers (DxSH:DxSL)

• DMA channel destination address registers (DxDH:DxDL)

• DMA channel control registers (D0C - D2C)

• DMA channel byte count registers (D0BC - D2BC)

• DMA channel block length registers (D0BL - D2BL)

Page 11: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 11M

DMA Control

DMA Control register 1 (DC1)

• Bus Bandwidth Control (BB1, BB0)– Controls the ratio of DMA/CPU bus activity

• Transfer enable (TECx)– Enables a channel to access address and data bus upon DMA triggering

1 = DMA channel x enabled0 = DMA channel x disabled

• CPU Interrupt enable (IECx)– Enables CPU interrupt upon transfer completion or restart of DMA transfer loop

1 = DMA channel x interrupts enabled0 = DMA channel x interrupts disabled

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ:

DC1 BB1 BB0 TEC2 IEC2 TEC1 IEC1 TEC0 IEC0

BB1:BB0 DMA Bus Cycles

00

01

10

11

CPU Bus Cycles

25% 75%

50%50%

0%

67% 33%

100%

Page 12: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 12M

DMA Status and Control Register

DMA Status and Control register 1 (DSC)

• Channel Status flags (IFCx)– Indicate DMA loop or transfer has completed– Generates a CPU interrupt ( if IECx is enabled )– Cleared by reading then writing logic 0 to flag bit

1 = DMA transfer complete0 = DMA transfer not complete

• DMA Loop enable bits (L2 -L0)– Enables looping back to the base addresses and repeating transfer again– Continues looping until disabled

1 = Loop mode enabled

0 = Loop mode disabled

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ:

DSC DMAP L2 L1 L0 DMAWE IFC2 IFC1 IFC0

Page 13: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 13M

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ:

DSC DMAP L2 L1 L0 DMAWE IFC2 IFC1 IFC0

DMA Status and Control register (DSC)

• DMA Priority (DMAP)– Controls the priority of DMA module interrupts

• DMA Wait Enable (DMAWE)– Enables DMA to operate while CPU in WAIT mode

1 = DMA enabled during WAIT instruction

0 = DMA suspended

DMAP = 0 DMAP = 1

Reset Reset

Software Interrupt (SWI) DMA Channel 0 Interrupt

External Interrupt DMA Channel 1 Interrupt

Timer Interrupt DMA Channel 2 Interrupt

SPI Interrupt Software Interrupt (SWI)

SCI Interrupt External Interrupt

DMA Channel 0 Interrupt Timer Interrupt

DMA Channel 1 Interrupt SPI Interrupt

DMA Channel 2 Interrupt SCI Interrupt

Highest Priority

Lowest Priority

DMA Status and Control Register

Page 14: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 14M

Interrupts

• DMAP = 1– Lower priority CPU interrupts recognized after current DMA transfer

completes– Block Transfers

• CPU Interrupt latency depends on size and bandwidth bits

• DMAP = 0– Higher priority CPU interrupts recognized after current byte is

transferred– Clears the transfer enable bit (TECx)

• Software must reenable the DMA channels

DMA Priority

Page 15: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 15M

Address Control, Transfer Data Size, & Source Selection

DMA Channel Control register 1 (D0C - D2C)• Source/Destination address control (SDC3 - SDC0)

– Control calculation of source/destination addresses– Assignments are implementation specific

RESET: INDETERMINATE AFTER RESETx = 0, 1 or 2

WRITE:

READ:

DxC SDC3 SDC2 SDC1 SDC0 BWC DTS2 DTS1 DTS0

SDC3:SDC2:SDC1:SDC0

1010

1001

1000

Source Address Destination Address

Increment Increment

0110

0101

0100

0010

0001

0000

Increment Decrement

Increment

Decrement

Decrement

Decrement

IncrementStatic

Static

Static

Static

Increment

Decrement

Static

Static

Decrement

Transfer Source

TIM Channel 0 Interrupt Request

TIM Channel 1Interrupt Request

TIM Channel 2 Interrupt Request

TIM Channel 3 Interrupt Request

SPI Transmit Interrupt Request

SPI Receive Interrupt Request

SCI Receive Interrupt Request

SCI Transmit Interrupt Request

DTS2:DTS1:DTS0

000

001

010

011

100

101

110

111•Byte/Word control (BWC)Selects 8-bit byte or 16-bit word transfers

–Source and/or Destination address must be static or BWC has no effect–Designed for 16 bit register transfer1 = 16-bit words0 = 8-bit bytes

• DMA Transfer source bits (DTS2 -DTS0)–Assigns the DMA channel to a source input

Page 16: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 16M

Source Address Registers

DMA Source Address Registers (D0SH/L - D2SH/L)

• Contains the source base address

• Used as base pointers during transfer calculations

WRITE:

READ:

DxSH AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8

RESET: INDETERMINATE AFTER RESET

WRITE:

READ:

DxSL AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

WRITE:

READ: DxDH AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8

RESET: INDETERMINATE AFTER RESET

WRITE:

READ:

DxDL AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

DMA Destination Address Registers (D0DH/L - D2DH/L)

• Contains the destination base address

• Used as base pointers during transfer calculations

Destination Address Registers

Page 17: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 17M

Block Length Registers

DMA Block Length registers (D0BL - D2BL)• Contains number of bytes to transfer• Compared to Byte Count register

– Determines if transfer is complete

RESET: INDETERMINATE AFTER RESET

WRITE:

READ:

DxBL BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0

Byte Count Registers

DMA Byte Count registers (D0BC - D2BC)• Contains the number of bytes transferred on that channel• Compared to Block Length register

– Determines if transfer is complete• Cleared when:

– Block Length = Byte Count– Write to the Channel source address register– Write to the Channel destination address register

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ:

DxBC BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0

Page 18: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 18M

DMA Setup

1) Write initial source address to source address register

2) Write initial destination address to destination address register

3) Select address manipulation for source/destination addresses, data size and

transfer source (DxC)

4) Enter number of bytes to transfer(DxBL)

5) Enable interrupts (if desired), select the bandwidth (DC1)

6) Enable the channel (DC1)

7) To force transfer: set SWIx (DC2)

• Note: Not necessary for normal DMA transfer

Page 19: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 19M

DMA ExercisePart 1

Write a code sequence to configure DMA channel 0 to service a TIM channel 0 interrupt. The

DMA will write a new output compare value from location $50 and $51 to TCH0H:TCH0L

register.

Part 2

Configure DMA channel 1 to service SPI transmission complete interrupt. The DMA will read

the SPI data register and store the data at location $52.

Part 3

Have DMA channel 2 service SCI data received interrupts. The DMA will read the SCI data

register and store the data at location $53.

Given:

TCH0 EQU $0027 ;Timer channel 0 register

SPDR EQU $0012 ;SPI data register

SCDR EQU $0018 ;SCI data register

Page 20: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 20M

Force Transfer

DMA Control register 2 (DC2)

• Initiates DMA transfers

• Simulates interrupts for test purposes

• Software initiated (SWI7 -SWI0)– Assignments are implementation specific– Initiates DMA request from DMA transfer source– Selected channel must be enabled for transfer to begin– Channel must have transfer source input (DTSx) assigned

1 = DMA software transfer initiated0 = DMA software transfer halted

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ:

DC2 SWI7 SWI6 SWI5 SWI4 SWI3 SWI2 SWI1 SWI0

Page 21: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 21M

Exercise

Part 4

Write a code sequence that configures DMA channel 0 to

initialize 176 bytes of RAM (the rest of page 0 RAM) to 0 starting at

address $50. This routine should signal the CPU when complete. Since

this is a large transfer, consider using 25 to 50% bus bandwidth.

Note: Set location $50 to zero first, then use this as the source location.

Page 22: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 22M

Low Power Modes

WAIT

• IF DMAWE is set:– DMA will complete transfers – Will execute transfers on all DMA interrupt requests– Can generate interrupt source that wakes CPU

• If DMAWE is clear:– Suspends DMA transfers, resumes after Wait terminates

STOP

• Suspends DMA transfer

• Upon STOP termination:– Reset aborts DMA transfer– External interrupt will resume DMA transfer

Page 23: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 23M

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ:

DC1 BB1 BB0 TEC2 IEC2 TEC1 IEC1 TEC0 IEC0

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ:

DSC DMAP L2 L1 L0 DMAWE IFC2 IFC1 IFC0

RESET: INDETERMINATE AFTER RESETx = 0, 1 or 2

WRITE:

READ:

DxC SDC3 SDC2 SDC1 SDC0 BWC DTS2 DTS1 DTS0

WRITE:

READ:

DxSH AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8

RESET: INDETERMINATE AFTER RESET

WRITE:

READ:

DxSL AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

DMA Register Summary

Page 24: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 24M

WRITE:

READ: DxDH AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8

RESET: INDETERMINATE AFTER RESET

WRITE:

READ:

DxDL AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

RESET: INDETERMINATE AFTER RESET

WRITE:

READ:

DxBL BL7 BL6 BL5 BL4 BL3 BL2 BL1 BL0

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ:

DxBC BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0

RESET: 0 0 0 0 0 0 0 0

WRITE:

READ:

DC2 SWI7 SWI6 SWI5 SWI4 SWI3 SWI2 SWI1 SWI0

DMA Register Summary Continued

Page 25: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 25M

Exercise Solution - part 1 -

; DMA exercise - all registers have been predefined with equates

; Part 1

ORG $0050

Data1 RMB 2

ORG $7000

CLR D0SH ; set up source address (high byte)

MOV #Data1, D0SL ; set up source address (low byte)

MOV #TCH0H, D0DH ; set up dest. address (high byte)

MOV #TCH0L, D0DL ; set up dest. address (low byte)

MOV #$08, D0C ; select TIM 0, word length

; static source and destination

MOV #$02, D0BL ; move 2 bytes

MOV #$00, DSC ; normal priority, Suspend during Wait

MOV #$02, DC1 ; 100% Bandwidth, Enable channel 0

; interrupt generation turned off

MOV #$02, DC1 ; enable channel 0

Page 26: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 26M

Exercise Solution- part 2 -

; DMA exercise - all registers have been predefined with equates

; Part 2

ORG $0052

Data2 RMB 1

CLR D1SH ; SPI is source address

MOV #SPDR, D1SL ;

CLR D1DH ; Data is the destination address

MOV #Data2, D1DL ;

MOV #$04, D1C ; Select SPI, byte length

; Static source and destination

MOV #$01, D1BL ; Move 1 byte

LDA DC1 ; Read current register value

ORA #$08

STA DC1 ; enable channel 1

Page 27: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 27M

Exercise Solution- part 3 -

; DMA exercise

; Part 3

ORG $0053

Data3 RMB 1

CLR D2SH ; set up source source address (low

byte)

CLR D2DH ; set up dest. address (high byte)

MOV #Data3, D2DL ; set up dest. address (low byte)

MOV #$06, D2C ; select SCI, byte length

; static source and destination

MOV #$01, D2BL ; move 1 byte

LDA DC1 ; Read current register value

ORA #$20

STA DC1 ; enable channel 2

Page 28: Direct Memory Access Module MTT48 10 - 1 M DIRECT MEMORY ACCESS MODULE (DMA)

Direct Memory Access Module MTT48 10 - 28M

; DMA exercise

; Part 4

Start EQU $50

ORG $7000

CLR Start

CLR D0SH

MOV #Start,D0SL ; Set up source address

CLR D0DH

MOV #Start,D0DL ; set up dest. address

MOV #$23,D0C ; select TIM 3 - unused, byte size

; static source and incr. destination

MOV #176,D0BL ; move 176 bytes

MOV #$00,DSC ; normal priority, Suspend during Wait

MOV #$43,DC1 ; 50% Bandwidth, Enable channel 0,

; enable interrupt

MOV #$08,DC2 ; Start block transfer by forcing interrupt

Exercise Solution- part 4 -