ARCHITECTURES FOR RF FREQUENCY SYNTHESIZERS

ARCHITECTURES FOR RF FREQUENCY SYNTHESIZERS

THE KLUWER INTERNATIONAL SERIES IN ENGINEERINGAND COMPUTER SCIENCE

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ARCHITECTURES FORRF FREQUENCYSYNTHESIZERS

by

Cicero S. VaucherPhilips Research Laboratories Eindhoven

with a Foreword by

Bram Nauta

KLUWER ACADEMIC PUBLISHERSNEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: 0-306-47955-9Print ISBN: 1-4020-7120-5

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Dordrecht

To Viviane

Foreword

The progress in the semiconductor industry has brought us advanced electronicsystems available for large groups of people. By putting more and more func-tionality on an integrated circuit (IC) these systems could become cheap inmass production. This is the reason why scientists and engineers put constanteffort in integrating more functions into ICs.

Many of these electronic systems need internal signals with a tunable, sta-ble and accurate frequency. An example of this is a radio-frequency receiver,where a signal with a stable frequency is used to tune to a radio-station of inter-est. In the past this frequency was generated with the help of bulky passive me-chanically tunable components. But if one wishes to integrate such a receiveron a chip, other components are needed to generate the tunable frequency. Inthis case, one needs to integrate a so-called frequency synthesizer, which relieson a clean fixed reference frequency, usually derived from a crystal, to create avariety of other frequencies.

A frequency synthesizer is usually realized with a phase-locked loop (PLL)which in turn can be implemented with on-chip components like transistors,resistors and capacitors. Such a synthesizer is far more complex than the old-days mechanically tuned resonators and can contain thousands of components.But still they are cheaper, more reliable, and easier in use: everybody wants a“digitally tunable” radio.

The application of synthesizers has gone through an enormous growth inthe past years. Today they are widely used in wireless telecommunication sys-tems like mobile phones but also in optical communication systems and cablemodems. PLL circuits are also widely used as clock generators for micropro-cessors. PLL frequency synthesizers, and in particular radio-frequency (RF)

viii Foreword

synthesizers, are therefore important components of modern electronic sys-tems.

A PLL frequency synthesizer may be cheap in mass production, but it iscertainly not a simple circuit to design. Phase-locked loops are non-linear sys-tems with very complex behaviour. Furthermore, PLLs are hard to simulatebecause time-constants are involved which may differ by many orders of mag-nitude. The output of a synthesizer has inaccuracies which are characterisedas jitter and phase noise. These effects are very difficult to understand and tosimulate. Finally, PLL design requires deep insight in system level design aswell as transistor level design. So it is no surprise that there is a large need fordesign know-how on frequency synthesizers.

This book deals with the design of RF frequency synthesizers. It containsbasic information for the beginner as well as in-depth knowledge for the experi-enced designer. Since frequency synthesizers are used in many different appli-cations, different performance aspects are important in every case. Sometimessettling-time is important, sometimes residual phase deviation is important andsometimes residual frequency deviation is important. In all cases the designmust be optimized in a completely different way. This book describes a con-ceptual framework for the different optimisations. It is, furthermore, widelyillustrated with practical design examples used in industrial products.

The book was originally the Ph.D. thesis of Cicero Vaucher, who wrote itafter 10 years of experience in RF frequency synthesizers at Philips ResearchLaboratories. I really enjoyed working with Cicero during the preparation ofhis thesis and now I feel very happy that it has been published as a book. Ci-cero has a natural talent in clear writing and therefore I believe this book isreally worth reading for a broad group of scientists and engineers.

BRAM NAUTA

Professor IC Design

University of Twente, The Netherlands

Preface

Frequency synthesizers are an essential building block of RF communicationproducts. Digital tuning has become commonplace in traditional market seg-ments, such as TVs and AM/FM radios, and is fundamental to the operationof personal cellular communication systems, in which the RF channels aredynamically allocated as the users move within the network, and the mobilehand-sets have to automatically and transparently re-tune to different RF car-rier frequencies.

The design of high-performance frequency synthesizers involves familiaritywith system optimization techniques and knowledge of state-of-the-art systemand building block architectures. Common technical requirements which needto be considered during the design phase include high spectral purity, fast set-tling time and low power dissipation. These are the main aspects treated in thisbook.

The main body of the text presents a theoretical analysis of different PLLproperties, followed by descriptions of innovative architectures, circuit imple-mentations and measurement results. The analysis of the PLL properties is per-formed with the use of the open-loop bandwidth and phase margin concepts,to enable the influence of higher-order poles to be taken into account from thebeginning of the design process. The common concepts of undamped natu-ral frequency and damping factor, originated in the analysis of second-ordersystems, are therefore not used in the text.

Chapters 1, 2 and 3 are of a tutorial nature. Chapters 1 and 2 review ba-sic communication techniques and the main specification points of frequencysynthesizers for tuning system applications. Chapter 3 focuses on single-looparchitectures, with a discussion of the properties of PLL building blocks on the

x Preface

system level and a review of single-loop architectures in which the minimumstep size is not equal to the reference frequency.

When organising this book I had the option to place the system-level anal-ysis of different performance aspects in different chapters, that is, separatedfrom more practical considerations such as the description of the applicationrequirements and the implementation of the building blocks. Instead, I havechosen to “frame” the theoretical analysis within a few chapters which alsodescribe the requirements of the intended applications. In this way, I hope thatthe reader will have a better understanding of the background and of the needfor the theoretical system analysis being presented. Chapter 4, for example, fo-cuses on tuning systems for phase-modulation communication systems, havingas a practical application an L-band tuner for digital satellite reception. Here,a crucial specification point is the residual phase deviation of the oscillatorsignal; as such, Chapter 4 includes an in-depth analysis of the residual phasedeviation of PLL frequency synthesizers.

Chapter 5 is the result of a frequency-modulation receiver project for car-radio applications, where the challenge was the combination of fast settlingtime with low residual frequency deviation. An analysis of the settling timeperformance as a function of the open-loop bandwidth and phase margin ispresented, followed by an analysis of the residual frequency deviation perfor-mance. This analysis led to the perception that the design procedure which op-timises the residual phase deviation performance, described in Chapter 4, mustbe avoided in frequency-modulation applications, as it always results in a sub-optimal residual frequency deviation performance. In other words, it is nec-essary to consider, during the optimization of the PLL frequency synthesizerparameters, whether it will be used in a phase-modulation or in a frequency-modulation communication system.

Chapter 6 focuses on programmable frequency dividers, having as practicalapplication a low-power paging receiver. Among others, a truly-modular andan adaptive-power architecture for low-power multi-band applications are pre-sented. Chapter 7 presents a summary of conclusions. Appendix A looks at thestability limits of PLLs using a PFD/CP combination, and Appendix B linksthe design of clock-conversion PLLs for optical networks to the wide-bandloop design techniques developed in Chapter 4.

The circuit design of VCOs and crystal oscillators is not treated in this work.However, extensive reference lists to literature on VCO design have been in-cluded at the end of Chapters 1 and 3.

Preface xi

Acknowledgements

Many persons contributed to the development of this book. I would especiallylike to thank Dieter Kasperkovitz for his support and motivation during the ex-ecution of the projects described in the text. Dieter is also acknowledged for hisvaluable inputs to the circuits and architectures presented in Chapters 4, 5 and6. I would also like to thank Prof. Bram Nauta for his continuous assistanceand constructive remarks during the preparation of the manuscript. The circuitsdescribed in the text were realised in close cooperation with many colleagues,mainly from Philips Semiconductors. In particular, I want to acknowledgethe following persons: Jon Stanley, Onno Kuijken, Philippe Gorisse, AlainVigne, Pascal Walbrou and Johan van der Tang for contributions to the workdescribed in Chapter 4. For contributions to Chapter 5, I would like to thankKave Kianush, Huub Vereijken, Bert Egelmeers, Jan Meeuwis and Gerrit vanWerven. I am also grateful to Zhenhua Wang and Gerrit van Veenendaal forcontributions to Chapter 6. Pieter Hooijmans is gratefully acknowledged forthe support provided for this work. Finally, I would like to thank everyone whoproposed improvements to earlier versions of the text.

CICERO S. VAUCHER

Eindhoven, The Netherlands

April 2002

Contents

Foreword

Preface

List of Acronyms

List of Symbols

Introduction1.1 Overview of the BookReferences

Tuning System SpecificationsTuning RangeMinimum Step SizeSettling TimeSpurious SignalsPhase Noise SidebandsPower DissipationIntegration LevelInterference Generation

References

3 Single-Loop ArchitecturesIntroductionInteger-N PLL ArchitecturePLL Building Blocks

3.13.23.3

vii

ix

xix

xxi

157

11111213141822242425

27272828

2.12.22.32.42.52.62.72.8

2

1

xiv Contents

3.3.13.3.23.3.33.3.4

Voltage-Controlled OscillatorsFrequency DividersPhase DetectorsThe Phase-Frequency Detector/Charge-Pump Combi-nationLoop Filter

Dimensioning of the PLL ParametersOpen- and Closed-loop Transfer FunctionsOpen-loop Bandwidth and Phase Margin

Spectral Purity PerformanceSpurious Reference BreakthroughPhase Noise Performance

Design of the Loop FilterSpurious Reference BreakthroughPhase Noise Contribution from the Loop Filter ResistorDimensioning of Time Constant and Capacitance

The Choice of the Reference FrequencySingle loop PLL with Divided Oscillator OutputFractional-N PLL Techniques

Phase Error CompensationModulation Techniques

Translation LoopsDirect Digital Frequency SynthesizersArchitectures Combining PLL and DDS SynthesizersSummary of Conclusions on Single-Loop Architectures

References

4 Wide-Band ArchitecturesIntroductionReceiver ArchitecturesResidual Phase Deviation

The Residual Phase Deviation PowerThe Open-Loop Bandwidth for Optimum Phase NoisePerformance

Minimum Approximated Residual Phase DeviationInfluence of the Phase Margin on the Residual PhaseDeviation

4.14.24.3

4.3.14.3.2

4.3.34.3.4

3.9.13.9.2

3.73.83.9

3.103.113.123.13

3.6.13.6.23.6.3

3.6

3.53.5.13.5.2

3.4.13.4.2

3.43.3.5

283031

33384242434949536263646670707577808587899091

999999

102102

104

107

109

Contents xv

The Influence of the Open-Loop Bandwidth on theResidual Phase DeviationThe Condition for the Implementation of the OptimumLoop Bandwidth

Single-Loop DesignSpecification of the PLL Building BlocksSingle-Loop ArchitecturesWide-Band Loop Design

Multi-Loop DesignPhase Noise PerformanceSpecification of the Different LoopsThe Limiting Values for the Reference Frequency

Satellite Tuning SystemDouble-loop Tuning System ArchitecturePhase Noise Performance

Dividers in Bipolar TechnologyArchitectureLogic Implementation of the Divider CellsCircuit ImplementationPower Dissipation Optimization and Sensitivity Mea-surements

VHF PFD/CP ArchitecturesArchitectureCircuit ImplementationMeasurement Results

ConclusionsReferences

5 Adaptive PLL ArchitectureIntroductionRDS Car-Radio ApplicationMulti-Band Tuner ArchitectureSettling Time

Settling BehaviourOpen-Loop Bandwidth, Phase Margin and SettlingTime Specifications

Settling Time Requirements5.5

5.4.15.4.2

5.15.25.35.4

164167

157157157158160160

4.9

4.8.14.8.24.8.3

4.8

4.7.14.7.24.7.34.7.4

4.7

4.6.14.6.2

4.6

4.5.14.5.24.5.3

4.5

4.4.14.4.24.4.3

4.4

4.3.6

4.3.5113

115116117120122125125128130132133135137137138139

141145145148149153153

xvi Contents

5.6 Residual Frequency DeviationIntroductionBasic Concepts

Simplified Treatment of the Residual Frequency Devi-ation of a PLLNumerical Results with Analytic Transfer Functions .Conclusions

Terrestrial FM BroadcastingReference Spurious Signals and Loop Filter AttenuationLimitations of Existing PLL Architectures

Adaptive PLL ArchitectureBasic ArchitectureLoop Filter ImplementationDead-Zone Implementation

Circuit ImplementationProgrammable DividersOscillatorsCharge-Pumps

Measurements

ConclusionsReferences

6 Programmable DividersIntroductionDivider Architectures

Architecture Based on a Dual-Modulus PrescalerPresettable Programmable CountersBasic Programmable PrescalerAdaptive Power Prescaler Architecture for Multi-BandApplications

Prescaler with Extended ProgrammabilityDividers in CMOS Technology

Logic Implementation of the Divider Cells

Circuit Implementation of the Divider CellsPower Dissipation OptimizationInput Amplifier

6.36.3.1

6.3.26.3.36.3.4

6.2.5

6.2.16.2.26.2.36.2.4

6.16.2

207

209210

212

213214216

167167168

170174178180182183

183184185187191191192192193196

198

201201202203205205

5.12

5.13

5.11.15.11.25.11.3

5.11

5.10.15.10.25.10.3

5.75.8

5.95.10

5.6.45.6.5

5.6.15.6.25.6.3

Contents xvii

6.3.5

6.3.66.4

Input Sensitivity Measurements and Maximum Oper-ation FrequenciesPhase Noise Measurements

ConclusionsReferences

7 Conclusions

A PLL Stability Limits Due to the Discrete-Time PFD/CP Operation 237237240

Stability LimitsA.1References

B Clock-Conversion PLLs for Optical TransmittersReferences

About the Author

Index

217222225225

229

241243

245

247

List of Acronyms

Analog-to-Digital ConverterAutomatic Frequency ControlAmplitude ModulationBit Error RateCharge-PumpDigital-to-Analog ConverterdB with respect to the CarrierDirect Digital SynthesizerD-type Flip-flopDegreeDouble SidebandElectromagnetic CompatibilityExclusive-ORFrequency ModulationFrequency Setting WordGaussian Frequency Shift KeyingGaussian Minimum Shift KeyingIntermediate FrequencyJouleKelvinLocal OscillatorLow-Pass FilterMulti-Stage Noise Shaping ModulatorPersonal ComputerPhase-Frequency DetectorPhase-Locked Loop

ADCAFCAMBERCPDACdBcDDSD-FFdgDSBEMCEXORFMFSWGFSKGMSKIFJKLOLPFMASHPCPFDPLL

xx List of Acronyms

PMQPSKRDSRFrmsROMS-HSNRSSBVCOVHFVLSI

Phase ModulationQuadrature Phase Shift KeyingRadio Data SystemRadio FrequencyRoot-Mean-SquareRead Only MemorySample-and-HoldSignal-to-Noise RatioSingle SidebandVoltage-Controlled OscillatorVery High FrequencyVery Large Scale Integration

List of Symbols

Symbol Meaning Page

79151616

3940752844

281248828

58

13103

30

Output of a digital accumulatorAmplitude of the carrier signal (V)Amplitude of a spurious signal (V)Relative amplitude of a spurious signal with respectto the carrier (dBc)Ratio of the time constants of the loop filterCapacitances of the loop filter (F)Fractional (decimal) part of division ratioOutput frequency of a PLL (Hz)Open-loop bandwidth, 0 dB cross-over frequency

Output frequency of a VCO whenMinimum value of the open-loop bandwidth (Hz)Clock frequency of a DDS synthesizer (Hz)Frequency of the signal at the output of a frequencydivider (Hz)Reference frequency at which the equivalent phasenoise floor is specified (Hz)Maximum frequency error with respect to (Hz)Higher offset frequency for integration of noisepower density (Hz)Input frequency to a frequency divider or PFD/CP

(Hz)

(Hz)

b

F

xxii List of Symbols

Output frequency of the tuning system (Hz) 4Lower offset frequency for integration of noisepower density (Hz)Target frequency after a frequency step (Hz)Fourier frequency (offset, modulation or basebandfrequency) (Hz)Frequency of maximum phase advance of the open-loop transfer function (Hz)Minimum step size of the tuning system (Hz)Offset frequency at which the free-running VCOphase noise power density is specified (Hz)Operation frequency of the PFD (Hz)Maximum PFD operation frequency at which fre-quency discrimination can be realized (Hz)Minimum value of the reference frequency in awide-band loop (Hz)Symbol rate in a digital communication system (Hz)Mixing frequency in a translation loop (Hz)Operation frequency before a frequency step (Hz)Magnitude of a frequency step (Hz)Frequency of crystal oscillator (Hz)Phase noise cross-over frequency (Hz)Open-loop transfer function of a PLLClosed-loop transfer function of a PLLLow-pass transfer function (de-emphasis network)Amplitude of the output current of a charge pump(A)Leakage current in the tuning line of the VCO (A)Instantaneous output current of a charge pump (A)An integerrms current noise density originated in the chargepumpBinary input to a digital accumulatorGain of PFD/CP combination (A/rad)VCO gain factor (Hz/V)Gain factor which depends on the configuration ofthe loop filter

103

13

45

12

28

131

15

104

36

1038613

16228106434316933

5034

54

75352839

G(s)H(s)

i

K

k

List of Symbols xxiii

Boltzmann constant;SSB phase noise power density in a 1 Hz band-width to total signal power, at offset frequency(dBc/Hz)SSB equivalent synthesizer phase noise floor at theinput of the phase detector (dBc/Hz)SSB phase noise power density due to quantizationnoise from aSSB free-running phase noise power density of theVCO (dBc/Hz)An integerUpper limit to the sum of the noise specification ofthe building blocks (dB)Integer denoting frequency divisionNumber of bits, word-width of a digital accumulator

loopnoise

maxspurious

Mm

N

Maximum (specified) magnitude of spurious signals(dBc)Main divider division ratio, integerMaximum value of N which leads to compliance to

An integerEffective length of a programmable divider chainProportionality factorOrder of aBinary numberReference divider division ratio, integerResistor used in the loop filterRatio of the limiting values of the residual frequencydeviationLaplace transform complex variableAbsolute temperature (K)High-pass transfer functionPeriod of the input signal to a frequency divider (s)Period of the output signal of a frequency divider (s)Period of the input signal to the PFD,Time (s)Locking time after a frequency step (s)

5920

58

83

109

118

717563

28123

20979811382840173

6460206206

13

T

modulator (dBc/Hz)

modulator

n

R

l

p

t

xxiv List of Symbols

Magnitude of the ripple voltage due to mismatch inthe CP current sources (V)Magnitude of the ripple voltage at the VCO tuningline (V)Voltage at the tuning input of a VCO (V)rms voltage noise density originated in the loop filter

Transimpedance of the loop filterA positive number, expresses the dependency of theequivalent phase noise floor on the reference fre-quency

filter elementsRelative magnitude of the phase noise due to loop

Excess noise factorRemaining frequency error with respect to finalvalue (Hz)Peak frequency deviation (Hz)Residual frequency deviation powerVCO free-running frequency deviation powerExpresses the influence of the phase margin on loop-noise (dB)Reset time of the D-FFs when the loop is phase-locked (s)Phase difference at the input of a phase frequencydetector (rad)Maximum phase difference that can be detected be-fore PFD/CP switches polarity of the output pulses(rad)Duty-cycle of the output pulse of a charge-pumpFrequency deviation power spectral density

Free-running VCO frequency deviation power den-sityEffective damping coefficientExcess phase of a sinusoidal signal (rad)Phase of the output signal of a frequency divider(rad)

1530

164

174

16938

37

35

36

169172120

51

109162

64

3958

2854

51

53

x

List of Symbols xxv

Phase error at the input of PFD/CP (rad) 7830Phase of the input signal to a frequency divider (rad)

Maximum value of during a settling transient(rad)

166

1535

Peak phase deviation of phase modulation (rad)Phase of the output signal of the reference divider(rad)rms phase deviation associated with a pair of PM 17spurious signals (rad)rms phase deviation due to several pairs of PM spu-rious signals (rad)

17

rms phase deviation associated with a single spuri-ous signal (rad)

18

Active time of the charge pump output signal (s)Time constants of the loop filter (s)Time constant determined from spectral purity con-siderations (s)

383968

187109108

103105125

116

116

Single-sided magnitude of the dead-zone (s)Minimum residual phase deviation powerMinimum approximated residual phase deviationpowerResidual phase deviation powerApproximated residual phase deviation powerResidual phase deviation power of a multi-loop tun-ing systemSpecification for the maximum residual phase devi-ation of the LO (rad rms)Specification for the residual phase deviation due tostochastic phase noise sources (rad rms)

116Specification for the residual phase deviation due tospurious signals (rad rms)Residual phase deviation specification for a wide-band loop (rad rms)Residual phase deviation power transferred to theoutput of a multi-loop tuning systemrms phase noise power density of main divider

122

125

54

xxvi List of Symbols

Phase noise power density at the output of a fre-quency divider

71

Equivalent synthesizer phase noise floor at the inputof the phase detector

55

Open-loop phase noise power density generated bythe loop filter elements

60

Phase margin (radians in equations, degrees in fig-ures)

44

Maximum phase advance of function (rad)Phase noise power density of the PLL output signal

4554

“Low-pass” phase noise power component of 55

“High-pass” phase noise power component of

rms phase noise power density of phase frequencydetector

60

54

rms phase noise power density of reference divider 54

rms phase noise power density of free-running VCO 54

rms phase noise power density of crystal oscillator 54

Ratio of and the effective noise bandwidthPhase of the open-loop transfer function(rad)

17345

DSB peak phase noise power density 20Angular frequency (rad/s)Open-loop bandwidth (rad/s)Frequency of maximum phase advance of the open-loop transfer function (rad/s)

4445