Analysis of the relationship between the kink effect and the indium levels in MOS transistors

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Materials Science and Engineering B 178 (2013) 1458– 1463

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Short communication

Analysis of the relationship between the kink effect and the indiumlevels in MOS transistors

N. Hizema,∗, A. Fargia, A. Kalboussia, A. Souifib

a University of Monastir, Laboratory of Microelectronics and Instrumentation, Monastir 5019, Tunisiab Institute of Nanotechnology of Lyon, 7 Avenue, Jean, Capelle, 69621 Villeurbanne Cedex, France

a r t i c l e i n f o

Article history:Received 1 April 2013Received in revised form 28 August 2013Accepted 7 September 2013Available online 21 September 2013

Keywords:Low frequency dispersionAdmittance spectroscopyElectrical characterizationMOSFETIndium deep trapsKink effect

a b s t r a c t

In this work, we investigate the effects of indium ion implantation on the channel of nMOSFETs. Deeplevel transient spectroscopy (DLTS) and admittance spectroscopy (AS) measurements have been madeon a series of indium doped silicon N+P structures and MOS capacitors. To analyse the indium-relatedlevels in nMOSFETs, we used a low frequency (LF) output conductance dispersion analysis, which is basedon the Gain-Phase versus frequency at different temperatures. These experiences show that the indiumlevel when operated at low temperatures at which the majority of carriers freeze-out exhibit a kink effect.The effects of indium doping on the kink were studied using the variation of channel conductance gd andtransconductance gm versus temperature in the kink zone. The excess drain current versus drain and gatevoltage show the maximums of both conductance gd and transconductance gm at around T = 124 K whenthe indium level is activated.

© 2013 Published by Elsevier B.V.

1. Introduction

As MOS devices scaled down to 0.1 �m regime, the control ofshort channel effects (SCE) becomes more challenging. The sus-ceptibility of boron to transient enhanced diffusion (TED) furtherenhances the dopant density near the surface, resulting in highthreshold voltage and low carrier mobility. This becomes increas-ingly difficult to achieve good device performance and, at the sametime, maintain a decent control of the short-channel effects usingboron channel implantation. To overcome the imminent difficul-ties, the super steep retrograde channel (SSRC) has been proposedas a viable scheme for devices with gate length of 0.1 �m or less[1–3]. A heavy-ion implantation is employed to form a localisedhigh-doping region at a controlled distance away from the Si–SiO2interface in the SSRC. In this way, a low doping concentration canbe maintained near the surface region, allowing an optimum drivecurrent to be achieved without compromising the short-channelbehaviour [4]. For deep sub-micron devices, conventional dopantscan therefore no longer be used and dopants like In for NMOS andAs or Sb for PMOS have been proposed [5]. Owing to its muchlower diffusivity and his ability to form a narrow as-implanted SSRCcompared to boron, indium has been proposed [6]. The success ofindium channel implantation is evidenced by its incorporation into

∗ Corresponding author. Tel.: +216 98205838.E-mail address: neila [email protected] (N. Hizem).

many mainstream CMOS technologies [4–10]. Reduction in SCE hasbeen observed with improved VT roll-off and reduced drain inducedbarrier lowering (DIBL), when using Indium as heavy dopant [5,7,8].However, in addition to its low solubility in silicon that leads to theformation of precipitates, its mass becomes a defect when it willhave to be electronically active. Otherwise indium has the tendencyto exhibit interstitial deactivation and carrier freeze-out even atroom temperature [7,8].

The goal of this work is to characterise MOS transistors(L = 100 �m) to determine how an incomplete ionisation of indiumaffects I(V) characteristics. In the second paragraph we will carryout frequency spectra on the conductance of the channel in orderto determine the apparent depth of the shallow levels of Indium intransistors and to find the parameters of tension that have influ-ence on these apparent levels which show electronic activation ofIndium. N+P structures and MOS capacitors are studied to com-pare the activation energy levels determined by DLTS and AS andthe trap states of nMOSFETs after low frequency output conduc-tance dispersion analysis. Kink effect observed in experimental C(V)and I(V) characteristics of nMOS capacitors and transistors is alsodiscussed.

2. Devices fabrication

N+ polysilicon gate MOS capacitors and nMOSFETs withL × W = 100 �m × 100 �m for nMOSFET and 200 �m × 200 �m forMOS capacitors, were made as shown in Fig. 1. We note that because

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Fig. 1. Structure of MOS devices investigated in this study (a) and the related band structure showing indium and boron levels in silicon (b).

of low values of capacitance we could not make capacitance mea-surements with short MOSFET that is why we used long channel. AP well about 5 × 1017 cm−3 indium implanted was performed in a Psubstrate at 0.1 �m under the interface. Boron was added to adjustthe substrate doping to about 1017 cm−3. The gate oxide thicknessof the nMOSFET device is 3.2 nm. To test the MOS devices, we usedN+P well diodes fabricated with 5 × 1016 cm−3 for both In and Bdopants. The setup used for the electrical characterisations (I(V),C(V), G(V), AS and DLTS) is shown in Fig. 2.

3. Experimental results and discussion

3.1. Deep level transient spectroscopy measurements

As expected, the DLTS cannot be made on MOSFETs becauseof its low gate capacitance. To skirt this problem, measurementsas shown in Fig. 3 were performed on N+P samples in 40–300 Ktemperature range and made by lock-in amplifier technique (A-B) for different emission rates. The signature of the indium traplevel shows activation energy of 0.18 eV, capture cross section of7 × 10−13 cm−2 and trap density of 3 × 1015 cm−3. The indium levelinvestigated in our study presents a strong field effect such as itsactivation energy varies from 0.15 eV to 0.2 eV. This is in good accor-dance with the literature [14].

HP 4284A

C-V

HP 4156A

I-V

HP 4194A

G-V

Device

Under Test

Vaccum

Pump

Cryostat

Computer and

GPIB Controller

Temperature

Controller 77K-

350K

Fig. 2. Setup diagram of the electrical measurements, using HP 4156A for I-V, HP4284A, for C, G-V and DLTS, and HP 4194A for admittance spectroscopy.

3.2. Admittance spectroscopy measurements

The conductance frequency versus the temperature G/ω (T) hasbeen investigated on N+P diodes at different temperatures. Underdirect polarisation, Fig. 4 shows the presence of a level located at0.13 eV, and another one at 0.3 eV. At zero volt we observe onlythe 0.13 eV level, that seems to be the same indium hole trapdetected around 0.16 eV according to DLTS results. C(V) curvesfor MOS capacitors at 300 K between −3 V and +2 V are identi-cal for high (1 MHz) and low (500 Hz) frequency. This allows usto think that there is no significant trap state in the polysilicongate near the oxide. Furthermore when the temperature decreases(T < 200 K), we observe an anomalous phenomena [7,8] near theflat band part (−0.9 V) of the C(V) curve (Fig. 5). This behaviourdisappears when measurements are performed at higher temper-ature (T > 300 K). Bouillon et al. called these phenomena the kinkeffect [7,8]. In Fig. 6, the important peak of G(V) at −0.9 V confirmsthe presence of the kink effect. This peak is amplified at low tem-perature but disappears at high temperature. To understand thisbehaviour, we studied the evolution of the conductance versus tem-perature at −0.9 V, by varying the frequency between 131 KHz and1 MHz, only one peak is observed (Fig. 7), with activation energyvalue of 0.16 eV (Fig. 8), this level is attributed to In level [13–15].The incomplete ionisation of indium is certainly responsible for thekink at −0.9 eV. Indeed Bouillon et al. [7,8], have demonstrated thatthe kink is sensitive to In concentration and does not exist for boroncounterparts. Moreover, performing calculations with and withoutincomplete ionisation, they have shown that the carrier freeze out

300250200150100500

-0,8

-0,6

-0,4

-0,2

0,0

DLT

S s

ignal (

a.u

)

Temperature ( K )

20 Hz

50 Hz

100 Hz

200 Hz

Fig. 3. DLTS signal of N+P junction for reverse bias Vr = −4 V and pulse bias Vp = 0 V,with different emission rates.

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Fig. 4. The conductance frequency G/� as a function of temperature at 0 V of N+P,diode with frequencies varying from 190 KHz to 1 MHz. The peak at low temperatureis, significant of a hole trap present in the structure.

Fig. 5. An anomalous behaviour with different temperatures at −0.9 V in the capac-itance, versus gate polarisations of MOS capacitor.

Fig. 6. An important peak observed at low temperature in the conductance versusgate, polarisations of MOS capacitor at −0.9 V.

Fig. 7. The conductance versus temperature at −0.9 V of CMOS structure shows aunique, large band with activation energy of 0.16 eV.

is responsible for an intrinsic reduction in the threshold voltage,which contributes to a saturation in VTh with indium implantationdose [7,8].

3.3. MOSFETs characterisation

3.3.1. Electrical characterisation of MOSFETsThe electrical characterisation of n channel MOS transistors

for different temperatures gives us the main results as shown inFig. 9. We notice a sharp increase in the drain—source currentwhen Vds = Vkink at low temperatures (T ≤ 250 K). This unusual vari-ation of the drain current well known as the kink effect (differentfrom C(V) kink effect) induces an increase of the drain/source out-put conductance (gds) and a decrease of the amplification factor.We also observe that when the gate voltage increases, the amountof drain current and kink voltage increases too. As the tempera-ture decreases, the excess of drain current increases especially atT = 124 K. Many studies consider the impact ionisation that occurs inthe InGaAs channel as responsible for the kink effect [11]. But otherworks confirm that due to the different temperatures behaviourof Ids (Vds) characteristics it seems impossible to correlate theobserved kink effect to only the impact ionisation phenomenon[12].

Fig. 8. The Arrhenius plots of traps detected in both N+P and CMOS structures afterDLTS, and admittance spectroscopy.

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Fig. 9. ID (VD) characteristics of nMOSFETs showing the kink effect for different gate, voltages and temperatures: (a) T = 86 K, (b) T = 124 K, (c) T = 173 K and (d) T = 230 K.

3.3.2. Frequency dispersion of the drain–source conductanceThe frequency dispersion of the drain–source conductance is

a more reliable tool for deep level analysis in MOSFETs. It is animportant parasitic effect which has a negative influence on thetransistor performance. This effect is induced by the presenceof the deep traps that modify the space charge region. At lowfrequencies the traps can follow the excitation signal, so the drain-source conductance gds has a value close to the d.c. one, while athigh frequencies the traps cannot follow the signal, and a variationof gds is observed [12].

A set of two devices were used in this work; the transistors werebiased in the saturation zone for Vds < Vkink, where In is supposedto be inactive. The amplitude of the modulation was typically50 mV. The experimental setup allows us to obtain simultaneouslythe variation of the drain–source conductance and the phasebetween the excitation and the output signals as a function ofthe frequency (Fig. 10). The peak maxima for the phase-shift areconsidered as transition frequencies and their variations withtemperature allow us to obtain an Arrhenius plot which gives thedeep level parameters. The activation energies are investigatedby low frequency output conductance dispersion techniques andare summarised in Table 1. We establish that particularly for thelevels around 107 meV and 180 meV do not appear at the samepolarisation. In order to get a better understanding of the relationbetween 107 and 180 meV, we report in Fig. 11, the results of fixedVgs = 1.5 V, and different drain–source tension Vds. The activationenergies values of 167 meV; 142 meV; 121 meV and 104 meV,respectively extracted from the Arrhenius plot show an electric

Fig. 10. The variation of the phase between the excitation and the output signals asa, function of frequency shows the shift of the peak with the temperature.

Table 1Activation energy levels detected with different techniques.

Techniques DLTS AS LF dispersion

Activation energy levels

180 meV 130–160 meV 90–170 meV0.2–03 eV 0.3 eV 0.2 eV0.4 eV – –– – 15–20 meV– – 65–70 meV

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Fig. 11. The activation energies values extracted from the Arrhenius plot forVds = 1.2 V, 1.3 V, 1.4 V and 1.5 V at Vgs = 1.5 V showing an electric field effect.

Fig. 12. The dependence of the apparent activation energy of In level and the draintension.

field effect. These levels are probably the apparent levels of theIndium level located at 160 meV. Fig. 12 shows the dependenceof the apparent activation energy and the drain tension (Vds). Wenote that if Vds varies about 0.3 V the indium energy decreasesabout 40% and as a result the ionisation is much higher.

4. Discussion

The activation energies of traps were investigated in differentstructures using DLTS, AS, and low frequency techniques. The DLTSand AS measurements allow us to detect and localise only thetraps situated under the gate in the structure, while the gds fre-quency dispersion measurements are sensitive especially to trapssituated near the drain. The activation energies obtained from thesemethods are summarised in Table 1. These results are comparable.The main level located at 0.16 eV present in all the structures anddetected by the different techniques is attributed to substitutionalIn. We have shown that this level is submitted to an electric fieldeffect [8,13–15].

The kink effect has been examined using the variation of channelconductance gd and transconductance gm versus temperature inthe kink zone. The analysis of the excess drain current versus drainand gate voltage at different temperatures in the kink zone, showsthe maximums of both conductance gd and transconductance gm

at around T = 124 K when the indium level is activated. This leadsto the hypothesis that there is a correlation between deep level

of indium situated at 0.16 eV and the observed kink effect in I(V)characteristics.

As it is well known [16,17], the appearance of excess drain cur-rent in the saturation region of MOSFET/SOI (the so-called kinkeffect) arises from the threshold voltage shift due to the for-ward biasing of the source-substrate diode caused by substrateimpact ionisation current flowing from the drain to the source. Inpractice, a similar situation occurs in bulk silicon MOSFETs oper-ating at very low temperature [18] or when disconnecting thesubstrate electrode at room temperature [19]. The impact of ion-isation is directly related to the avalanche phenomenon. Indeedby increasing the voltage Vds beyond the pinch-off voltage, thedrain field becomes strong enough to ionise atoms in the chan-nel area space charge in the drain side. These highly energeticelectrons are able to extract other electron–hole pairs. Thereforethe electrons are created and contributing to a strong conductionchannel. The holes are attracted towards the gate, but others areattracted to the substrate thus causing a gate-substrate currentresulting in an increase of the drain current too [20–22]. This ionisa-tion can also attack the traps in the substrate, where a generationof recombination will induce an additional current. However fortemperatures below room temperature the bonding of the sub-strate is insufficient to cancel the kink effect. This leads us tosuggest, that in addition to the substrate effect, the increased cur-rent is the result of trapping and detrapping by a deep level centre[11,23].

We believe that the relationship between the kink and thedeep traps arises when decreasing the gate length. Indeed, thisdecrease was such that the channel zone is not rectangular, andone cannot overlook the drain channel interface from under thegate length. The trap in drain lateral side (to the interface SCR/drain)will undergo both the gate along x direction (channel depth) and thedrain along the two axes x and y (the channel is more rectangular).Part of the voltage Vds will then be superimposed inversely to thegate. By applying a positive Vgs, the hole trap will capture the elec-trons since the Fermi level rises. By applying a low voltage Vds, allthe voltage appears along the y-axis direction to drain the electronsfrom the source to drain. Gradually, as the voltage Vds increases,the component along x direction Vds also increases until a criticalvoltage (called Vkink) sufficiently lowers the Fermi level again andcauses the trap to eject the trapped electrons pinch in the area. Thechannel is reconstituted, and becomes conducting. The current islinear with almost the same slope and saturates again.

5. Conclusion

Deep levels in PN junctions and MOS capacitors samples weredirectly examined by means of the DLTS and AS techniques. Fur-thermore, low frequency output conductance was used for deeplevel analysis in MOSFETs. We have found that all these techniqueshave been useful for deep level characterisation and they can beused in a complementary manner.

Ids–Vds measurements were also performed on the n channelMOSFET transistors; they have shown the presence of kink effectin the structure. For MOS transistors, it has been shown that Indiumdefect situated at 0.16 eV could be correlated to kink effect. On theother hand the maximums of both conductance gd and transcon-ductance gm at around T = 124 K confirms our hypothesis about thecorrelation of deep levels with the observed kink effect in all Ids–Vdscharacteristics.

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