ANALOG INTEGRATED CIRCUITS DESIGN - College of · PDF file · 2011-06-17Analog Integrated Circuits University of Massachusetts Amherst ANALOG INTEGRATED CIRCUITS DESIGN University

Analog Integrated Circuits

University of Massachusetts Amherst

ANALOG INTEGRATED

CIRCUITS DESIGN

University of Massachusetts

Electrical and Computer Engineering Department

Omid Oliaei

ECE697BB/Oliaei 2

• Real-world signals are Analog.

• Signals generated by sensors are analog

• Digital signal processing of signals requires Analog-to-Digital Conversion.

• Analog signal needs to be amplified and filtered before A/D.

• Amplifiers and Filters are Analog Circuits.

• A/D is a Mixed-Signal Circuit.

Why Analog?

Chapter 1



ECE697BB/Oliaei 3

• Digital signals in a digital communication system behave as analog signals

at certain stages of transmission, receive and processing.

Ex 1. Lossy Cable Ex 2. Disc Drive

• Signal Attenuation, Noise and Distortion incurred in the propagation

channel require that the received signal be Amplified, Filtered and

Equalized using Analog circuits.

Ex 3. Wireless Receiver Ex 3. Optical Receiver

Chapter 1

ECE697BB/Oliaei 4

•Why Integrated?

• Larger integration � larger complexity

• Lower parasitics � Higher speed

• Lower cost

• Moore’s Law: Number of transistors doubles every 18 months:

• 1960: 25 µm Gate length• Today: 90 nm and 65 nm in production

• 45 nm and 32 nm are in lab. 22nm and 16nm on roadmap.

•Why CMOS?

• Digital (Main Driver)

• Low Power, Simplicity, Scaling, Low cost

• Analog

• Integration with digital

• Improved speed over years

Chapter 1



ECE697BB/Oliaei 5Chapter 1

Analog

Design

Performance

Constra

ints

Schem

atic

Test

Layout

System Level

Circuit Level

Component Level

Levels of Abstraction

What is Analog Design?Don’t Forget

Variations

ECE697BB/Oliaei 6

CAD TOOLS FOR CIRCUIT DESIGN

• Two Dominant Suppliers:

• Cadence 80% market share

• Mentor Graphics 20% market share

• Simulation:

• System Level: Matlab, SPW

• High-Level (Behavioral): Verilog, Verilog_A, Verilog AMS

• Low-Level (Electrical): SPICE, SPECTRE, ADS, Proprietary Tools

• Cadence and Mentor Graphics Include tools for

• Schematic Capture

• Simulation

• Layout

Chapter 1



ECE697BB/Oliaei 7

Schematic Capture

Netlist

Electrical/Behavioral Simulations

Layout: Automatic/Manual

Technology

Device Model

Parasitic Extraction

Design Rules Check (DRC)

Layout Versus Schematic (LVS)

Masks

Fabrication

Design House FoundryCustomer

Specifications

TestProduction

Chapter 1

ECE697BB/Oliaei 8

Analog Design Space

Tradeoffs

• Analog Design is a Multi-Dimensional Optimization Problem.

• Improving one parameter always results in degradation of some others.

Cost ?

Chapter 1




Basic MOS Device Physics

• Understanding Device Physics is Essential to Analog Design.

• MOS device is symmetric.

NMOS

Bulk

Side Diffusion

(Sio2) Contact

(Metal)

Ddrawneff LLL 2−=5 nm0.25 µµµµm

2.2 nm0.13 µµµµm

3.5 nm0.18 µµµµm

ToxLdrawn

ECE697BB/Oliaei 10

• MOS is a four-terminal device.

• Substrate (bulk) of an NMOS is connected to the lowest potential.

• Substrate (bulk) of a PMOS is connected to the highest potential.

• All p-n junctions are reverse biased.

• Conduction takes place beneath gate, between source and drain.

NMOS

PMOS

Chapter 2



ECE697BB/Oliaei 11

Complementary MOS Process (CMOS):

PMOSNMOS

Chapter 2

PMOS

ECE697BB/Oliaei 12

MOS CHANNEL FORMATION

Cut Off

Depletion

Inversion

VG

GND

VG

GND

VG

GNDGND

VTH

Chapter 2



ECE697BB/Oliaei 13

• Device turn-on is a gradual phenomenon.

• There exists several definitions for VTH.

• One definition: when VG=VTH :

density of electrons on the interfaced equals density of holes in the substrate

• VTH increases with increasing the substrate doping.

Adjusting VTH by ion implantation:

• P+ layer increases VTH

Chapter 2

ECE697BB/Oliaei 14

PMOS IN INVERSION STATE

• PMOS: Holes flow from Source to Drain.

• NMOS: Electrons flow from Source to Drain.

• Electrons have a higher Mobility. � NMOS is faster than PMOS (~ 3 times).

Chapter 2

S D



ECE697BB/Oliaei 15

MOS Symbols

Chapter 2

Arrow indicates current flow from positive voltage to negative voltage polarity.

ECE697BB/Oliaei 16

NMOS

I-V CHARACTERISTICS

Uniform Charge

Distribution

• Larger VDS � Larger Longitudinal Field

• Larger VGS � More Charge Carriers

Chapter 2

More Current



ECE697BB/Oliaei 17

I/V Characteristics (cont.)

vxVVVWCI THGSoxD )]([ −−−=

∫∫==

−−=VDS

V

THGSnox

L

x

D dVxVVVWCdxI00

)]([µ

Given v = µE and E(x) = −dV (x)

dx

dx

xdVxVVVWCI nTHGSoxD

)()]([ µ−−=

ID = µnCoxW

L[(VGS − VTH)VDS −

1

2VDS

2]

ECE697BB/Oliaei 18

I-V CHARACTERISTICS: Triode Region

Triode Region:

THGSDS VVV −<

ID = µnCoxW


1

2VDS

2]

Almost Linear

nµ Electrons Mobility

ox

siox

tC

ε= Oxide Capacitance

W Device Width

L Device Length

35.0=siε

DSTHGSL

WoxnD VVVCI )( −≈ µ

Oxide Permittivity

oxt Oxide Thickness

sV

cm

.

2

[ ]mµ

[ ]mµChapter 2

[ ]cmpF /

[ ]2/ cmpF



ECE697BB/Oliaei 19

THGSDS VVV −>

I-V CHARACTERISTICS: Saturation Region

2)(2

THGSoxn

D VVL

WCI −

′=

µ

V'DS = VGS − VTH (Pinch − off )

LL ≈′Chapter 2

ECE697BB/Oliaei 20

MOS OPERATION REGIMES

Both PMOS and NMOS:

THGSDS VVV −< Triode Region

THGSDS VVV −= Pinch-Off

THGSDS VVV −> Saturation Region

• In saturation, MOS behaves as a current source.

Chapter 2



ECE697BB/Oliaei 21

constant VDSGS

Dm

V

Ig

∂∂

=

= µnCoxW

L(VGS − VTH)

gm = 2µnCoxW

LID

=2ID

VGS − VTH

Transconductance in Saturation Region

2)(2

THGSoxn

D VVL

WCI −=

µ

Chapter 2

ECE697BB/Oliaei 22

ID = µnCoxW


1

2VDS

2]

ID = µnCoxW

L(VGS − VTH)VDS, VDS << 2(VGS − VTH)

)(

1

THGSL

WoxnDS

DSON

VVCI

VR

−=

∂∂

=µ

DRAIN-SOURCE RESISTANCE IN TRIODE REGION

Chapter 2

Voltage-Controlled Resistance



ECE697BB/Oliaei 23

THRESHOLD VOLTAGE AND BODY EFFECT

( ) 220 FSBFTHTH VVV Φ−+Φ+= γ

VB < 0 attracts holes and widens depletion region

� Larger VG > 0 to put opposite charge on gate

� Larger VG > 0 to create inversion

� Higher VTH

4.03.0 << γ Body effect coefficient

FΦ Fermi level

Source-Bulk voltage

Chapter 2

ECE697BB/Oliaei 24

CHANNEL LENGTH MODULATION: SATURATION REGION

L' = L − ∆L

)1(1

)/1(1

'/1 DSVL

LLL

L λ+=∆+=

)1()(2

2DSTHGS

oxnD VVV

L

WCI λ

µ+−=

L L’

DSTHGSoxn

DS

DS IVVL

WC

V

Ig

DSλ

µλ ≈−=

∂∂

= 2)(

2

Chapter 2

L

1∝λ,

L

Ig DS

DS∝



ECE697BB/Oliaei 25

ECE697BB/Oliaei 26

=

T

GSD

V

VII

ζexp0

SUBTHRESHOLD CONDUCTION

• For VGS<VTH, there exists a weak inversion layer causing a small diffusion current.

• This “leakage” current causes increased power dissipation in digital circuits.

• To operate in weak inversion, transistor must be wide � low speed.

• Application: Ultra Low-Power design.

Chapter 2



ECE697BB/Oliaei 27

MOS LAYOUT

Gate

(Poly)Contacts

(Metal)

Gate

Shared

Chapter 2

Gate Contact

ECE697BB/Oliaei 28

PARASITIC CAPACITANCES

Overlap

Bottom-plate

cap

Side-wall

cap

• Junction capacitance increases non-linearly with reverse bias.

Chapter 2



ECE697BB/Oliaei 29

GAT-SOURCE AND GATE DRAIN CAPCITANCES

• Cgs is maximum in the saturation region

•

• Device is symmetric in the triode region

Chapter 2

)]([ xVVVWCQ THGSoxch −−∝

oxGS WLCC3

2≈

oxGDGS WLCCC2

1≈=

ECE697BB/Oliaei 30

LOW-FREQUENCY MOS SMALL-SIGNAL MODEL

D

o

Ir

λ1

=

SBF

mBS

D

mbV

gV

Ig

+Φ==

22

γ∂∂

0=SBV 0≠SBV

: Drain-source resistance

: Bulk transconductance

saturation

Chapter 2



ECE697BB/Oliaei 31

HIGH-FREQUENCY SMALL-SIGNAL MODEL

Chapter 2

Saturation

Triode Cut Off

ECE697BB/Oliaei 32



ECE697BB/Oliaei 33

ECE697BB/Oliaei 34

GATE ACCESS RESISTANCE

Two fingers

Reduce resistance

Chapter 2

• Gate resistance effect is significant at RF.



ECE697BB/Oliaei 35

COMMON-SOURCE with RESISTIVE LOAD

Av = −gmRD

Deep triode

Saturation

Sat.

Triode

Off

Chapter 3

ECE697BB/Oliaei 36

omv rgA −=

Av = −gm ro || RD

∞→DR

Chapter 3

COMMON-SOURCE with RESISTIVE LOAD: Model



ECE697BB/Oliaei 37

DIODE-CONNECTED MOS

(gm + gmb)Vx +Vx

ro

= Ix

Vx

Ix

=1

gm + gmb

|| ro ≈1

gm + gmb

Chapter 3

ECE697BB/Oliaei 38

COMMON-SOURCE STAGE with DIODE-CONNECTED LOAD

Av = −gm1 1

gm2 + gmb2

= −gm1

gm2

1

1 +η

Av = −(W / L)1

(W / L)2

1

1 + η

Av = −un (W / L)1

up (W / L)2

• Gain independent of bias current

• Good gain accuracy: good matching

• Gain independent of bias current

• Gain set by two different types of transistor

PMOS Diode-Connected Load

Chapter 3



ECE697BB/Oliaei 39

COMMON-SOURCE with CURRENT SOURCE LOAD

Av = −gm ro1 || ro2

• Large Output Voltage Compared with Resistive Load

• All Transistors Need to be in Saturation for High Gain

• M1 sets the Minimum Output Voltage

• M2 Sets the Maximum Output Voltage

Saturation

Triode

Av = −gmRON2

RON 2 =1

µnCoxW

L

2

(VDD − Vb − | VTHP |)

Chapter 3

High-Resistance Node

ECE697BB/Oliaei 40

COMMON-SOURCE WITH SOURCE DEGENERATIONS

Av = −GmRD

Av =−gm RD

1+ gm RS

Gm =gm

1 + gmRS

Gm =gmro

RS + [1+ (gm + gmb )RS ]ro

Av = −GmRD || ROUT

Including Second-Order Effects

Chapter 3



ECE697BB/Oliaei 41

COMMON-SOURCE OUTPUT RESISTANCE

ROUT = [1 + (gm + gmb )ro ]RS + ro

ROUT = ro' ≈ ro [1+ (gm + gmb )RS ]

Av = −GmRD || ro'

Av =−gm RD

1+ gm RS

= −RD

1/ gm + RS

Simplified Model

Chapter 3

ECE697BB/Oliaei 42

SOURCE FOLLOWER

mbmmbm

outgggg

R+

==11

||1

Av =gmRS

1+ (gm + gmb )RS

=RS

1/ gm + (gm + gmb

gm

)RS

≈RS

1/ gm + RS

Small-Signal Model

Output Resistance

• Source Follower Exhibits a high input resistance

and a low output resistance.

Chapter 3



ECE697BB/Oliaei 43

SOURCE FOLLOWER WITH FIXED BIAS CURRENT

• Id1, thus, Vgs1- Vth1, are independent of Vin.

Av =

1

gmb

|| ro1 || ro2 || RL

1

gmb

|| ro1 || ro2 || RL +1

gm

Load Effect on Gain

Application: Buffering a High-Gain Stage

Chapter 3

ECE697BB/Oliaei 44

COMMON-GATE

Rout ={[1 + (gm + gmb )ro]RS + ro}|| RD

AC couplingDC coupling

DmbmD

DSSombmo

ombmv RggR

RRRrggr

rggA )(

)(

1)(+≈

++++++

=

Small-Signal Model

Gain

Output Resistance

Input Resistance

Rin = ro ||1

gm

||1

gmb

Chapter 3



ECE697BB/Oliaei 45

CASCODE AMPLIFIER

Dmbmoo

Dooombm

Rggrr

RrrrggRout

||)]([

||}])(1{[

2221

21222

+≈

+++=

AV ≈ gm1{[ro1ro2 (gm 2 + gmb2 )] || RD ]}

AV ≈ gm1[(ro1ro2 gm2 ) || (ro3ro4gm3 )]Shielding Effect of Cascode

Chapter 3

ECE697BB/Oliaei 46

DIFFERENTIAL VERSUS SINGLE-ENDED

Single-Ended Source Differential Sources

Advantage: Reduced Sensitivity to Supply Noise

Supply Noise

Clock Noise



ECE697BB/Oliaei 47

PSEUDO-DIFFERENTIAL AMPLIFIER

Disadvantage: Sensitive to Input Common-Mode Voltage

Chapter 4

ECE697BB/Oliaei 48

DIFFERENTIAL AMPLIFIER

Tail current: Rejects input common mode

Dm

inin

outoutdiff Rg

VV

VVA =

−−

=21

21Differential-Mode Gain

0=cACommon-Mode Gain

2

2

/

4

/

4

2in

oxn

SS

in

oxn

SS

oxn

in

Dm

VLWC

I

VLWC

I

L

WC

V

IG

−

−=

∆∆

=

µ

µµ∂∂

Chapter 4



ECE697BB/Oliaei 49

SMALL-SIGNAL ANALYSIS

Dmd RgA −=

Differential-Mode

SSm

Dc

Rg

RA

+−=

)2/(1

2/

Common-Mode

Virtual ground

Chapter 4

ECE697BB/Oliaei 50

COMMON-MODE RESPONSE

SSm

Dm

CMin

YX

Rg

Rg

V

VV

21, +=

−

Load Resistor Mismatch

Transistor Mismatch

( )1)( 21

21

, ++−

−=−

SSmm

Dmm

CMin

YX

Rgg

Rgg

V

VV

Chapter 4



ECE697BB/Oliaei 51

DIFF. AMP WITH ACTIVE LOAD

mP

mNoPoNmPmNd

g

grrggA −≈−= − )||||( 1

)||( oPoNmNd rrgA −=

)](||)[( 7551331 oomoommd rrgrrggA ≈

Chapter 4


CURRENT MIRRORS

2

12

2 )(2

THDDoxn

OUT VVRR

R

L

WCI −

+≈

µ

Reference Current

Sensitive to VDD , Vth , W, L



ECE697BB/Oliaei 53

CURRENT-BIASED DIFFERENTIAL AMPLIFIER

Chapter 5

ECE697BB/Oliaei 54

CASCODE CURRENT MIRROR

Low-Voltage Cascode

Chapter 5



ECE697BB/Oliaei 55

DIFFERENTIAL AMPLIFIER WITH

ACTIVE CURRENT MIRROR

Large-Signal Operation

Chapter 5

ECE697BB/Oliaei 56

ID1 = ID3 = ID 4 = gm1,2Vin / 2 ID2 = −gm1,2Vin / 2

Iout = ID2 − ID4 = −gm1,2Vin ,⇒ Gm = gm1, 2

DIFFERENTIAL AMPLIFIER WITH ACTIVE LOAD

Small-Signal Analysis

Av ≈ GmRout

Rout ≈ ro2 || ro4 , (2ro1,2 >> [1/ gm3] || ro3 )

Chapter 5



ECE697BB/Oliaei 57

COMMON-MODE ANALYSIS

4,3

2,1

2,121

1

m

m

SSm

CMg

g

RgA

+−

≈

xF VV =

)21)(||( 2,14,32,14,3 SSmoom

CM

DM RgrrgA

ACMRR +==

Common-Mode Gain

Common-Mode Rejection Ratio

Chapter 5

ECE697BB/Oliaei 58

FREQUENCY RESPONSE OF AMPLIFIERS

vi vo

pi

o

sRCSsCR

sC

sV

sV

ω/1

1

1

1

/1

/1

)(

)(

+=

+=

+= RCp πω 2/1=

Single-Pole Passive RC

ωωω

jRCV

V

i

o

+=1

1

)(

)(

: pole frequency

( )22

1

1

)(

)(

ωωω

RCV

V

i

o

+=ωjs =

Z1 =Z

(1− Av)Z2 =

Z

(1− A−1

v )

Miller’s Theorem

X

Yv

V

VA =

vA

Chapter 6



ECE697BB/Oliaei 59

AMPLIFIER FREQUENCY RESPONSE ANALYSIS

C1 = CF(1− Av) C2 = CF(1− A−1

v ) ≈ CF

Capacitance Multiplication

Association of Poles and Nodes

ωωω pNinsin

out

CRCR

A

CR

A

sV

sV

21

21

1

1

11)(

)(

+++=

Chapter 6

ECE697BB/Oliaei 60

COMMON-SOURCE FREQUENCY RESPONSE

[ ] 1()1()(

)(

)

2 ++++++++−

=DBGDDGSSGDDmSDBGDSBGSGDGSDS

DmGD

i

o

CCRCRCRgRsCCCCCCRRs

RgsC

V

V

f p,in =1

2πRS CGS + (1+ gmRD )CGD[ ]

f p,out =1

2π CGD + CDB( )RD[ ]Exact Analysis

GD

mz

C

g+=ω

Chapter 6

Approximate Analysis (Miller)



ECE697BB/Oliaei 61

SOURCE FOLLOWER OR COMMON DRAIN

vo

vi=

gm + sCGS

s2RS (CGSCL + CGSCGD + CGDCL)+ s gmRSCGD + CGD + CGS( )+ gm

f p1 ≈gm

2π gmRSCGD + CL + CGS( ) , assuming f p2 >> f p1

=1

2π RSCGD +CL + CGS

gm

Chapter 6

ECE697BB/Oliaei 62

SOURCE FOLLOWER INPUT IMPEDANCE

At low frequencies, gmb >>| sCL |

Zin ≈1

sCGS

1+ gm / gmb( )+1/ gmb

∴ Cin = CGSgmb /(gm + gmb ) + CGD (same as Miller)

LmbGS

m

GS

insCgsC

g

sCZ

+

++≈

11

1

At high frequencies, gmb << | sCL |

Zin ≈1

sCGS

+1

sCL

+gm

s2CGSCL

Chapter 6



ECE697BB/Oliaei 63

SOURCE FOLLOWER OUTPUT IMPEDANCE

ZOUT =VX / IX

=sRSCGS +1

gm + sCGS

≈1/gm , at low frequencies

≈ RS , at high frequencies

( )mS

m

GSmSm gR

g

CLgRRgR /1,/1,/1 12 −=−==

Output ringing due to CL and inductive

component of output impedance.

Chapter 6

ECE697BB/Oliaei 64

CASCODE STAGE

f pA =1

2πRS CGS1 + CGD1 1+gm1

gm 2 + gmb 2

f pX =gm 2 + gmb 2

2π CGD1 + CDB1 + CSB 2 + CGS2( )

f pY =1

2πRD CDB 2 + CL + CGD 2( )

Chapter 6



ECE697BB/Oliaei 65

DIFFERENTIAL PAIR

f p1 ≈1

2π (roN || roP )CL

f p2 =gmP

2πCE

fZ = 2 f p 2 =2gmP

2πCE

Chapter 6

ECE697BB/Oliaei 66

FEEDBACK PRINCIPLES

Y(s) = H (s)[X(s) − G(s)Y (s)]

Y(s)

X(s)=

H (s)

1+ G(s)H (s)

βββ

ββ1

1

1

1≈

+⋅=

+==

A

A

A

A

X

YACL

• Gain Desensitization

2

211

1

1

R

RR

A

AACL

+=

+⋅=

β

ββ

β

• Example

1

21R

RACL +≈

Chapter 8



ECE697BB/Oliaei 67

FEEDBACK EFFECT ON BANDWIDTH

+=

p

cl

ff

j

AA

1

0

( )

+++

=

)1(11

1

00

0

ββ

ββ

Aff

jA

AA

p

CL

Chapter 8

ECE697BB/Oliaei 68

FEEDBACK EFFECT ON OUTPUT IMPEDANCE

IX =VX −VM

Rout

=VX − (−βA0VX )

Rout

VX

IX

= Rout,CL =Rout

1+ βA0

VX

IX

= Rin ,CL = Rin(1+ βA0)

• Input Impedance

• Output Impedance

Chapter 8



ECE697BB/Oliaei 69

AMPLIFIER TYPES

Chapter 8

ECE697BB/Oliaei 70

OP-AMP

-+

-+ -+

Differential Output

Single-Ended Output

∞→vAIdeal Op-Amp

∞→inR

0=outR

Chapter 9



ECE697BB/Oliaei 71

SINGLE-STAGE OP-AMP

• OP-AMP as a voltage buffer

Chapter 9

ECE697BB/Oliaei 72

CASCODE OP-AMP: SINGLE-STAGE

+ Higher Gain

- Reduced Output Swing

- Output swing dependent on input swing

Telescopic Cascode

Chapter 9



ECE697BB/Oliaei 73

IMPROVED SINGLE-ENDED CASCODE OP-AMP

Chapter 9

Low-Voltage Cascode Current Mirror

ECE697BB/Oliaei 74

TRIPLE CASCODE

• Av app. (gmro)3/2

• Severely Limited Output Swing

• Complex biasing

Chapter 9



ECE697BB/Oliaei 75

FOLDED-CASCODE AMPLIFIER

PMOS Input

NMOS Input

+ High Gain

+ Output Swing Decoupled from Input Swing

- Reduced Speed

Chapter 9

ECE697BB/Oliaei 76

FOLDED-CASCODE OP-AMP

13331 ])[(|| oombmmv rrgggA44 344 21

+≈

Cascode Gain

Chapter 9



ECE697BB/Oliaei 77

| Av |≈ gm1{[(gm 3 + gmb3)ro3 (ro1 || ro5 )] || [(gm 7 + gmb 7)ro7ro9 ]}

FOLDED-CASCODE OP-AMP

Chapter 9

ECE697BB/Oliaei 78

TELESCOPIC VERSUS FOLDED CASCODE

Non-dominant Pole

Non-dominant Pole

Chapter 9



ECE697BB/Oliaei 79

FOLDED-CASCODE OP-AMP IMPLEMENTATION

Current-Mirror

Current-MirrorDevices in Signal Path

Current-Mirror

signal

Chapter 9

ECE697BB/Oliaei 80

SINGLE-ENDED TWO-STAGE OP-AMPS

+ Large Voltage Swing

- Reduced Speed

Single-Ended Output Two-Stage Op Amp

Chapter 9

Active Current Mirror



ECE697BB/Oliaei 81

FULLY-DIFFERENTIAL TWO-STAGE OP-AMPS

+ Larger Voltage Swing

+ Better Noise Performance

Chapter 9

Ex.1 Ex.2

ECE697BB/Oliaei 82

OUTPUT IMPEDANCE ENHANCEMENT USING FEEDBACK

Rout = A1gm 2ro2ro1

Disadvantage: Low swing or Large Supply Voltage

Regulated Cascode

Chapter 9



ECE697BB/Oliaei 83

DIFFERENTIAL GAIN BOOSTING

Low-SupplyHigh-Supply

Chapter 9

ECE697BB/Oliaei 84

OP-AMP USING DIFFERENTIAL GAIN BOOSTING

Enhanced Telescopic Cascode

Chapter 9

Enhanced Folded Cascode



ECE697BB/Oliaei 85

COMPARISON

Chapter 9

Performance Comparison of OP-AMP Topologies

ECE697BB/Oliaei 86

COMMON-MODE FEEDBACK

Chapter 9

Low-Gain Amplifier

-+ -+

High-Gain Amplifier

• Output common-mode voltage in a low-gain diff-pair is well-defined.

• Output common-mode voltage in a low-gain diff-pair is ill-defined.



ECE697BB/Oliaei 87

COMMON-MODE FEEDBACK PRINCIPLE

Auxiliary amplifier sets the output common-mode.

CMref

oo VVVV

==+

2

21refCM VV =

ECE697BB/Oliaei 88

COMMON-MODE SENSING METHODS

Resistive Buffered-Resistive



ECE697BB/Oliaei 89

FOLDED-CASCODE WITH COMMON-MODE CONTROL

(a)

(b)

ECE697BB/Oliaei 90

SIMPLIFIED CMFB

• M7 and M8 in Triode.

• Advantages:

• Simple, low power

• Disadvantages:

• Low Accuracy

• Reduced Output Swing due to M7 and M8

• Increased Output Parasitic Capacitance

• CMFB with improved output swing:



ECE697BB/Oliaei 91

IMPROVED CMFB

CMref VV =

Through Symmetry:Complete Implementation

ECE697BB/Oliaei 92

TRANSIENT LARGE-SIGNAL: SLEWING

Slew rate:

( )L

SSout

C

I

dt

tdVSR ==



ECE697BB/Oliaei 93

SLEWING IN TELESCOPIC OP-AMP

( )L

SSout

C

I

dt

tdVSR

2==

Fully-Differential:

ECE697BB/Oliaei 94

FOLDED-CASCODE SLEWING

( )L

SSout

C

I

dt

tdVSR

2==

Fully-Differential:

ANALOG INTEGRATED CIRCUITS DESIGN - College of · PDF file · 2011-06-17Analog Integrated Circuits University of Massachusetts Amherst ANALOG INTEGRATED CIRCUITS DESIGN University

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