Analog electronics feucht - analog circuit design

Designing Amplifi er Circuits

D. FeuchtInnovatia Laboratories

Raleigh, NC.

Analog Circuit Design Series Volume 1

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Published by SciTech Publishing, Inc.911 Paverstone Drive, Suite BRaleigh, NC 27615(919) 847-2434, fax (919) 847-2568scitechpublishing.com

Copyright © 2010 by Dennis Feucht. All rights reserved.

No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Sections 107 or 108 of the 1976 United Stated Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 646-8600, or on the web at copyright.com. Requests to the Publisher for permission should be addressed to the Publisher, SciTech Publishing, Inc., 911 Paverstone Drive, Suite B, Raleigh, NC 27615, (919) 847-2434, fax (919) 847-2568, or email [email protected].

The publisher and the author make no representations or warranties with respect to the accuracy or completeness of the contents of this work and specifi cally disclaim all warranties, including without limitation warranties of fi tness for a particular purpose.

Editor: Dudley R. KayProduction Manager: Robert LawlessTypesetting: SNP Best-set Typesetter Ltd., Hong KongCover Design: Aaron LawhonPrinter: Docusource

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Printed in the United States of America

10 9 8 7 6 5 4 3 2 1

ISBN: 9781891121869Series ISBN: 9781891121876

Library of Congress Cataloging-in-Publication DataFeucht, Dennis. Designing amplifi er circuits / D. Feucht. p. cm. -- (Analog circuit design series ; v. 1) ISBN 978-1-891121-86-9 (pbk. : alk. paper) -- ISBN 978-1-891121-87-6 (series) 1. Amplifi ers (Electronics)--Design and construction. 2. Electronic circuit design. I. Title. TK7871.2.F477 2010 621.3815′35--dc22 2009028288

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Contents

Chapter 1 Electronic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Electronic Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Product Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Design-Driven Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Nonlinear Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 2 Amplifi er Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Bipolar Junction Transistor T Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9The b Transform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Two-Port Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Amplifi er Confi gurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13The Transresistance Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Input and Output Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18The Cascade Amplifi er. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27BJT Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30The Cascode Amplifi er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32The Effect of Base-Emitter Shunt Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . 38The Darlington Amplifi er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43The Differential (Emitter-Coupled) Amplifi er. . . . . . . . . . . . . . . . . . . . . . . . . . 47Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Matched Transistor Buffers and Complementary Combinations . . . . . . . . . . . 68Closure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Chapter 3 Amplifi er Concepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73The Reduction Theorem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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m Transform of BJT and FET T Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Common-Gate Amplifi er with ro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Common-Source Amplifi er with ro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Common-Drain Amplifi er with ro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83FET Cascode Amplifi er with ro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Common-Base Amplifi er with ro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85CC and CE Amplifi ers with ro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Loaded Dividers, Source Shifting, and the Substitution Theorem . . . . . . . . . 92Closure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Chapter 4 Feedback Amplifi ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Feedback Circuits Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Port Resistances with Dependent Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98General Feedback Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Input Network Summing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Choosing xE, xf, and the Input Network Topology. . . . . . . . . . . . . . . . . . . . . . 103Two-Port Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Two-Port Loading Theorem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Feedback Analysis Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Noninverting Op-Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Inverting Op-Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Inverting BJT Amplifi er Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Noninverting Feedback Amplifi er Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 124A Noninverting Feedback Amplifi er with Output Block . . . . . . . . . . . . . . . . 134FET Buffer Amplifi er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Feedback Effects on Input and Output Resistance . . . . . . . . . . . . . . . . . . . . . 140Miller’s Theorem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143Noise Rejection by Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145Reduction of Nonlinearity with Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147Closure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Chapter 5 Multiple-Path Feedback Amplifi ers . . . . . . . . . . . . . . . . . . . . . . .149Multipath Feedback Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149Common-Base Amplifi er Feedback Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 151Common-Emitter Amplifi er Feedback Analysis . . . . . . . . . . . . . . . . . . . . . . . . 159

vi Contents

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Common-Collector Amplifi er Feedback Analysis . . . . . . . . . . . . . . . . . . . . . . 166Inverting Op-Amp with Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 168Feedback Analysis of the Shunt-Feedback Amplifi er. . . . . . . . . . . . . . . . . . . . 171Shunt-Feedback Amplifi er Substitution Theorem Analysis. . . . . . . . . . . . . . . 178Idealized Shunt-Feedback Amplifi er. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182Cascode and Differential Shunt-Feedback Amplifi ers. . . . . . . . . . . . . . . . . . . 186Blackman’s Resistance Formula. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190The Asymptotic Gain Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196Emitter-Coupled Feedback Amplifi er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198Emitter-Coupled Feedback Amplifi er Example . . . . . . . . . . . . . . . . . . . . . . . . 200Audiotape Playback Amplifi er Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204Closure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Contents vii

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Preface

Solid-state electronics has been a familiar technology for almost a half century, yet some circuit ideas, like the transresistance method of fi nding amplifi er gain or identifying resonances above an amplifi er’s bandwidth that cause spurious oscillations, are so simple and intuitively appealing that it is a wonder they are not better understood in the industry. I was blessed to have encountered them in my earlier days at Tektronix but have not found them in engineering text-books. My motivation in writing this book, which began in the late 1980s and saw its fi rst publication in the form of a single volume published by Academic Press in 1990, has been to reduce the concepts of analog electronics as I know them to their simplest, most obvious form, which can be easily remembered and applied, even quantitatively, with minimal effort.

The behavior of most circuits is determined most easily by computer simula-tion. What circuit simulators do not provide is knowledge of what to compute. The creative aspect of circuit design and analysis must be performed by the circuit designer, and this aspect of design is emphasized here. Two kinds of reasoning seem to be most closely related to creative circuit intuition:

1. Geometric reasoning: A kind of visual or graphic reasoning that applies to the topology (component interconnection) of circuit diagrams and to graphs such as reactance plots.

2. Causal reasoning: The kind of reasoning that most appeals to our sense of understanding of mechanisms and sequences of events. When we can trace a chain of causes for circuit behavior, we feel we understand how the circuit works.

These two kinds of reasoning combine when we try to understand a circuit by causally thinking our way through the circuit diagram. These insights, obtained

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x Preface

by inspection, lie at the root of the quest. The sought result is the ability to write down accurate circuit equations by inspection. Circuits can often be analyzed multiple ways. The emphasis of this book is on development of an intuition into how circuits work with a perspective that can be applied more generally to cir-cuits of the same class.

In this fi rst volume of the Analog Circuit Design series, basic transistor ampli-fi er circuits are given a design-oriented analysis, using the simple but effective T model of the bipolar junction transistor (BJT) and fi eld-effect transistor (FET). It is delightful to be able to write down from inspection rather involved gain and port impedances that, when evaluated, give accuracies comparable to SPICE simulations. Designing Amplifi er Circuits remains focused on quasistatic (low-frequency ac) analysis and leaves the additional complication of reactance and dynamic analysis for succeeding volumes.

Consequently, feedback analysis – a topic that I never found satisfactory treat-ment of in textbooks – is presented with insights and from angles that hopefully will reduce it to analysis by inspection for readers. Some circuit transformations that I call the b transform and the m transform, its dual, are especially helpful in reducing circuits to simpler forms for analysis. They are usefully applied in considering transistor circuits for which collector-emitter (or drain-source) resistance is not negligible, a topic often omitted in the coverage of amplifi er circuits.

Coverage of the list of basic amplifi er stages, including two-transistor combi-nations and their interactions when connected, results in enough material for a book – this book.

Much of what is in this book must be credited in part to others from whom I picked up essential ideas about circuits at Tektronix, mainly in the 1970s. I am particularly indebted to Bruce Hofer, a founder of Audio Precision Inc.; Carl Battjes, who founded and taught the Tek Amplifi er Frequency and Transient Response (AFTR) course; Laudie Doubrava, who investigated power supply topics; and Art Metz, for his clever contributions to a number of designs, some extending from the seminal work on translinear circuits by Barrie Gilbert, also at Tek at the same time. Then there is Jim Woo, who, like Battjes, is another oscilloscope vertical amplifi er designer; Ian Getreu and Bob Nordstrom, from whom I learned transistors; and Mike Freiling, an artifi cial intelligence researcher in Tektronix Laboratories whose work in knowledge

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Preface xi

representation of physical systems infl uenced my broader understanding of electronics.

In addition, in no particular order, are Fred Beckett, Lee Jalovec, Wayne Kelsoe, Cal Diller, Marv LaVoie, Keith Lofstrom, Peter Staric, Erik Margan, Tim Sauerwein, George Ermini, Jim Geddes, Carl Hollingsworth, Chuck Barrows, Dick Hung, Carl Matson, Don Hall, Phil Crosby, Keith Ericson, John Taggart, John Zeigler, Mike Cranford, Allan Plunkett, Neldon Wagner, and Paul Magerl. These and others I have failed to name have contributed personally to my knowledge as an engineer and indirectly to this book. Most of all, I am indebted to the creator of our universe, who made electronics possible. Any errors or weaknesses in this book, however, are my own.

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3Amplifi er Concepts

THE REDUCTION THEOREM

The b transform greatly simplifi es open-loop amplifi er circuit analysis and makes the transresistance method possible. We now examine circuits with more complex topologies. It is common for transistor amplifi er stages to have a sig-nifi cant forward transmittance through ro. This results in parallel forward paths. Parallel c-e or c-b resistance causes bilateral signal fl ow with a combination of feedback and multiple forward paths.

This leads to some network theorems that are useful for simplifying these circuits. Analytic techniques adaptable to intuitive use are based on powerful, general circuit theorems. The b transform is half of a more general theorem, the reduction theorem. It has two forms:

current form transform⇒ β

voltage form transform⇒ μ

These forms are duals. The fi gure below portrays the b transform as a general network theorem. Two networks, represented by blocks, share a common port with a controlled source between them. In the current-source case, network N1 could be a bipolar junction transmitter (BJT) base circuit, in which i is the base current. Then network N2 is the emitter circuit, and the current source that shunts the common port is a BJT collector current source.

Wherever circuits are equivalent to the top network, two equivalent circuits (middle and bottom) are possible. These correspond, respectively, to equivalent

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74 Chapter 3

base and emitter circuits for a BJT. In the middle diagram, N2 is transformed using b + 1; in the bottom, N1 is transformed instead. All voltages, currents, and resistances in the transformed network are affected as shown.

N1 N2i ( )β + 1 i

r1

v1

i1

r2

v2

i2

β i

b transform

N2 referred to N1

N1 referred to N2

ir

v

i

v

r2( )β + 1

i ( )β + 1/

( )β + 1 i

v

r2

v

i

( )β + 1

( )β + 1 i

1

1

1

2

2

1

1

/r1

2

2

The fi gure below displays the corresponding dual of the b transform, the m transform. It applies to circuits with a voltage gain because m is a voltage gain. This transform was used extensively in modeling vacuum-tube triodes and applies especially to fi eld-effect transistors (FETs) because of their low drain resistance. It enables us to avoid use of feedback analysis in shunt-feedback circuits by transforming them into circuits most easily analyzed open-loop.


Amplifi er Concepts 75

m TRANSFORM OF BJT AND FET T MODELS

The m transform cannot be applied directly to circuits using the T model because the transform is based on a controlled voltage source. The T model, shown below, is shunted by ro. This familiar model is used later when feedback analysis is applied to multipath circuits. For now, it must be transformed into a model with a controlled voltage source. This can be done by fi rst referring re to the base as rp (using the b transform). Then ro shunts the controlled current source and forms a Norton equivalent circuit with it. The Norton circuit can be converted to a Thevenin equivalent by noting that

β α α⋅ = ⋅ = ⋅⎛⎝⎜⎞⎠⎟ =i i

vr

vr

b ebe

e

be

m

N1 N2

r1

v

i

r2

v

i

r1

v

i

r2

i

r2

v

i

mv– +

+

_

+

_μ + 1( )vv

+

_v

μ + 1( )/

v μ + 1( )/

+

_μ + 1( ) v

r

i

μ + 1( )

v1μ + 1( )

1

1 2

2

2

2

2

2

1

1

1

1

m transform

N2 referred to N1

N1 referred to N2


76 Chapter 3

This current is converted to a Thevenin voltage by multiplying by the series resistance ro, resulting in

rvr

rr

v vobe

m

o

mbe be⋅⎛⎝⎜

⎞⎠⎟ = ⎛

⎝⎜⎞⎠⎟ ⋅ = ⋅μ

More precisely, the defi nition of m for the BJT model is

μ ≡ −=

vv

ce

be ic 0

b

e

re

ro

c

ib

b

e

ro

c

ib

T model with ro Norton equivalenthybrid-p

Thevenin equivalenthybrid-p

rp

rp

vbe

+

–

ro

c

e

b+ –

mvbe

bibbib

The condition that ic be zero allows vce to be the voltage of the controlled source alone, without additional drop across ro. Furthermore,



μμ +

⎛⎝⎜

⎞⎠⎟

=+

=−− ( ) = −

−=

=1 10

0

rr r

v v

v vv

v vo

o m

ce be i

ce be i

ce

be ce i

c

c c == = =

= =0 0 0

vv

vv

ce

cb i

ec

bc ic c

For ic = 0 (and fi nite collector resistance), then vc = 0 and

λ μμ

=+

⎛⎝⎜

⎞⎠⎟

=1

vv

e

b

This relationship appears often in circuit analyses and is designated by l, the counterpart of a = b/(b + 1).

A similar transformation can be applied to the quasistatic FET circuit model, shown below, where ro is included.

g

s

ro

d

vgs

g

s

ro

mvgs

d

Thevenized FET model

vgs

+

-

ro

d

s

g

FET T modelFET model with ro

rm

vgs

+

-

vgs

+

+

-

-

rm

vgs

rm

The model immediately converts to the Thevenin equivalent form of the BJT model. An alternative equivalent model is also shown, in which the gate is con-nected to the current source and rm is added. This is an FET T model. The gate current ig remains zero because all ig must fl ow through rm. Its resulting voltage drop affects vgs, and since the current source is controlled by vgs, a change in drain current equal to ig is injected into the gate node. In other words, since the voltage across rm is vgs, the current that must be fl owing in rm is vgs/rm. But this is the amount of current injected into the gate node by the drain current source. By Kirchhoff’s current law (KCL), ig must be zero.


78 Chapter 3

The defi nition of m applied to this FET model is substantially the same as the BJT model. The relationship between the BJT and FET models is simple: If re of the BJT model is replaced by rm, the FET model results.

BJT to FET T-Model Conversion

r r e s b g c d v ve m be gs⇒ ⇒ ⇒ ⇒ ⇒, , , ,

Applying this conversion to the BJT defi nition of m results in the FET version of m:

FET μ ≡ −=

vv

ds

gs id 0

Because ro for FETs is typically much lower than for BJTs, the use of transistor models that include ro is more common for FETs.

COMMON-GATE AMPLIFIER WITH ro

The fi gure below shows a common-gate (CG) amplifi er, drawn so that the reduc-tion theorem can be easily applied to it. The gate is at ground and is the common terminal of the two networks shown in boxes. Network N1 is the source circuit, and N2 is the drain circuit.

The FET model of the CG circuit is between N1 and N2. To make this circuit correspond to the m-transform circuit, ro must be included in N2. The result of transforming the drain circuit (N2) is shown in the lower equivalent circuit. The drain circuit has been referred to the source side. The output voltage vo across RL is also transformed to vo/(m + 1). This transformed circuit is now a voltage divider between input vi and output vo/(m + 1):

v RR r R

vo L

S o Liμ

μμ μ+

= +( )+ +( ) + +( )

⋅1

11 1

The voltage gain is thus



CG AR

R R rv

L

S L o

=+ +( ) +( )μ 1

This result is reminiscent of the transresistance method but uses the m transform instead of the b transform. It demonstrates the voltage form of the transresis-tance method. The denominator of the expression for CG Av can be interpreted as amplifi er transresistance, rM. The resistance in the drain contributes to rM and appears smaller by 1/(m + 1) when referred to the source side of the FET. The b transform involves base and emitter networks; the m transform involves the drain (or collector) and source (or emitter) circuits instead.

The input resistance rin can be envisioned directly from the upper circuit to be

CG rr R

Rino L

S= ++

+μ 1

RS

vi

–

N2N1

+

g

– –

+ –

RL

ro

vos

++

vgs vgs( + 1)μ

+ 1μRL

+ 1μvo

+ 1μro

s

RS

vi

–

+

–

+

vgs

dmvgs


80 Chapter 3

The CG output resistance can be found by m-transforming the source circuit. In this case, the resistance of the source referred to the drain is (m + 1) times larger, so that

CG r R r Rout L o S= + +( )[ ]μ 1

COMMON-SOURCE AMPLIFIER WITH ro

A common-source (CS) FET amplifi er is shown below.

vo

g

vi

–

++vgs

–

RS

s

mvgs

d

+

–

ro

RL

+ mvg –

RS

vi

–

N2

+

+ +

mvs– +

RL

––

vs (m + 1) vs

s

g

vgs

+

–

ro

N1

vo

The voltage-source FET model makes Kirchhoff’s voltage law (KVL) analysis easy with only one loop. The needed equations are

v i Rs s S= ⋅

v i Ro s L= − ⋅

i R r R v v R is S o L gs g S s⋅ + +[ ] = ⋅ = ⋅ − ⋅ ⋅μ μ μ

Solving for Av gives



vv

Rr R R

o

g

L

m L S

= −+ ( ) + +( )( )⋅μ μ μ1

Although this gain is a ratio of resistances, the terms in the denominator involving m do not have a simple interpretation in terms of the m transform and circuit topology. But by factoring (m + 1)/m out of the denominator, we obtain two factors containing vs:

CS AR

R r R

v v v v

vL

S o L

s g o s

= −+

⎛⎝⎜

⎞⎠⎟

⋅+ +( ) +( )

↑ ↑

( ) ( )

μμ μ1 1

The fi rst factor, l, is the gate-to-source gain. The second is the same as the CG Av. Its denominator can be interpreted as rM, keeping in mind that it is vs (not vg) across rM that generates is. Consequently, the voltage form of the transresis-tance method is based on fi nding rM across vs and then (if needed) relating vs to vg through l:

rvi

Ms

s

=

and

v v vs g g=+

⎛⎝⎜

⎞⎠⎟

⋅ = ⋅μμ

λ1

The gain expression of vo/vg was found using basic circuit laws, not by applying the m transform directly to the circuit topology. To do so for the CS is not as obvious as for the CG. The gate is not common to both source and drain circuits. In the circuit shown above, it is redrawn on the right so that application of the m transform is explicit. Because the port voltage is chosen to be vs, the drain voltage source m · vgs is split into two sources so that the fi rst is dependent upon vs. The remaining source, m · vg, becomes part of the drain network and is


82 Chapter 3

The voltage across the source-referred RL is

v vr

Ro i

M

L

μλ

μ+= − ⋅ ⋅

+⎛⎝⎜

⎞⎠⎟1 1

Solving for the voltage gain gives

CS AR

R r RR

R r Rv

L

S o L

L

S s L

= − ⋅+ +( ) +( )

= − ⋅+ + +( )

λμ

λμ1 1

The expression ro/(m + 1) has been expressed as

rr r

rso o

m=+

= ⋅+

⎛⎝⎜

⎞⎠⎟

= ⋅μ μ

μμ

λ1 1

When ro is referred to the source, it transforms to rs, the FET analog of re, in that both are related to rm by dual factors, a and l. Although a expresses a current loss due to base current, l expresses a voltage loss due to vgs; m and b are duals, as are l = m/(m + 1) and a = b/(b + 1).

m Transform (Voltage) b Transform (Current)

m bl = m/(m + 1) a = b/(b + 1)

The input resistance of the CS amplifi er is infi nite. The output resistance is the same as the CG; the source circuit referred to the drain is the same for both.

RL

m + 1

m + 1

m + 1 vo

ro

RS

+ –lvi

transformed along with it. When the m transform is applied to the drain circuit, the circuit shown below results.



COMMON-DRAIN AMPLIFIER WITH ro

The last of the three basic FET confi gurations is the common-drain (CD) or source-follower, shown below. Applying the voltage form of the transresistance method, rM is found by determining the resistance across which the source voltage generates the source current is. The m transform is required to refer the resistance on the drain side of the FET voltage source to the source side.

vo

g

vi

–

++vgs

mvgs

–

RS

s

d

+

–

ro

RD

As before, it is

rR

sD++μ 1

This resistance, when referred to the source circuit, is in series with RS. The total transresistance is thus

r R rR

M S sD= + ++μ 1


84 Chapter 3

The source current generated by vs across rM develops an output voltage across RS. The voltage gain from gate to source must include the l factor;

CD AR

R r Rv

S

S s D

= ⋅+ + +( )

λμ 1

This gain is more general than for a CD amplifi er without a resistance in the drain, RD.

The input resistance of the CD is infi nite, and the output resistance is

CD r R rR

out S sD= ++

⎛⎝⎜

⎞⎠⎟μ 1

FET CASCODE AMPLIFIER WITH ro

The voltage form of the transresistance method extends directly to multiple-transistor amplifi er stages. The FET cascode amplifi er model, shown below, has a voltage gain of

cascode AR

Rr r R

R

R r r

vL

So o L

L

S s

= − ⋅+ + +( ) +( )( )

+

= − ⋅+ +

λ μμ

λ

11 2 2

1

1

1

11

ssLR

2 12

1

11

1μ μ

μ+( ) + +( )( )

+

This can be interpreted (and also constructed) by inspection of the circuit diagram. The input voltage vi at the gate of the CS produces vs via l1. The CS rM is RS in series with the drain resistance, referred to the source. Drain resis-tance is ro1 in series with the CG drain circuit referred to its source, or (ro2 + RL)/(m2 + 1). When these resistances are referred to the CS source, the denomi-nator of the previous gain equations, rM, results. The source current develops the output voltage, vo, over RL (in the numerator) and is an inverting output. Av can be written as the lower equation just presented, using the defi nition of rs, which is ro referred to the source circuit.



The output resistance of the cascode stage can be found using the same approach and is

cascode r R r r Rout L o o S= + +( )⋅ + +( )⋅( )[ ]2 2 1 11 1μ μ

To construct this expression for rout, the m transform is used to refer source resistances to the drain circuit.

COMMON-BASE AMPLIFIER WITH ro

The application of the voltage form of the transresistance method to BJT amplifi ers adds the complication of rp. It forms an additional loop or node not present in the CG circuit. This complication does not signifi cantly affect the approach.

RL

vo

d

ro2

–

+

d

s

ro1

–

+s

cascode

RS

g

+

–

–

g

+

vi

–

+

m1vgs1

m2vgs2

vgs1

vgs2


86 Chapter 3

The circuit model is redrawn (upper right) to make the application of the m transform explicit. After the collector circuit is referred to the emitter side (middle), the divider formed by RE and rp is Thevenized (lower). The voltage gain can then be found by solving the voltage divider:

RL

c

ro

–

+

e

–

+

vo

RE

RE

vi

b rp

rπ

rp

rp

rp

+ –

+vi

–

e

b

c

–

+

–+

+vi

–

RE

RE

ro

ro

ro

vo

vo

vo

RL

RL

RL

–

+

ic

ic

+

vi

–

–

+

⏐⏐

(rp + RE)

mvbe

m + 1

m + 1

m + 1

m + 1

m + 1

m + 1

mvbe

vbe

vbe

vbe

vbe



CB Ar

r RR

r R R r

v v v v

vE

L

E L o

e i o e

=+

⎛⎝⎜

⎞⎠⎟

⋅+ +( ) +( )

↑ ↑( ) ( )

π

π π μ 1

This gain expression has two additional complications over that of the CG. At the emitter, RE is now shunted by rp. This affects rM in the second factor of the common-base (CB) gain equation. The fi rst factor accounts for the divider formed by rp with RE. An alternative formulation of Av regards rp and RE as forming a current divider with a transmittance of (ic/ie):

CB Ar

r r RR

R r r R

ii

vo L

L

E o L

c

e

=+ +( ) +( )

⎡⎣⎢

⎤⎦⎥⋅

+ +( ) +( )[ ]

= ⎛⎝⎜

π

π πμ μ1 1

⎞⎞⎠⎟ ⋅⎛⎝⎜

⎞⎠⎟ ⋅⎛⎝⎜

⎞⎠⎟ = ⎛

⎝⎜⎞⎠⎟ ⋅⎛⎝⎜

⎞⎠⎟ ⋅( )i

vvi

ii r

Re

i

o

c

c

e inL

1

For the CB gain equation, ie is the common quantity of the transresistance method. The input vi generates ie across the input resistance rin, which is rM, the denominator of the second factor:

CB r R rr R

in Eo L= + +

+⎛⎝⎜

⎞⎠⎟π μ 1

Some of ie is lost to the base, leaving ic, and is accounted for by the fi rst factor of CB Av. The output voltage is then developed across RL by ic. In this formula-tion, both voltage and current forms of the transresistance method are present. The m transform refers the collector resistances to the emitter; the voltage form is applied. The (ic/ie) factor, however, is a circuit-dependent a characteristic of gain equations resulting from the current form. In contrast, the previous CB gain equation has a purely voltage-form interpretation. It is easier to apply only one form, and is preferred in most cases.

The CB output resistance is found by applying the m transform to the emitter circuit:


88 Chapter 3

CB r R r r R R rout L o E L c= + +( )⋅( )[ ] =μ π1

The m-transformed expression for the collector resistance, rc, has been derived before:

rvi

R R rR

R Rc

c

cE B o

E

B E

= = + + ⋅+

⎛⎝⎜

⎞⎠⎟

1 β

This equivalent formula was given a b-transform interpretation before. To derive rc of CB rout from rc, substitute m · rp for b · ro and let RB = rp.

CC AND CE AMPLIFIERS WITH ro

The common-collector (CC) (emitter-follower) is shown below, with a simpli-fi ed equivalent circuit. This is a generalized CC amplifi er in that collector resis-tance is included.

Following the approach used with the CS amplifi er, the gain is

CC passAR

R rR r

R r R rv

E

E

C o

E C o

=+

⎡⎣⎢

⎤⎦⎥⋅ +( ) +( )

+ +( ) +( )⎡⎣⎢

⎤⎦⎥

π π

μμ1

1iive path

active path+ ⋅+ +( ) +( )

⎡⎣⎢

⎤⎦⎥λ

μπ

π

R rR r R r

E

E C o 1

The CC has two gain paths: an active path due to the gain of the transistor, and a passive path due to a fi nite rp. The fi rst factor of both terms is (ve/vi). For the active path, the second factor is a ratio of load resistance RE||rp over rM.

The second factor of the passive path term is a voltage-divider gain due to the drop across the collector resistance, referred to the emitter. This is a loaded divider with

Rr R

Eo C+( )

+( )μ 1



The passive path gain can be rewritten to make this explicit:

R r RR r R r

E o C

E o C

+( ) +( )[ ]+( ) +( )[ ] +

μμ π

11

The fi gure below shows the common-emitter (CE) circuit model and its succes-sive modifi cations leading to equivalent circuit (e).

Again, the m transform reduces this circuit to a voltage divider. rp creates a loaded divider (c) that is Thevenized in (d). The voltage source, l · vi is combined with vi in (e), from which a voltage gain expression can be written as

CE

ac

AR

R rR

R r r R

v v v v

vE

E

L

L o E

e i o e

= − ++

⎛⎝⎜

⎞⎠⎟

⋅+( ) +( ) +

↑ ↑ ↑( ) ( )

λμπ π1

ttive passivepath path

RC

c

ro

–

+

e

RE

b

+ –

vo

+vi

–

+

–

vo

⏐⏐

( )RE

ve

+

–

ro + RC

mvbe

m + 1

rprp RE

vi

vbe

lviRE + rp


90 Chapter 3

e ro cvo

RL

+

–

ve

(b)

+vi–

bRE

–++–

RL

c

ro

–

+

e

RE

b

+ –

(a)

+vi

–

vo

+vi

–

ro

vo

RL

(c)

μ + 1

μ + 1

μ + 1( )μ

μ + 1

+ –

vi

RE ve

+

–

+vi

–

ro

vo

RL

(e)

μ + 1

μ + 1

μ + 1⏐⏐

( )μ + 1μ

–( )[ ]

+vi

–

ro

vo

RL

–+μ + 1

μ + 1

μ + 1⏐⏐

( )

ve

lvi

(d)

rp

rp

rp

mvbe

mve mvb

vbe

RE + rp

RE

RE + rp

RE

rpRE

rpRE



The second factor of the CE Av is the load resistance over rM, the same as for the CB amplifi er. The novelty is in the fi rst factor. The fi rst term, −l, is the m-transform base-to-emitter voltage gain due to the active device m amplifi cation; it expresses the gain due to the active forward path. The CS Av contained only this term. With the CE, the second term is added due (once again) to rp. This term represents a voltage divider formed from rp and RE and expresses the gain of a passive path from input to output. This term gives the passive gain from vi to ve. The voltage component of ve due to the passive path is then amplifi ed along with the active path component by the second factor of the CE Av. Because the passive-path gain is noninverting, it decreases the overall (inverting) gain somewhat.

The output resistance can be obtained by direct application of the m trans-form to the input side of the circuit:

CE r R r r Rout L o E= + +( )⋅( )[ ]μ π1

The input resistance rin of the CE can be found by redrawing (c) as shown below. The right side is Thevenized in (b). The voltage source on the right is controlled by vi and affects rin. Resorting to basic circuit analysis, we can solve for the input resistance:

rvi

v

vR

R R rv

r R R r

ini

i

i

iE

E L oi

E L o

=− ⋅

+ +( ) +( )⎛⎝⎜

⎞⎠⎟

+ +( ) +( )

λμ

μπ

11

CE r rR

R R rR R rin

E

E L oE L o= ⋅

+ +⎛⎝⎜

⎞⎠⎟

+⎡⎣⎢

⎤⎦⎥ + +( )π μ 1

This expression is not immediately apparent from the circuit topology, as previous circuit expressions were and reveals limits to the extent a topology-oriented approach can take. Substituting b · ro for m · rp gives an alternative b-transform-like expression. It is left to the reader to fi nd a topology-oriented explanation for these expressions of rin.


92 Chapter 3

LOADED DIVIDERS, SOURCE SHIFTING, AND THE SUBSTITUTION THEOREM

For circuits with more that three branch or loop equations, fi nding algebraic solutions can be tedious. In these situations, the following formulas are often useful. Thevenin and Norton circuits for loaded dividers are shown below. For the voltage divider in (a),

v va c

a c bi

vc

a ca c b c

vi i= ⋅+

⎛⎝⎜

⎞⎠⎟

= =+

⎛⎝⎜

⎞⎠⎟

⋅⎛⎝⎞⎠ ⋅,

1

and for the current divider in (b),

ia b

a b cvb

i=+

⎛⎝⎜

⎞⎠⎟

⋅⎛⎝⎞⎠

Loaded dividers often appear, and it is useful to be able to reverse the loading, as the following formulas allow:

+

–

+

–

λvi

+ 1μ

(a)

vi

vi

+

–

rin

rin

+

–

viλ

+ 1μ

(b)

⏐⏐⏐⏐⏐⏐⏐⏐

RE

RE

RE

RE + (ro + RL)/(m + 1)

ro + RL

ro + RLrp

rp



a b c a c ba ca b

+ = +( )⋅ ++

⎛⎝

⎞⎠

a ca c b

a ba b c

cb+

=+

⋅

It is also handy to note that

a ba

ba b

=+

The manipulation of expressions involving the || operation are made easier by the following properties:

associative property of : a b c a b c( ) = ( )

distributive property of over× = ⋅( ): ab ac a b c

commutative property of : a b b a=

a bc d

a bc

a bd

= +

vi

b

vi

+

–

b

(a)

c

iv

a

(b)

c

iv

ab


94 Chapter 3

Source Shifting

An alternative to algebraic manipulation is the direct manipulation of circuit models. The source-shifting transformation can separate a circuit into two inde-pendent circuits, as shown below. A current source is replaced by two sources with the same current in series. This change introduces an additional node c between the two sources. This is useful, for example, in transforming a loop with a fl oating current source into two separate loops with ground-referenced current sources, as shown in (b).

a b

ii

c

a b

(a)

i

1 R2

(b)

R1 R2i i

i

R

The voltage dual of this source-shifting transformation is shown below.A voltage source is replaced by two parallel sources of the same voltage. This

transformation is useful in separating two branches, giving each its own source, as in (b).

Substitution Theorem

The substitution theorem applies to controlled sources as shown below. It too has dual current and voltage forms. In (a), a voltage-controlled current source (VCCS) of current v/r has a terminal voltage of v. Because it is controlled by the voltage across its terminals, it behaves as a resistance of r. Similarly, the



current-controlled voltage source (CCVS) in (b) has a terminal voltage of ri with current i, and is also equivalent to a resistance of r.

a b

v+ –

R1 R2 R1 R2

ba

v+ –

v+ –

(a)

(b)

v

+

–

v

+

–

v

+

–

v

+

–

v

+

–

r

v r/

vr

(a)

r·i

+

–

i

rVCCS

rCCVS

(b)

i

rr·i

+

–


96 Chapter 3

To demonstrate source shifting and the substitution theorem, the CS with ro is modeled in (a) below.

vi

+

–

(a)

RS RL

ro

vgs + –g

vo

vgs rm

vg rm RS RL vo

+

–

rovs

(c)

vgs rm rm

vg rm

vs rm RS

vgs rm vo

+

–

rovs

RL

(b)

Current-source shifting is applied, resulting in (b). This circuit is also modifi ed by splitting vgs/rm into two sources, vg/rm and vs/rm. The current source, vs/rm is across vs, and the substitution theorem can be applied, resulting in rm in (c). Successive applications of Norton and Thevenin conversions then reduce the circuit to an equivalent form, from which the CS gain readily follows.

CLOSURE

The dual forms of the reduction theorem, source-shifting, and the substitu-tion theorem expand the power of circuit analysis, allowing the reduction of active amplifi er stages to voltage and current dividers. These methods, however, are not suffi cient in themselves. In the next chapter, feedback theory is developed – another analytic method that greatly simplifi es circuit analysis. The methods of this chapter are based on transformations of networks that eliminate dependent sources and result in a single network. Feedback theory reduces signal paths (transmittances) instead, resulting in a single transmittance.


Designing Dynamic Circuit Response


Raleigh, NC.


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10 9 8 7 6 5 4 3 2 1

ISBN: 9781891121838Series ISBN: 9781891121876

Library of Congress Cataloging-in-Publication DataFeucht, Dennis. Designing dynamic circuit response / D. Feucht. p. cm. -- (Analog circuit design series ; v. 2) Includes bibliographical references and index. ISBN 978-1-891121-83-8 (pbk. : alk. paper) – ISBN 978-1-891121-87-6 (series) 1. Frequency response (Dynamics) 2. Transients (Dynamics) 3. Electronic circuit design. I. Title. TK7867.F48 2010 621.3815′35--dc22

2009028289

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Contents

Chapter 1 Transient and Frequency Response. . . . . . . . . . . . . . . . . . . . . . . . 1Reactive Circuit Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1First-Order Time-Domain Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . 4Complex Poles and the Complex Frequency Domain . . . . . . . . . . . . . . . . . . . . 7Second-Order Time-Domain Response: RLC Circuit . . . . . . . . . . . . . . . . . . . . 10Forced Response and Transfer Functions in the s-Domain . . . . . . . . . . . . . . . 16The Laplace Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Time-Domain Response to a Unit Step Function . . . . . . . . . . . . . . . . . . . . . . . 29Circuit Characterization in the Time Domain. . . . . . . . . . . . . . . . . . . . . . . . . . 37The s-Plane Frequency Response of Transfer Functions. . . . . . . . . . . . . . . . . . 41Graphical Representation of Frequency Response . . . . . . . . . . . . . . . . . . . . . . 43Loci of Quadratic Poles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Optimization of Time-Domain and Frequency-Domain Response . . . . . . . . . 53Reactance Chart Transfer Functions of Passive Circuits . . . . . . . . . . . . . . . . . . 61Closure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Chapter 2 Dynamic Response Compensation . . . . . . . . . . . . . . . . . . . . . . . 75Passive Compensation: Voltage Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Op-Amp Transfer Functions from Reactance Charts . . . . . . . . . . . . . . . . . . . . 78Feedback Circuit Response Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Feedback Circuit Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Compensation Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Compensator Design: Compensating with Zeros in H . . . . . . . . . . . . . . . . . . 105Compensator Design: Reducing Static Loop Gain . . . . . . . . . . . . . . . . . . . . . 118Compensator Design: Pole Separation and Parameter Variation . . . . . . . . . 120

FDCPR.indd vFDCPR.indd v 7/29/2009 10:11:26 AM7/29/2009 10:11:26 AM

Two-Pole Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Output Load Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Complex Pole Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159Compensation by the Direct (Truxal’s) Method . . . . . . . . . . . . . . . . . . . . . . . 162Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Chapter 3 High-Frequency Impedance Transformations. . . . . . . . . . . . . . .167Active Device Behavior above Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167BJT High-Frequency Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168Impedance Transformations in the High-Frequency Region . . . . . . . . . . . . . 170Reactance Chart Representation of b-Gyrated Circuits. . . . . . . . . . . . . . . . . . 177Reactance Chart Stability Criteria for Resonances . . . . . . . . . . . . . . . . . . . . . 179Emitter-Follower Reactance-Plot Stability Analysis. . . . . . . . . . . . . . . . . . . . . . 181Emitter-Follower High-Frequency Equivalent Circuit . . . . . . . . . . . . . . . . . . . 183Emitter-Follower High-Frequency Compensation . . . . . . . . . . . . . . . . . . . . . . 186Emitter-Follower Resonance Analysis from the Base Circuit . . . . . . . . . . . . . 190Emitter-Follower Compensation with a Base Series RC . . . . . . . . . . . . . . . . . 191BJT Amplifi er with Base Inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193The Effect of rb′ on Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195Field-Effect Transistor High-Frequency Analysis . . . . . . . . . . . . . . . . . . . . . . . 197Output Impedance of a Feedback Amplifi er . . . . . . . . . . . . . . . . . . . . . . . . . . 198Closure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

vi Contents

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2Dynamic Response Compensation

PASSIVE COMPENSATION: VOLTAGE DIVIDER

Vi(s)

Vo(s)

R1

R2 C2

C1

+

−

The familiar resistive voltage divider, shown above, illustrates the idea of com-pensation. When a capacitive load C2 shunts R2, the step response is overdamped and bandwidth is reduced. To compensate for C2, C1 is added in parallel with R1. The transfer function of this divider is

V sV s

RR R

s R Cs R R C C

o

i

( )( )

=+

⎛⎝⎜

⎞⎠⎟

⋅ ⋅ +⋅( )⋅ +( ) +

2

1 2

1 1

1 2 1 2

11

The addition of C1 introduces a fi nite zero and makes N(s) and D(s) of the same degree in s, a condition for an all-pass fi lter. When the pole and zero are equated, the (all-pass) compensation condition is

R C R C1 1 2 2⋅ = ⋅

A similar technique can be used with the current-divider dual, in which series load inductance is compensated by placing series inductance in the other

FDC02.indd 75FDC02.indd 75 7/29/2009 10:10:27 AM7/29/2009 10:10:27 AM

76 Chapter 2

branch of the divider. To compensate, the L/R time constants of the two branches are set equal.

v

t

1 + a

1 − a

1

Now suppose that this divider, or a circuit with a similar transfer function, is not properly compensated and has a step response like that shown above, in which the fractional overshoot or undershoot is a. This time response is

L L L− − −++

⋅⎧⎨⎩

⎫⎬⎭

=+

++( )

⎧⎨⎩

⎫⎬⎭

=1 1 111

11

11

ss s s s s s

z

p

z

p p

z

p

ττ

ττ τ

ττ ++

+ +−

+⎧⎨⎩

⎫⎬⎭

= + −⎡

⎣⎢

⎤

⎦⎥⋅ −

11

1

1 1

s s

e

p

p

z

p

t p

ττ

ττ

τ

At t = 0, the exponential is 1. Its coeffi cient therefore is a, and the relationship between the pole and zero time constant is

τ τz pa= +( )⋅1

An additional cascaded compensation network with a pole time constant tpc = tz and a zero time constant tzc = tp results in a fl at frequency and step response. The value of tp can be estimated by observing the transient decay of the step response. The settling time is 4 to 5 times tp as observed on an oscillo-scope screen. With this estimate for tp and from measurement of a from the step response, tz can be calculated from the above equation.

Example: Shunt-Series All-Pass Circuit

This circuit has a terminal impedance of


Dynamic Response Compensation 77

R2R1

Z

L C

Z RsL R sR C

s LC s R R CR

s LCR R s L R R= ⋅ +( ) +( )+ +( ) +

= ⋅ ( ) + +1

1 22

1 21

22 1 11 1

122

21 2

11C

s LC s R R C( ) +

+ +( ) +

Z has two poles and two zeros. If the poles and zeros cancel, the input resistance is merely R1 and is independent of frequency. This is achieved when

LCRR

LCLR

R C R R C⋅⎛⎝⎜⎞⎠⎟ = + ⋅ = +( )⋅2

1 12 1 2,

or

R R RLR

R C1 2= = = ⋅,

This circuit suggests frequency compensation schemes. A series RC can be com-pensated with a series RL and vice versa.

Example: Series-Shunt All-Pass Circuit

This is the dual of the previous example, for which

ZsL

sL RR

sR CR

s LC s L R L Rs LCR R s L R

=+

++

= ⋅ + ( ) + ( )[ ] +[ ] +1

2

22

21 2

22 11 1

1

11 2 1+[ ] +R C

The all-pass conditions are found by equating N(s) and D(s) and then equating coeffi cients:


78 Chapter 2

L C RR

L CLR

LR

LR

R C⋅ ⋅ = ⋅ + = + ⋅2

1 1 2 12,

This reduces to the all-pass conditions:

R R RLR

R C1 2= = = ⋅,

Note that they are the same as for the previous circuit example. For both, R = Zn.

OP-AMP TRANSFER FUNCTIONS FROM REACTANCE CHARTS

The reactance-chart method can be applied to operational amplifi er (op-amp) circuits to fi nd their transfer functions. With this capability, we can more easily attend to their compensation. To begin, consider the voltage gain of ideal invert-ing op-amps:

V sV s

Z sZ s

o

i

f

i

( )( )

= −( )( )

This is an s-domain extension of the inverting-op-amp gain equation (from Design-ing Amplifi er Circuits) and assumes an infi nite op-amp bandwidth and gain.

R1

R2

Z

C

L



Under these simplifying conditions, the op-amp integrator and differentiator shown above have the following gains.

Op-amp integrator:

V sV s sRC

o

i

( )( )

= − 1

Op-amp differentiator:

V sV s

sRCo

i

( )( )

= −

The transfer functions are shown on the Bode plots of fi gures (b) and (d) above, to the right of their respective circuits.

For the op-amp integrator, a fi nite-gain op-amp cannot supply adequate gain as the input frequency approaches zero. At 0 Hz (dc), the op-amp circuit is open loop and subject to static drift from offset errors. To stabilize the closed-loop gain (at some high value and at a low frequency), the feedback capacitor is shunted by a large resistor, as shown below.

Vi

Vi

Vo

R

(a) (b)

C

−−1

+1

1+

Vo

RC

−

+

(c) (d)

log w

log⏐⏐ ⏐⏐Av

1RC

1 log w

log⏐⏐ ⏐⏐Av

1RC


80 Chapter 2

The static gain is then −Rf/Ri and the output, though not exactly the integral, is predictable and stable.

Vi

Rf

Vo

Ri

C

−

+

= −Rf

RiAv ·

1sRf C + 1

Rf

Ri

Rf

Ri

log w

log⏐⏐ ⏐⏐Av

log⏐⏐ ⏐⏐Z

⏐⏐ ⏐⏐Zf

1Rf C

log w1Rf C

The reactance plots for ||Zf || and ||Zi|| are shown above. The ratio, ||Zf ||/||Zi||, is the magnitude of the gain ||Av||. At frequencies below wp = 1/RfC, C is effectively an open circuit, and the gain is determined by the resistors. Above wp, C domi-nates Rf, and integration occurs; the −1 slope (single-pole roll-off) is character-istic of time-domain integration.

The op-amp differentiator has similar limitations but at high frequencies. To limit high-frequency gain, Ri is added in series with C, as shown below.



The differentiator is statically stable because of the resistive feedback. Above wp = 1/RiC, the circuit fails to accurately differentiate, and the gain is deter-mined by the resistors. The transfer function plot is derived from the reactance chart as before, shown below.

Vi

RiRf

Vo

C−

+

=Avs

sRi C + 1−Rf C

Rf

Ri

Rf

Ri

log w

log⏐⏐ ⏐⏐Av

log⏐⏐ ⏐⏐Z

⏐⏐ ⏐⏐Zi

⏐⏐ ⏐⏐Zi

1Ri C

log w1Ri C

The reactance-chart method is not limited to these simpler examples. The following fi gure shows a more involved circuit.

Vi

A = – ————————————Rs + 1

sR Ci + 1 i–——————————Ci ))⏐⏐Ri(s(CfRs )Ri( +s

v

sR iR–

+Vo

CfCi


82 Chapter 2

For this circuit, ||Zf || = 1/w ⋅ Cf, and ||Zi|| is shown on the log ||Z || plot.

log ω log ω

log⏐⏐A ⏐⏐

1R Ci

v

i

log⏐⏐Z⏐⏐

Rs

Rs

Ri +Ci

1

R i

Cf

⏐⏐R s( )Ci

RiRs

⏐⏐Ri

⏐⏐⏐⏐Zi1Rs+Ri( )Cf

R i⏐⏐R s( )Ci

11R Cii

As shown for a similar passive circuit, the addition of Rs to the RiCi plot shifts it upward to Ri + Rs at 0 Hz. This ||Zi|| plot rolls off and intersects Rs at a break fre-quency that, if it were caused by Ci, would be due to an equivalent resistance of Rs||Ri. This is shown by the dotted lines with arrows. The upward-shifted ||Zi|| plot rolls off at a capacitive value less than Ci. Since the circuit has no capacitor of this value, the zero of ||Zi|| is referred to the Ci curve (following the dotted lines) so that its resulting expression is readily interpretable in terms of the circuit topology. The ||Av|| plot follows, as in previous examples, from the plots of ||Zf || and ||Zi||.

Vi

ARi Rs+

= −v

sR iR–

+Vo

sR Ci + 1 i( )sR + 1 c( )CcRf

Cc

Ci

Rc

Rf

Ri + 1 Ci )]⏐⏐Rss( [ Rf + 1 C )]Rcs( [ + c

The op-amp circuit shown above does not have a unique transfer function plot but depends on the relative values of its poles and zeros. The reactance-



chart method is limited in generality (compared with the s-domain transfer function Av) because only one case can be plotted. All possible orderings of pole and zero values have to be considered by generating separate plots. In practice, the relative (if not actual) values of the elements are known because they are determined by the functional requirements of the circuit.

log ω log ω1R Cii

1

R i⏐⏐R s( )Ci

log⏐⏐Z⏐⏐Rc

Rc

Rf +

⏐⏐Rf

RfRc

⏐⏐Z ⏐⏐f

Cc

1R c Cc

1Rf + R c( )Cc

log⏐⏐Z⏐⏐

RsRi +

RiRs

Rs⏐⏐Ri

Ci ⏐⏐Z ⏐⏐i

The reactance plot of ||Zf || is shifted from the plot of RcCc because ||Zf || = Rf ||Rc at high frequencies. At 0 Hz, ||Zf || must be Rf. The zero of ||Zf || is set by the RcCc plot, and ||Zf || has a −1 slope between resistances of Rf ||Rc and Rf. This slope represents a capacitance greater than Cc but not an actual circuit element value. Therefore, the break frequency at Rf is found by referring the resistance to the Cc plot (the dotted line with arrow pointing upward). The resistance at Cc is Rf + Rc, and the pole of ||Zf || is at 1/(Rf + Rc)Cc. This technique of scaling the impedance at a given frequency by referring to a reactive circuit element (such as Cc here) to fi nd the associated resistance is also used to fi nd ||Zi||.

When ||Zf || and ||Zi|| are combined to form ||Av||, the transfer function shown below results. In the particular plots shown above, Rf > Rc, Ri > Rs, and the order-ing of poles and zeros as shown is assumed. Again, this frequency response is not unique but depends on the placement of poles and zeros. Some ordering limitations are imposed by basic circuits laws. The pole at 1/(Ri||Rs)⋅Ci must always be higher in frequency than the zero at 1/Ri⋅Ci, and the zero at 1/Rc⋅Cc must be greater than the pole at 1/(Rf + Rc)⋅Cc. Furthermore, depending on circuit values, complex poles and zeros are possible for this circuit, and the reactance chart asymptotic approximations may not be adequate for lightly damped response.


84 Chapter 2

Noninverting op-amp frequency response is determined with the reactance chart method in the same way that passive dividers were treated previously. The difference is that for the op-amp, the closed-loop response is the reciprocal of the divider H, or

AZ Z

ZZZ

vf i

i

Hin

i

=+

=

where ZHin is the impedance of the feedback network from the op-amp output. On a reactance chart, ||ZHin|| is plotted by adding ||Zf || and ||Zi|| on the chart. Since asymptotic approximations are used,

log log

loglog ,

log ,

Z Z Z Z

Z ZZ Z Z

Z Z Z

1 2 12

22

12

22 1 1 2

2 2

12

+ = +

= ⋅ +( ) =>>�

11

⎧⎨⎩

Consequently, ||Z1 + Z2|| = ||Z1|| + ||Z2|| under the given constraints, and reactance chart impedance magnitudes can be asymptotically combined by addition of individual impedance magnitudes.

FEEDBACK CIRCUIT RESPONSE REPRESENTATION

The feedback techniques in Designing Amplifi er Circuits derived closed-loop response from loop gain. The closed-loop gain Av(s) is similarly determined from the loop gain GH(s). Feedback in the s-domain is the subject of control

log ω

log⏐⏐⏐⏐A ⏐⏐v

1R Cii

1

R i⏐⏐R s( )Ci

Ri +R s

Rs

fR

RfR c

1R Cc c

Rf +R1

( )c Cc



theory, found typically in control and circuits textbooks, and will not be system-atically developed here. Instead, basic aspects of amplifi er stability and desirable dynamic response are explained, leading to methods for compensation of ampli-fi ers that have undesirable responses.

Of the representations of Av(s), the Bode, Nyquist, and root-locus plots are the most commonly used. Bode plots are already familiar and present the fre-quency and phase response. Nyquist plots of the imaginary (jw-axis) and real (s-axis) components of GH with w as the parameter are an alternative repre-sentation. For each of these, closed-loop performance is determined by the loop-gain characteristics.

Root-locus diagrams are s-plane plots of the loci of closed-loop poles with open-loop gain K as a parameter. As K increases from zero, the closed-loop poles begin at open-loop poles and proceed toward open-loop zeros (some of which may be at infi nity). When these poles leave the left half-plane, the feedback circuit becomes unstable. The pole loci can be found by setting the denomina-tor of Av(s) to zero. Then,

1 0+ ( )⋅ ( ) =G s H s

or

GH e= − = ⋅ ±1 1 π

In polar form, the locus conditions are

GH GH= ∠( ) = ± °1 180,

Locating the loci in the s-plane is simplifi ed by root-locus rules. These rules are constraints imposed on the location of the closed-loop poles by these constraint equations. Some of the more commonly used (and easily remembered) rules are the following:

1. The root loci start at the poles of GH (for K = 0).

2. The root loci terminate at the zeros of GH.

3. There are as many separate root loci as poles of GH.


86 Chapter 2

4. The loci are symmetrical about the real axis.

5. The root loci are on the real axis to the left of an odd number of real poles and zeros of GH.

6. The sum of the closed-loop poles is constant. (The centroid of the loci remains constant.)

Other rules can also be constructed from the constraints.The Bode magnitude plot for an amplifi er with a frequency-independent H

and a single, real pole −p is shown below.

log

log w(KH + 1)p

1H

K

p

⏐⏐ ⏐⏐GH

The amplifi er gain is

G sK

s p( ) =

+ 1

The closed-loop gain for positive K and H is then

A sGGH

KKH s KH p

v( ) =+

=+

⎛⎝

⎞⎠ ⋅

+( ) +1 11

1 1

The closed-loop response is also that of a single, real pole, but at the fre-quency of wbw = (KH + 1) ⋅ p. The bandwidth has been extended by KH + 1. This response is unconditionally stable. (Whenever steady-state frequency response (that is, jw-axis response) is related to pole locations in s, it is assumed that a positive value of the real component of the pole location is used for the steady-state frequency. To be precise, wbw = (KH + 1) ⋅ |−p| for real poles. Frequency response involves only positive frequencies, and p > 0 for negative poles, so no confusion should result.) The root-locus plot is shown below.



The open-loop pole at −p moves toward and terminates as the closed-loop pole −(KH + 1)p.

s-p

jw

−(KH + 1)p

Next, consider an amplifi er with two poles:

G sK

s p s p( ) =

+( )⋅ +( )1 21 1

For H constant with frequency, the closed-loop response is

A sKH

KH s KH s KHv

n n

( ) =+

⎛⎝

⎞⎠ ⋅

+( ) + +( ) +11

1 2 1 12 2ω ζ ω

Av is also a quadratic pole response. The closed-loop parameters are

ω ωnc n KH p p KH= ⋅ + = ⋅ ⋅ +( )1 11 2

and

ζ ζωc

ncKHp p=

+= +

1 21 2


88 Chapter 2

For complex poles, both pole angle and magnitude depend on the static loop gain, as did the single-pole response. That is why static loop gain is the param-eter of closed-loop pole movement for root-locus plots. For both fi rst- and second-order loop gain, stability is unconditional. Response can become unac-ceptably underdamped in Av(s) for excessive loop gain, but the poles remain in the left half-plane. The Bode magnitude and root-locus plots are shown for second-order loop gain below.

log w

jω

s

K

p1

(a)

(b)

−p1−p2

p2

⏐⏐ ⏐⏐GH

The Bode plot of ||G|| and ||1/H ||, for the single-pole G and constant H, is shown below.



Because the magnitude axis is logarithmic, the difference between the ||G || and 1/H plots is the loop gain. That is,

log log logG H GH− ( ) =1

These Bode plots are an alternative to calculation and plotting of ||GH || to determine response characteristics. We need only plot ||G|| and 1/H separately and then use 1/H as the unity-gain axis. This applies also for ||H(jw)||. In the above plot, the open- and closed-loop gains intersect at wbw of Av(s). ||Av|| rolls off with ||GH || above this closed-loop bandwidth.

The closed-loop bandwidth can be calculated from the plot. The static gain magnitude of G is K and since 1/H is constant, the difference between them is KH on a Bode plot. The slope of ||G|| due to the pole at p is −1. The w-axis is also logarithmic, a logarithmic frequency difference is a ratio, and wbw/p = KH + 1. The bandwidth is then

ωbw KH p= +( )⋅1

and is the same as for the plot of ||GH|| in the fi rst Bode plot.The fi gures below show some Bode and root-locus plots for circuits with up

to three poles and two zeros. Bode plots show the gain-phase relationship with frequency directly and are most useful for compensating fi xed-gain amplifi ers. Root-locus plots show the closed-loop poles in the s-plane and how these poles vary with loop gain. For circuits with three or more poles, the closed-loop poles can leave the left half-plane with increasing K. The addition of zeros tends to “bend” the loci back from the jw-axis. This effect is a basis for response compensation.

K

log w

log

wbwp

⏐⏐ ⏐⏐G

1H


90 Chapter 2

p z

−z

(a) (b)

(c) (d)

(e) (f)

(g) (h)

(i) (j)

−p

p1 p2 z

z p1 p2

z p

−z−p

−p2

−p2

p3 zp2p1

p3zp2p1

−p3

−p3 −p2 −p1−z

−p3

−z2 −p3−z1 −p2

−p1

−p2

−p1−z−p2 −p1

−p3 −p2 −p1−p1

p1 p2 p3

−z

−z

−p1−z −z−p2 −p1

p1 p2z

p3zp2p1

p3p2

p1 z1 z2



FEEDBACK CIRCUIT STABILITY

Circuits with no RHP poles or zeros are minimum-phase circuits. Most circuits are of this kind. The stability of a minimum-phase circuit can be determined from a Bode plot. When loop gain, G( jw)H( jw) ≤ −1 (or G(−H) ≥ 1), the feedback is in phase with (and thus reinforces) the error input with a loop gain magni-tude ≥ 1, enough to sustain oscillation. In other words, the phase lead or lag around the GH loop is large enough to invert the waveform and to cause it to come back to the input in phase. This is positive feedback. When GH(jw) = −1, then ||GH|| = 1 and f = ±180°. On a Bode plot, when f crosses −180°, stability requires ||GH || < 1. Or, when ||GH|| ≥ 1, −180° < f < 180° for stability. This stabil-ity condition is called the Nyquist criterion.

For minimum-phase circuits, stability can be determined from a Nyquist plot of GH(jw) by observing whether GH encloses the (−1, j0) point. By traversing GH as w goes from 0+ to infi nity, if (−1, j0) remains to the left of the curve, it is not enclosed and the circuit is stable (that is, has no closed-loop RHP poles). The following fi gure shows some examples of non-enclosing curves.

w = 0+−1

w = 0+

w = 0+

b

c

a

Im{GH( jw)}

Re{GH( jw)}

Stability is not as easy to determine for nonminimum-phase circuits – that is, those with right half-plane poles or zeros. Circuits with RHP zeros can be condi-tionally stable within a loop-gain range. For minimum-phase circuits, a decrease in static loop gain K increases the relative stability. But for a conditionally stable circuit, a decrease in gain can decrease stability instead. The reason for this can be seen graphically below.


92 Chapter 2

The plot of GH(jw) extends above f = −180° with a magnitude exceeding unity. As magnitude decreases, the phase reverts to the stable side of −180° (to quadrant III) and skirts around (−1, j0), not enclosing it. The phase again lags beyond −180° at a loop-gain magnitude of less than unity. Because the plot crosses −180° on both sides of −1, too great an increase or decrease of K could cause it to enclose (−1, j0).

−1

w = 0+w = ∝

f

Im{GH}

Re{GH}

⏐⏐ ⏐⏐GH

Encircled,not enclosed

Enclosed,encircled

Im

ReAB

The fi gure above shows a nonminimum-phase circuit polar plot in which GH encircles points A and B but encloses only A. The complete locus is needed to see



the encirclements and includes GH for w = 0− to w = −∞. The negative frequency range locus of GH is symmetric with the positive range locus relative to the real axis. The GH locus in the s-plane closes at infi nity (that is, from w = −∞ to w = +∞) with a counterclockwise path at infi nity, enclosing the stable LHP. The Nyquist criterion must be generalized to include the nonminimum-phase case. The number of RHP poles must be zero for stability; their number is as follows:

number of closed-loop RHP poles = number of poles of GH in RHP − net number of counterclockwise encirclements of (−1, j0) by GH

For nonminimum-phase circuits, stability cannot be determined by enclosure; the Nyquist criterion requires encirclements instead. For stability the net number of CCW encirclements of (−1, j0) must equal the number of positive poles of GH.

Bode plots cover only the positive frequency range of GH and for nonminimum-phase circuits can be misleading. But for minimum-phase cir-cuits, stability and (to some extent) major response characteristics can be readily determined from them. Since most circuits are minimum phase, Bode plots are usually applicable.

Relative stability is measured by gain and phase margins. The gain margin is the difference between one and the gain at f = −180°. The phase margin (PM) is the difference between the phase at a gain of one and −180° and is the amount of additional phase lag that will make the circuit unstable. Although second-order circuits are unconditionally stable, phase margin still describes relative stability whereas gain margin is infi nite. Therefore, phase margin is usually more meaningful in circuits than gain margin.

Gain and phase margins are related to second-order response parameters such as z, Mp, and Mm. As the margins decrease, the closed-loop damping ratio zc decreases, and Mpc and Mmc increase. For second-order feedback circuits with no fi nite zeros, the relationship between PM and zc is approximately

ζ ζc c≅ < < < < °PMPM in deg PM nd-order

1000 0 7 0 64 2, , . , ,


94 Chapter 2

Because overshoot is a function of zc, by combining equations for Mp and pole angle, PM can be expressed in terms of overshoot:

M Mpc pc≅ − > °75 20 2PM in % PM in deg PM nd-order, , , ,

From the Mm equation, Mmc is also a function of zc and can be related similarly to PM. Pole angle is cos−1(zc); a phase margin of 50° corresponds to a pole angle of 60° and an overshoot of 25%. This is greater than the 16% of an open-loop second-order circuit. The exact relationship between PM and zc is found by choosing

G ss s

Hnc c nc

( ) =+( ) =1

21

ω ζ ω,

This choice results in a closed-loop transfer function with only a quadratic pole factor. Solve for the unity-gain crossover frequency wT. Then solve for the phase margin, and substitute wT. The result, in radians, is

PMc c c

= −+ +

⎧⎨⎪

⎩⎪

⎫⎬⎪

⎭⎪−π

ζ ζ ζ21

2 2 4 1

1

2 4tan

Based on this result, the error of PM in the above approximation of zc is calcu-lated to be less than about ±5 degrees. The plot below is this function when converted to units of degrees.

90

70

50

PM

, deg

30

10

0.20 0.4 0.6 0.8 1.0 1.2 zc



Example: Two-Pole Feedback Amplifi er Stability

A feedback amplifi er has two poles in G, none in H, and a closed-loop step response that has 45% overshoot. The static loop gain is 20. What is its phase margin and damping ratio?

The loop gain has only a quadratic pole factor, so the previous formulas apply. (If G has zeros or H has poles, they become zeros of the closed-loop gain, and the quadratic-pole analysis does not apply.) The closed-loop transfer function is similar to Av(s), where KH is the static loop gain. For overshoot, zc is calculated from Mp (or found in the overshoot table) on page 39 and is zc ≅ 0.25. From the prior zc equation, the open-loop z is

ζ ζ= + ⋅ = ⋅( ) =KH c1 21 0 25 1 13. .

z can also be calculated by using the approximations of zc and Mpc with the zc equation:

ζ ≅−( ) ⋅ + =

75100

1 1 37M

KHpc .

This overdamped open-loop response becomes underdamped when the loop is closed. From zc, PM ≅ 100·zc = 25°.

Example: Transimpedance Amplifi er with Input Capacitance

R

G(s)

C

Vo

Ii


96 Chapter 2

This amplifi er consists of a voltage amplifi er with voltage gain G(s). The feed-back blocks are

T RsC

RsRC

HsRC

i = =+

= −+

11

11

,

The closed-loop transimpedance is

Z s T sG s

G s H sR

sRCG s

G s sRC

RG s

m i( ) = ( )⋅ ( )+ ( ) ( )

=+

⋅ ( )− ( ) +( )

= ⋅ ( )1 1 1 1

ssRC G s+ − ( )1

For a single-pole amplifi er,

G sK

s G

( ) = −+τ 1

Then

Z s RK

K s RC K s RC Km

G G

( ) = − ⋅+

⎛⎝

⎞⎠ ⋅

⋅ +( )[ ] + ⋅ +( ) +( )[ ] +11

1 1 12 τ τ

To fi nd PM, because of the zero in G/(1 + GH) due to H, we cannot use the second-order approximations even though Zm(s) has no fi nite zeros. Instead we apply a more general approach using the Bode plot.

For K = 999, R = 1 MΩ, tG = 159 μs (pG = 1 kHz), and C = 5 pF, then at 0 Hz, Zm(0) = −999 kΩ, and the closed-loop poles are at

1 1000 110002

31 8 1000 31 8kHz MHz kHz MHz( )⋅( ) = ( ) = ( )⋅( ) =, . .πRC

These poles are not too close, but the static loop gain is high. The damping ratio is low:



ζcba

= =2

0 092.

1000

100

31.4

10

−45°

−90°

−135°−159°

11 kHz

3.18 kHz 31.8 kHz

178 kHz10 kHz1 kHzf

100 kHz 1 MHz

178 kHz

log f

log f

log⏐⏐GH⏐⏐

From the ideal Bode plot, the PM is about 11°, which is nearly unstable. PM is found as follows. First, fi nd the gain at the higher pole. It is 31.8 kHz/1 kHz = 31.8 times less than the fi rst pole. The gain slope between poles is −1, so the ratio of gains is also 31.8. The open-loop gain at 31.8 kHz is thus 1,000/31.8 = 31.4. The magnitude then decreases at a slope of −2 and crosses unity gain at

fT = ( )⋅ = ( )⋅( ) =31 8 31 4 31 8 5 60 178. . . .kHz kHz kHz

We now know fT and proceed to plot the phase. The phase lags of the two poles overlap. The 1 kHz pole phase range extends from 100 Hz to 10 kHz, and the 31.8 kHz pole range is from 3.18 kHz to 318 kHz. In the overlap (between


98 Chapter 2

3.18 kHz and 10 kHz), the phase slope is twice that due to a single pole. For a single pole, phase changes −90° in two decades for a −45°/dec slope. In the overlap, it is −90°/dec. At the higher pole, f = −135°. To fi nd the additional phase lag to fT, calculate the number of decades and multiply by the phase slope, then add −135°:

log.

17831 8

45 135 169kHzkHz

dec⎛⎝⎜

⎞⎠⎟

⋅ − °( ) − ° = − °

Then PM = −169° − (−180°) = 11°. The result from the exact Bode plot is also 11°.

Most feedback circuits have more than two poles and are capable of instabil-ity. Feedback circuit compensation relies on an intuitive understanding of how pole and zero placement affects stability. Although optimal compensation tech-niques exist, they are rarely the most expedient, cost-effective, or reliable ways to compensate most feedback circuits.

Consider a loop gain with n poles at frequency w = p. The Bode plots of mag-nitude and phase are shown below. The magnitude rolls off at p with a slope of −n. The phase lags by −45°⋅n at p and rolls off at −45°⋅n/dec. The frequency at which the asymptotic approximation for phase crosses −180° is

ωφ = ⋅ −( )p n n10 4

Similarly, for the unity-gain crossover frequency wT of a magnitude with static gain of K,

ωTnp K= ⋅ 1

For stability, wT < wf or wf − wT > 0. Subtracting log wT from log wf yields

log log logω ωφ − = ⋅ ⎛⎝⎜

⎞⎠⎟

>−

T

n

n K1 10

04



As n increases, f rolls off toward −180° faster than ||GH|| does toward one. As this frequency difference approaches zero, the maximum K for stability is approximately

K n< −104

For n = 4, K < 1, which is hardly a useful feedback circuit. If the poles are complex, the situation is worse; f rolls off even faster. Frequency plots for a three-pole circuit are shown in root-locus plot (f) on page 90.

Now consider the effect on stability of separating the poles. For a two-pole Av, zc increases with open-loop z, which can be expressed in p1 and p2 by multiply-ing the factors of G. The coeffi cients yield

ω ζn p pp p

p p= ⋅ = ⋅ +

1 21 2

1 2

12

,

K

1

0

−n

−45°n

−90°n

n = 1

−135°n

−180°n

p w Τ

f wf

log w

log wp/10 10p

(−45°)n/decade

p

log⏐⏐GH ⏐⏐


100 Chapter 2

wn is the geometric mean of the two poles and lies midway between them on a Bode (log w) plot. Relate the poles by a constant g :

p p1 2 0= ⋅ ≥γ γ,

Then

ζ γγ

= +( )12

Minimum z = 1 when g = 1 for real poles. For maximum pole separation of g = 0 or ∞, z = ∞. For the two-pole case, maximum pole separation increases stability.

A root-locus plot of two real poles, maximally separated, shows that they must travel a maximum distance along the real axis before meeting and becoming complex. This can be generalized from inspection of the root-locus plot (f) for three poles. A heuristic stability rule suggested by these obser-vations is

Pole separation increases stability.

COMPENSATION TECHNIQUES

Compensation is often necessitated by circuit imperfections. Parasitic circuit elements, unavoidable reactive input and output loading, and undesirable amplifi er frequency response are the major reasons. Some of these are shown for the following op-amp circuit.

The power supply leads to the op-amp terminals contribute series inductance (L1 and L2). Stray capacitance from the supply terminals to the inputs is signifi -cant if appreciable high-frequency dynamic voltage is present at the supply ter-minals. The op-amp inputs have some internal capacitance to ground, causing a shunt RC with Ri. The op-amp output is an equivalent shunt RL in series with a voltage source. The inductance is due to gain roll-off above the op-amp band-width. (See Chapter 3.) This output impedance can resonate with a capacitive



load. Furthermore, the op-amp usually has several poles. All of this amounts to a “naturally occurring” unstable circuit requiring response compensation.

A clue to compensation comes from studying root-locus plots on which mul-tiple poles cause instability (with suffi cient gain), as shown below. The inclusion of a zero in the loop gain causes poles that would head to the right to be “pulled back” from their course toward the jw axis.

−

−

−

−V

+

+

+

+V

Ri

Rin

Cin

CinLout

CL RL

VoRout

C1

L1

C2

L2

Rf

Vi

p1

(f )

-p3 -p2 -p1

p2 p3


102 Chapter 2

Root-locus rule 6 is intuitively powerful for envisioning where the poles of separate loci will move. They maintain a fi xed centroid on the real axis so that pole movement – say, to the left – is accompanied by corresponding pole move-ment to the right.

−z −p3 −p2 −p1

(g)

p1 p2 p3 z

When a zero terminates the movement of a pole to the left (as in root locus (g), shown above), the poles moving right also cease moving in that direction. Depending on the order of poles and zero, various loci occur but always act according to rule 6 (as seen in root loci (h–j)).

Adding LHP zeros to the loop gain enables the response to be compensated. So another heuristic stability rule is as follows:

LHP zeros tend to increase stability.

−z −p3 −p3 −p1

−p2

−z−p2 −p1

−z2 −p3−z1 −p2

−p1

(g) (h)

(i) (j)

p1 p2 p3z

−z −p2−p3 −p1

p1 p2 p3z p1 z1 z2

p2 p3

p3 zp2p1



Now, consider how to apply these heuristic guidelines more specifi cally as compensation techniques.

1

1 2 3

Pole-zero cancellation

Uncompensatedresponse

4 log m

−4 −3 −2 −1 s

jωlog ⏐⏐ ⏐⏐GH

Pole-zero cancellation places the compensator zero on an offending pole of GH. If the compensator pole is far removed from its zero, then the offending pole is effectively shifted far away. Pole-zero cancellation is demonstrated above.

1

1

2 3

Phase-lead

4

−4 −3

−2.5

−2 −1

Phase-lead compensation places the zero near wf, where f = −180°. This prolongs a stable phase while magnitude continues to roll off toward one. The compensa-tor pole is an implementation side effect that must be put somewhere. Since the zero is placed where phase lead is needed, the pole should be placed at a higher frequency, well beyond wT, where the additional phase lag it contributes will occur beyond where the magnitude crosses one. Phase-lead compensation is demonstrated in the above fi gure. Because phase-lead compensation occurs at high frequencies, it mainly affects the transient response.


104 Chapter 2

Phase-lag compensation places the compensator pole at a lower frequency than the zero. The idea is to introduce the pole at a frequency below the poles of the loop, where the magnitude is fl at. By decreasing the magnitude while the phase lag is still small and then correcting it with a zero, the magnitude is reduced while contributing little phase lag. This technique allows higher static loop gain and consequently smaller steady-state error.

Phase-lag compensation mainly affects low-frequency response error because the compensating pole and zero are placed at low frequencies, relatively near 0 Hz. The step response can have a long-lasting exponential decay (or “tail”) (see pole-zero cancellation above) before settling to the steady-state value. Whenever a low-frequency pole and zero are meant to cancel but are mis-aligned, a dipole is created with a time-domain response showing a long-lasting exponential.

1.5

1

2 3

Phase-lag

4

−4 −3 −2 −1.5 0

Lag-lead

Compensation

1

1

2 3 4 5 7

−7 −6 −5 −4 −3 −2 −1

Lag-lead compensation is a combination of lag and lead compensation, in which two poles and two zeros are introduced into the loop. Both techniques may be required to stabilize amplifi ers with many close poles.



Pole separation can itself be a technique. If the poles are far enough apart, the magnitude, starting from the lower-frequency poles, has enough frequency range to decrease to a gain of one before excessive phase lag accumulates. An important instance of pole separation is dominant-pole compensation, in which one pole is placed at a frequency much lower than the others (and thus dominates the response).

Another pole separation technique is pole-splitting, in which a low-frequency zero is introduced to pull an adjacent pole toward it; all the while the next higher frequency pole increases in frequency. The effect is just the opposite of what is usually expected on a root-locus plot; the poles separate instead of moving toward each other (while satisfying root-locus rules).

One of the simplest of all compensation techniques is static loop gain reduction. This may not be desirable in many applications due to its reduction in the benefi cial effects of feedback. But for circuits with abundant loop gain (as many op-amp circuits have), this can be an effective technique.

Although these techniques are usually suffi cient to achieve desirable response, combinations of them may be necessary for highly unstable amplifi ers. In addi-tion to stabilization of the loop with compensators, stages in GH can be individ-ually compensated. Sometimes a transistor causes an oscillation and must be stabilized before overall loop response can even be considered. Therefore, good design practice is to start with an evaluation of stage responses before consider-ing loop response.

The techniques described in this section have various realizations in analog circuitry. But a technique and its various realizations (and how to design them) are different considerations, just as fi lter types (such as Butterworth, Bessel) have corresponding circuit realizations (such as state-variable, negative imped-ance converter, Sallen-Key). The limitations on circuit topology can affect the choice of technique (bottom-up design) though ideally the nature of the problem determines the best choice of technique (top-down design).

COMPENSATOR DESIGN: COMPENSATING WITH ZEROS IN H

How can zeros be realized in circuitry, and at what frequencies should they be placed? Realizable circuits have no fewer poles than zeros. This complicates compensation because we must be careful where the added poles are placed. If


106 Chapter 2

the pole is less than the zero, the response of (a) below results; if the zero is less than the pole, (b) results.

p

(a) (b)

z pz

−z −p −z−p

Some passive compensator circuit realizations are shown below.

Vi

Phase-lead

(a)

(b)

(c)

Phase-lag

Lag-lead

−p

−p2 −z2 −z1 −p1

jw

−z s

+

−

+

−

R1

z = 1/R1C

R2

VoC

−z

jw

−p s

jw

s

p = 1/(R1 R2)C⏐⏐

Vi

+

−

+

−

R1

C1R2

C2

Vo

Vi

+

−

+

−

R1

z = 1/R2C

R2

C

Vo

p = 1/(R1 + R2)C

z1 = 1/R2C2z2 = 1/R1C1p1 << p2



For the phase-lead (a) and phase-lag (b) compensators, the separation of pole and zero depends on the ratio of R2 to R1 + R2. For effective compensation, this separation must be signifi cant; therefore, the values of R1 and R2 must be sig-nifi cantly different. The lag-lead compensator of (c) has transfer function

T ssR C sR C

s R C R C s R C R C R C( ) = +( )⋅ +( )

⋅ + ⋅ + +( ) +1 1 2 2

21 1 2 2 1 1 1 2 2 2

1 11

From (c), the conditions on pole and zero placement are

p z z p1 1 2 2< << <

and R1C1 << R2C2. The wide separation of these critical frequencies is desirable. By choosing the separation of the zeros, we can determine the pole and zero pair separations. A trade-off between these separations must be based on the particular amplifi er requirements.

Ci

Rf

(a)

(b)

Cf

Vo

Ri−

+

−

+

Vi

−

+

−

+

Vi

Ci Ri

Cf

Rf

Vo


108 Chapter 2

These are not the only compensator realizations. The uncompensated ampli-fi er topology affects choice of design, especially if the compensator can be syn-thesized from part of the given topology. What follows are particular amplifi er compensation techniques.

The op-amp shown above has one op-amp pole p in G(s). Another pole is due to the input capacitance Ci. If the poles are too close, compensation might be needed. Inserting a phase-lead compensator in cascade with either the input or output of the op-amp is undesirable because it decreases input resistance or increases output resistance. Because H consists of a voltage divider, it can be modifi ed to form a phase-lead compensator. The topology of H is familiar; it is an uncompensated voltage divider. A compensation capacitor Cf is placed in parallel with Rf. Then

HR

R RsR C

s R R C Ci

f i

f f

f i f i

= −+

⎛⎝⎜

⎞⎠⎟

⋅+

( )⋅ +( ) +1

1

H is equivalent to the compensated divider formula. If the pole is set to equal the zero, H becomes an all-pass network, and the pole due to Ci is cancelled. In this case,

CRR

Cfi

fi=

⎛⎝⎜

⎞⎠⎟

⋅

Example: Op-Amp Input Capacitance Compensation

The amplifi ers of (a) and (b) above have values of Ri = 47 kΩ, Rf = 220 kΩ, Ci = 100 pF, K = 100 k, and p = 10 Hz. The uncompensated loop has an op-amp pole at 10 Hz and a pole due to Ci at 1/(220 kΩ || 47 kΩ)(100 pF) or 41.1 kHz.



From the simulated open-loop Bode plot of GH, shown below, fT ≅ 80 kHz and PM ≅ 26°.

84.867

43.334

1.80000

Mag

nitu

de, d

B

Pha

se, l

og

−39.733 −110.27

−179.98

−154−146.12

−75.414

−40.560

−5.7066

−81.288

−122.801.0000 100.00 10000.0

Frequency, Hz+1.00E + 0.6

(zc or Mpc cannot be applied here because H has a pole. Poles of H become zeros of the closed-loop gain.) The closed-loop frequency response is shown below.

28.413 27.934

4.3472

−19.240

−42.826

−66.413

−90.000

14.732

1.0513

−12.630

−26.311

−39.992

Mag

nitu

de, d

B

Pha

se, d

e g

1.0000 100.00 10000.0Frequency, Hz

+1.00E + 0.6


110 Chapter 2

The closed-loop step response is also simulated, as shown below.

6.2444

5.8654

5.4865

Am

plit

ude,

V

5.1076

4.7286

4.34970.0000 +2.00E−05 +4.00E−05

Time, s

+6.00E−05

The addition of Cf creates a zero at 1/(220 kΩ)⋅Cf. According to the design formula, Cf = 22 pF. The compensated response has a single pole at 10 Hz, with a phase lag approaching −90° and a 90° PM.

10 Hz

log ⏐⏐ ⏐⏐GH

100 Hz

57 Hz

1 kHz 100 kHzlog f

p comp.

pH comp.

10 kHz

We could have chosen to cancel p with the zero instead. If p were cancelled, Cf would be 72.3 nF, and the magnitude plot would be fl at to the compensator pole, now at only 56.8 Hz, with single-pole roll-off from this pole. This alternative pro-vides greater loop bandwidth. For the inverting op-amp, the larger Cf causes a lower-frequency pole in Ti, reducing closed-loop bandwidth considerably.

The maximum amount of phase lead that a phase-lead compensator intro-duces into a loop depends on the separation of its pole and zero. From the asymptotic approximation for phase, both pole and zero linearly affect phase for one decade on each side of them. If they are separated by two decades, the zero achieves a full 90° of phase lead before the pole begins to take effect. Consequently, maximum phase lead equals



45 1 100

90 100

°( )⋅ ⎛⎝

⎞⎠ ≤ ⎛

⎝⎞⎠ ≤

° ⎛⎝

⎞⎠ >

⎧

⎨⎪⎪

⎩⎪⎪

log ,

,

pz

pz

pz

The frequency of maximum phase lead is at p z⋅ or about p/10, where the pole begins to cancel the effect of the zero. The frequency range over which phase-lead compensation occurs is

log ,

,

p z p z

p z( ) ≤ ≤

>⎧⎨⎩

dec

dec

1 100

2 100

Example: Op-Amp Phase-Lead Compensation

Vi

Rf

Cf

10 kΩ

1 kΩ Vo

Ri

−

−

++

A fast op-amp has a gain of 2.2 M and poles at 100 Hz and 1 MHz.

105.98 −5.7051

−40.449

−75.194

−109.94

−144.68

−179.43

73.987

41.998

10.009

−21.981

−53.970

Mag

nitu

de, d

B

Pha

se, d

eg

10.000 1000.0Frequency, Hz

+1.00E + 07+1.00E + 05


112 Chapter 2

The above Bode plot of GH (without Cf) shows that phase lag approaches −180°, causing oscillatory response. Cf is introduced to phase-lead compensate the loop. The closed-loop response is shown below.

33.624 −1.4489

−36.909

−72.370

−107.83

−143.29

−178.75

22.962

12.300

1.6374

−9.0249

−19.687

Mag

nitu

de, d

B

Pha

se, d

eg

Frequency, Hz+1.00E + 07+1.00E + 06

Bode plot gain at the second pole frequency and the unity-gain frequency fT are of interest. On a log-log plot, a line with slope n relates changes in magni-tude and frequency according to

yy

ff

n2

1

2

1

⎛⎝⎜

⎞⎠⎟

= ⎛⎝⎜

⎞⎠⎟

The loop gain is 2.2 M/11 = 200 k. The pole separation of p1 and p2 is 1 MHz /100 Hz or 4 decades. With a negative slope, the loop gain is reduced over 4 decades at p2, to 200 k/104 = 20. For fT, the slope is −2 and

fT = ( )⋅ ≅1 20 1 4 47MHz MHz.

The phase plot (dashed curve) shows a phase lag of −169° at fT, and PM = 11°. At p2, the phase lag is −135°, and the phase rolls off at −45°/dec. At 4.47 MHz, then over



log . .4 47 1 0 65MHz MHz dec( ) =

this results in an additional 29°, or a total of −164°. This linear approximation is +5° in error. The phase plot value results in z ≅ 0.11, a pole angle of about 84°, and a step-response overshoot Mp, of 71%. This response is too under-damped for many applications.

The maximum phase lead that can be introduced is

45 45 45 1°( )⋅ ⎛⎝

⎞⎠ = °( ) ( )⎡

⎣⎢

⎤

⎦⎥ = °( )⋅ +log log log

pz

R R CR C

RR

f i f

f f

f

i

⎛⎛⎝⎜

⎞⎠⎟

or (45°)(log 11) ≅ 47°. The phase lead of the zero occurs over a frequency range of log (11) ≅ 1.04 dec. If the high end of this range is placed at the compensated fT, or fTc, then phase lag is held constant from fTc/(p/z) to fTc. This placement of phase-lead range is accomplished by noting that p begins to affect phase at p/10. So we set

fp

zf

p zTc

Tc= = ⋅( )10

10,

An increase in z from this placement fails to use the full range of phase lead. A decrease in z increases fTc until the break to a −2 slope occurs at fTc.

z decreasing

log w

fTc2

fTc1fTz2 z3

log⏐⏐ ⏐⏐GH


114 Chapter 2

Then fTc remains fi xed as z continues to decrease. When a decreasing z increases fTc, the magnitude slope at fTc is −1, and phase is decreasing. For maximum PM, phase should begin to decrease again at fTc. The phase-lead range is then placed with the high end at fTc.

We still must relate fTc to the uncompensated plot. At z the two plots roll off at their respective slopes to fT and fTc. Because their gain change is the same, their locations depend on the slope differences. Consequently, using the slope equation results in

fz

fz

f f zTc TT Tc

⎛⎝

⎞⎠ = ⎛

⎝⎞⎠ ⇒ = ⋅

− −1 2

Combining with the fTc equation,

fp z

z fp z

p fpz

T T T= ⋅ = ⋅ = ⋅ ⋅⎛⎝⎞⎠10

1010, ,

For the example, fT = 4.47 MHz and p/z = 11. Then

z p z fp

Tc= = ⋅ = = =4 26 11 46 910

4 69. , . , .MHz MHz MHz

At z/10 = 426 kHz, the phase is

log4261

45 135 118kHz

MHz⎛⎝⎜

⎞⎠⎟

⋅ °( ) − ° = − °

This is an improvement of about 46° (as calculated from the maximum-phase equation) over the uncompensated amplifi er. The compensated PM ≅ 57°.

Phase-lag compensation of the amplifi ers in (a) and (b) above can be imple-mented in H by connecting a series RC between the op-amp input terminals, as shown below.



Ci

Rf

Rc

Rc

Cc

Cc

(a)

(b)

Vo

Vo

Ri−

+

−

+

Vi

−

+

−

+

Vi

Ri Ci

Rf

Given an op-amp with dominant pole at p in G(s), then

H sR

R RsR C

s R C R C s R C C R Ci

f i

c c

c c p i p c i c c

( ) = −+

⎛⎝⎜

⎞⎠⎟

⋅ +[ ] + +( ) +[ ] +

12 11

where Rp = Rf ||Ri. For Rc << Rp and Cc >> (Rp/Rc)·Ci,

H sR

R RsR C

sR C sR Ci

f i

c c

p c c i

( ) ≅ −+

⎛⎝⎜

⎞⎠⎟

⋅ ++( )⋅ +( )

11 1

The effect of this compensation is to add a pole and zero. Because Rc << Rp, the pole frequency, 1/Rp ⋅ Cc, is less than the zero frequency, 1/Rc ⋅ Cc. For Cc >> (Rp/Rc)·Ci, this zero is less than the second pole, 1/Rc ⋅ Ci. This results in a pole and zero ordering of

pR C R C R C R Cp c c c p i c i

< < < <1 1 1 1


116 Chapter 2

The effect of the compensation network is shown below, which demonstrates phase-lag compensation.

log w1pCR

pc

1c CR c

1c CR

Uncompensatedresponse

i−1

−2

−2

−1

1p CR i

log⏐⏐ ⏐⏐GH

Above 1/Rp ⋅ Cc, the magnitude decreases at a steeper slope at small phase angles. Then, as w approaches a gain of one, the zero is introduced (at 1/Rc ⋅ Cc) to reduce the phase-angle slope and to increase phase margin. The root-locus plot is shown below.

cR cC–1

pR iC–1

pR cC–1 –p

ω

σ

j

Another way to add a zero to H when a feedback capacitor is used for compensation is to add a resistor in series with it. The effect of this Rc is to add a zero at 1/Rc ⋅ Cc and to move the pole at 1/Rf ⋅ Cc down in frequency to 1/(Rf + Rc) ⋅ Cc.



Example: Phase-Lag Compensation

–

+

R

Vo

iV

+

–

i

Rc

Cc

Rf

10 k Ω1 k Ω

We want to phase-lag compensate the amplifi er for maximum PM. The op-amp has poles at p1 = 100 kHz and p2 = 1 MHz and a static gain of 2200. A phase-lag compensator is realized by adding a series RC from the inverting input of the op-amp to ground with elements Rc and Cc. Then

H sR

R Rs R C

s R R R Ci

f i

c c

c f i c

( ) = −+

⎛⎝⎜

⎞⎠⎟

⋅ ⋅ +⋅ + ( )[ ]⋅ +

11

Substituting values, H(0) = 1/11 = 0.0909 and GH(0) = 200. To achieve as much PM as possible, the pole and zero of H must be widely separated. The ratio of the H zero to pole is

zp

R RRf i

c

= +1

and is large when Rc << Rf ||Ri. Rf and Ri are given, allowing us to both place and separate z and p by selecting Rc and Cc. If the high end of the phase range of z is placed two decades below p1, then phase is restored to zero at p1/10, but the gain will have rolled off by a decade to 20. By placing z at 1 kHz, RcCc = 159 μs. For a full 90° of phase lag, z/p = 100. Substituting into the above equation gives Rc = 91.8 Ω. The closest 5% resistor value is 9.1 Ω. Cc is 159 μs/9.18 Ω = 17 μF, or a 5% tolerance value of 18 μF.


118 Chapter 2

Estimate the compensated PM as follows. The gain at p1 is 20, and f must be −45°. The gain rolls off another decade to p2, where it is 2. Then

fTc = ⋅( ) =2 1 1 41MHz MHz.

This is log (1.41), or 0.15, decades above p2. At p2, f = −90°. At −90°/dec, the additional phase lag at fTc is 59° or −149° total, and the PM = 31°.

Example: Transimpedance Amplifi er with Input Capacitance (continued)

In the transimpedance amplifi er circuit on page 95, z was unacceptably low. We can apply phase-lead compensation in H by shunting R with a compensation capacitor Cc.

The open-loop poles are at frequencies of 1/R ⋅C and 1/tG = pG. The addition of Cc shifts the pole in H to pH = 1/R ⋅ (C + Cc) and adds a zero at z = 1/R ⋅ Cc. With phase-lead compensation, z < pH. The root locus plot is shown in (c) on page 90. The complex pole locus bends left in a circle and rejoins the real axis above the zero. Because the static loop gain is given, pole placement for the desired response largely depends on the placement of z.

The addition of Cc results in a closed-loop transimpedance of

VI

KK

sR C Cs R C C K s K RC K

o

i

c

G c G

= −+

⎛⎝

⎞⎠ ⋅ +( ) +

+( ) +( )[ ] + +( ) + +11

1 1 12 τ τ (( ) +[ ] +RCc 1

The closed-loop z of the poles is derived as

ζ ττc

G c

G c

ba

RC K RCR C C K

= = ⋅ +( ) +( ) ++( ) +( )2

12

11

For a maximally fl at envelope or group delay (MFED) pole placement, ζc = 3 2 . Substituting into zc and solving for Cc it is 2.3 pF.

COMPENSATOR DESIGN: REDUCING STATIC LOOP GAIN

Phase-lag compensation reduces loop gain except at low frequencies. The simpler technique of reducing K does not require a compensation capacitor,



Cc, and does not appreciably degrade static performance for amplifi ers (such as op-amps) with high loop gains. Neither does it introduce compensation poles and zeros that must be readjusted when closed-loop gain is adjusted. The Bode magnitude plot is shifted downward. With Cc shorted, Av of the inverting op-amp, shown on the next page in (a), is not affected by Rc but the loop gain is. The inverting op-amp has input attenuation Ti = 1 + H; both Ti and H are affected by Rc such that Av remains unchanged. Consequently, GH can be adjusted by adjusting H with Rc without affecting closed-loop gain.

The noninverting op-amp confi guration can also be compensated by Rc. To achieve the same result, Rc must be placed across the op-amp inputs in (b). The fl ow graph for this topology has a transmittance of Ti in front of the feedback loop. The feedback equations are

V K E E T V H V V Vo i i o i= ⋅ = ⋅ − ⋅ = − −,

The transmittances are

TR

R R Ri

c

i f c

=+

HR R

R R Rc i

c i f

=+

G K=

Combining these equations yields the closed-loop gain

AR R

RK K R RR R R K

R RR

vf i

i

c i

c i f

f i

i

=+⎛

⎝⎜⎞⎠⎟ ⋅ +( )[ ]⋅[ ]

+ +( )=

+⎛⎝⎜

⎞⎠⎟

11 KK →∞

This is the familiar noninverting op-amp gain formula when K → ∞. Av is not affected by Rc, but the loop gain is. Because GH = KH, the effect on loop gain is to attenuate H by Rc shunting Ri. An apparent disadvantage of this topology is that Rc reduces the input resistance. But the effect is minimal with large K because Rc is across E, a small voltage, and is bootstrapped.


120 Chapter 2

Ri and Rf can be generalized to impedances. The frequency-dependent closed-loop gain is unaffected by Rc whereas the static loop gain is reduced. This shifts the Bode magnitude plot downward, causing it to cross a gain of one at a lower frequency, where the phase lag is less.

COMPENSATOR DESIGN: POLE SEPARATION AND PARAMETER VARIATION

One of the simplest compensation techniques is pole separation by dominant-pole compensation. If one pole is introduced into a feedback loop at a much lower frequency than the other loop poles, it causes the gain to roll off at −20 dB/dec (−1 slope) over a large frequency range until the next pole is encountered. If the range is large enough, the unity-gain frequency is less than the remaining poles, so that their infl uence is inconsequential. An existing pole can often be reduced in frequency by modifying the value of its associated circuit elements.

Vo

(a)

(b)

Vi

Rc

RiRf

E−+

Vo

Vi

Ri

Rc

Rf

E −

++

−



Another pole separation technique, pole-splitting, is commonly applied by placing a capacitor from input to output across an inverting amplifi er stage with a dominant pole. The diagram above shows a feedback amplifi er with dominant forward-path pole at −pG and a transfer function of

G Ks pG

= − ⋅+

11

The feedback path is that of an RC differentiator. The resulting loop gain is

GHK

s psRC

sRCG

=+

⋅+1 1

The closed-loop root locus is plotted below.

Vi

Vo

R

C

−

+

−Ks/pG + 1

s

jw

−pG−1RC


122 Chapter 2

Because of the zero at the origin, the pole at −pG migrates to the right while the pole at −1/RC increases in frequency. This is pole-splitting. The poles split apart instead of coming together and thereby achieve pole separation. The closed-loop transfer function is

V sV s

Ks RC p s K RC p

o

i G G

( )( )

= − ⋅ ( ) + +( ) +[ ] +1

1 1 12

Because of the Miller effect, evident in the linear term of the denominator, the integrator pole moves away from pG as K increases, separating the poles.

−Gm

Ii

Vi

Zf

Vo

Zi ZL

To analyze the shunt capacitive realization of pole-splitting in more detail, the fi gure above shows an inverting amplifi er stage with its fl ow graph, shown below.

Zi Zf

Zf ZL

Ii Vo

Vi

G1 −Rm=

ZLG2 Zf + ZL=

ZiZf + Zi

⏐⏐

⏐⏐

The active forward path is a transadmittance amplifi er with a gain of −Gm = −1/Rm < 0. The input and output are both loaded by generalized impedances



Zi and ZL, and the transadmittance amplifi er is shunted by a feedback imped-ance Zf. From the fl ow graph, the closed-loop transimpedance is

VI

Z ZZ Z Z R

Z Z Z R Z Z Zo

if i

f L f m

f L f m i f i

= ( )⋅ ( ) −( )+ ( ) −( )[ ]⋅ +( )[ ]1

and Zin is

Z ZZ

Gin i

f=−1

For the simpler case of no loading, Zi and ZL are removed, and the transimped-ance is

VI

Z Ro

i Z Zf m

i L, →∞

= − +

Because the output quantity is a voltage, a low-impedance output is desirable (to approximate a voltage source). In this case, ZL << Zf, and G2, the passive path in G, is negligible. Then

GZ Z

RZR

f L

m

L

m1 =

−≅

−

and

G HZR

ZZ Z

L

m

i

f i1 = ⎛

⎝⎜⎞⎠⎟ ⋅

+⎛⎝⎜

⎞⎠⎟

To make the circuit more specifi c, let ZL contribute a single pole due to a parallel RC load:

ZR

sR CL

L

L L

=+ 1


124 Chapter 2

Similarly, let the input loading of the Gm amplifi er be a parallel RC:

ZR

sR Ci

i

i i

=+ 1

and let the feedback impedance be a capacitance:

ZsC

ff

= 1

These choices of impedances simulate a common-emitter (CE) (or common-source [CS]) stage with collector-base (or drain-gate) capacitance. Substituting these impedance expressions,

G HRR

sR CsR C C sR C

L

m

i f

i f i L L1

1 1= ⋅

+( ) +[ ]⋅ +( )

The frequency response and root loci are plotted below.

log w

jw

s

−1Ri (Cf + Ci)

−1RL CL

−1Ri (Cf + Ci)

−1RL CL

log⏐⏐ ⏐⏐G1H



The zero at the origin splits the poles. Because the zero is not positive, there is no danger of instability with too much static loop gain, Gm. As gain increases, however, the lower-frequency pole decreases in frequency, and the bandwidth is correspondingly decreased.

The above assumed that G2, the passive forward path through Zf, was negligi-ble. If we extend this analysis to include it, we get some interesting and impor-tant results. The complete G is

G G GZ Z

RZ

Z ZZ Z

Z Rf L

m

L

f L

f L

f m

= + = − ++

=−1 2

Specifi cally, G1 and G2 are

GRR sR C C

L

m L f L1

11

= − ⋅⋅ +( ) +

GZ

Z ZsR C

sR C CL

f L

L f

L f L2

1=

+=

⋅ +( ) +

Then G becomes

GRR

sR CsR C C

L

m

m f

L f L

= − ⋅− +⋅ +( ) +

11

This more complete expression for G has an additional RHP zero at +1/Rm⋅Cf. The loop gain is

GHRR

sR C sR CsR C C sR C C

L

m

m f i f

L f L i f i

= ⋅− +( )⋅( )+( ) +[ ]⋅ +( ) +[ ]

11 1

The root locus of GH is not directly obtainable as before because the RHP zero varies with Rm, and RL/Rm is the static loop gain. Root-locus plotting is based on fi xed open-loop poles and zeros that are independent of static gain. In GH, both elements that affect static loop gain also affect a pole and zero. This sug-gests limits on the applicability of the root-locus technique.


126 Chapter 2

Consequently, we proceed directly to the closed-loop voltage gain Vo/Vi:

VV

RR

sR C sR C Cs a sb

o

i

L

m

m f i f i= − ⋅− +( )⋅ +( ) +[ ]

+ +1 1

12

where

a R R C C C C C Ci L i f L f i L= ⋅ + +( )

b R CRR

R C R C R Ci fL

mi i L f L L= ⋅ +⎛

⎝⎜⎞⎠⎟ + + +1

Finally, the closed-loop transimpedance is

VI

Z ZVV

Z HVV

RRR

sR Cs a sb

o

if i

o

if

o

ii

L

m

m f= ⋅ = −( )⋅ = − ⋅− +

+ +.

112

This expression has two LHP poles and one RHP zero. Its characteristic equa-tion is the same as the voltage gain equation.

The Miller effect is evident in the linear coeffi cient b in the fi rst term, where the Miller capacitance Cf is multiplied by the static voltage gain plus 1. As Rm decreases, b increases while a remains constant. This causes the poles to move apart with decreasing Rm. It also causes the RHP zero to increase in frequency. The LHP zero of Vo/Vi remains fi xed as Rm varies. The movement of its poles and zero with decreasing Rm (or increasing Gm) is shown below. The poles move to zero and −∞; the RHP zero goes to +∞.

−1Ri (Cf + Ci)

Rm

∞−p2 −p1

0

Rm Cf

jw

s+1



A root-locus plot with a circuit element as parameter is a root contour plot. If KGH can be reformulated as X⋅F(s), where F(s) is independent of X, then X is a constant relative to F and can be varied in the root-locus equation, KGH = XF = −1. The root-locus rules then apply, and the pole loci are mapped as a parameter of X. If a formulation compatible with the root-locus technique is not feasible, then movement of the poles and zeros of the closed-loop transfer function with variation of a circuit element can still be investigated. The result-ing closed-loop parameter variation technique is often quite useful in determining the effect of a circuit element on the dynamic response.

If Cf is made the parameter instead of Rm, the movement of the poles with Cf can be plotted. As Cf increases in Vo/Ii, the RHP zero decreases toward zero. For the poles, Cf is in both a and b. We can estimate pole location from extreme values of Cf. When Cf = 0, the poles are located at −1/Ri⋅Ci and −1/RL⋅CL. These are also the open-loop poles for Cf = 0. As Cf increases slightly from zero, the poles will decrease until Cf dominates (that is, Cf >> Ci, CL). Then the quadratic pole factor becomes

s C R R C C sC RRR

Rf i L i L f iL

mL

2 1 1⋅ ⋅ +( )[ ] + ⋅ ⋅ +⎛⎝⎜

⎞⎠⎟ +⎛

⎝⎜⎞⎠⎟ +

In solving for the poles, we fi nd that the b/2a term is independent of Cf. Also the (Ci + CL) factor in a is not found in b. If it is varied (as long as Cf continues to dominate), the pole loci will move together and form a complex circular arc centered at the origin. (See “Loci of Quadratic Poles” for a description of root loci due to parameter variation.)

As Cf → ∞ in Vo/Ii, both poles and zero move toward the origin. One pole and the RHP zero reach the origin and cancel, leaving a single pole at

−( )⋅ +( )

1R R R C CL i m i L

An infi nite Cf is a short between input and output such that Vo = Vi. The substi-tution theorem applies to the transadmittance current source, transforming it into a resistance across Vi of value Rm. All circuit components are in parallel.


128 Chapter 2

Therefore, a very large Cf couples input and output so that their separate poles are effectively merged into one.

From the open-loop gain, GH, if CL >> Cf, then Cf has negligible effect on the open-loop pole at −1/RL(Cf + CL); it remains relatively fi xed as Cf increases. For the other open-loop pole, if Ci is not much greater than Cf, it moves appreciably to the right. Under these conditions, variation in Cf causes pole separation.

Now analyze the closed-loop transimpedance of this amplifi er for other choices of circuit impedances. Consider new circuit conditions, in which Zi is removed and the load is only capacitive:

ZsC

Z ZsC

LL

i ff

= → ∞ =1 1, ,

Then

VI sC

sR CsR C

o

i f

m f

m L

= ⋅− +

+1 1

1

G has the RHP zero and a pole at the origin with coeffi cient Rm(Cf + CL). H = −1 and GH = −G. As Rm decreases, closed-loop pole and zero separate.

−1RmCL RmCf

ZL = 1/sCL

jw

s+1



The pole and zero can be adjusted independently by varying CL or Cf, respectively.

If a resistive Zi is added, the modifi ed conditions are

ZsC

Z R ZsC

LL

i i ff

= = =1 1, ,

Then

GsR C

sR C Cm f

m f L

= −− +

+( )1

andH

RsC R

sR CsR C

i

f i

i f

i f

= −+

= −+1 1


VI

RR C C R C

sR Cs s R C C R C

o

i

i

m f L i f

m f

i f L m L

= −+( ) +

⋅− +

⋅ ⋅ ( )[ ]( ) +( )1

1

The closed-loop poles and zero are plotted below.

1Rm Cf

ZL = 1/sCLZi = Ri

jw

−1 s[Ri (Cf RmCLCL)]⏐⏐ ⏐⏐

The static factor, a pole, and the RHP zero vary with decreasing Rm. Again, pole and zero move outward, away from the origin. This circuit behaves as an integra-tor due to the fi xed pole at the origin. The effect of adding Ri is only to shift the non-zero pole.


130 Chapter 2

Ri is now removed and RL added. The conditions are

Z RsC

RsR C

Z ZsC

L LL

L

L Li f

f

= =+

→ ∞ =11

1, ,

For these conditions, H = −1 and the open-loop gain is

GHRR

sR CsR C C

L

m

m f

L f L

= ⋅− +

+( ) +1

1


VI

RR R sC

sR Cs R R C

o

i

L

L m f

m f

m L L

= −+

⎛⎝⎜

⎞⎠⎟

⋅ ⋅− +

( )⋅ +1 1

1

Again, the s-plane plot is similar to the previous two cases, with the pole location modifi ed due to RL.

1Rm Cf

jw

s−1

(Rm RL)CL⏐⏐

ZL = RL 1/sCL⏐⏐

Finally, consider the addition of a resistive Ri to the circuit of the above trans-conductance equation. The conditions are then

Z RsC

RsR C

Z R ZsC

L LL

L

L Li i f

f

= =+

= =11

1, ,




VI

RRR

sR Cs R R C C s R C C R C R R

o

ii

L

m

m f

L i L f L f L i f L m

= − ⋅ ⋅− +

( ) + +( ) + +( )1

12 [[ ] + 1

The effect of resistances at both input and output is to move the low-frequency pole off the origin. The circuit no longer behaves as a pure integrator.

1Rm Cf

jw

s

ZL = RL 1/sCL⏐⏐Zi = Ri

−p2 −p1

When Rm decreases, the poles split in the usual way; one goes to the origin and the other to −∞. Again, this locus of poles is due to variation in the linear-term coeffi cient of the denominator of Vo/Ii. The quadratic coeffi cient remains constant with Rm.

This extended analysis of the generic transconductance amplifi er demon-strates the conditions for pole-splitting due to variation in static loop gain Gm and in Cf. The limitation of the root-locus technique was largely overcome by closed-loop parameter variation. This circuit is representative of CE and CS amplifi ers and wideband amplifi ers in general.

Example: Transimpedance Amplifi er Pole-Splitting

Vo

Ci

Cf

Ri

Rm

CLRL

−1

Ii


132 Chapter 2

This amplifi er is an idealized form of inverting transistor amplifi er with a feed-back capacitance. Let

R R R C C CL m i f i L= = = = = =1 100 10 10 10 90k k pF pF pFΩ Ω Ω, , , , ,

From Vo/Ii, solve for the zero and poles. They are

z p= =159 124 10 81 2MHz kHz MHz, , .,

The Bode plot confi rms the pole and zero values.

Frequency

0

200

150

100

50

0

−50

−100

−20

−40

−60

Mag

nitu

de, d

BP

hase

, deg

−80

−100

−12010 kHz 100 kHz 1.0 MHz 10 MHz 100 MHz 1.0 GHz

Frequency

10 kHz 100 kHz 1.0 MHz 10 MHz 100 MHz 1.0 GHz



As b remains constant with Rm, the poles should move toward each other as Rm is increased. Calculating again for Rm = 1 kΩ,

z p= =15 9 461 2 891 2. , , .,MHz kHz MHz

As predicted, the poles are now closer. With a further increase in Rm, they will eventually become complex.

TWO-POLE COMPENSATION

High-performance feedback amplifi ers require high loop gain over a wide fre-quency range. Dominant-pole (single-pole) compensation reduces gain appre-ciably at higher frequencies because the pole must be placed at a relatively low frequency to decrease loop gain to one at a desirable phase margin. The time response might then be acceptable, but the side effect is that, except at low frequencies, the loop gain rolls off, and high-frequency amplifi er perfor-mance suffers. The benefi ts of feedback are retained by keeping the loop gain high over the frequency range of interest. If loop gain is too low at higher fre-quencies, then distortion (or nonlinearity) is high and noise rejection low. For an analog-to-digital converter (ADC) interface, bits of accuracy and signal-to-noise ratio (SNR) will be lost at higher frequencies, and for the audiophile, the cymbals will sound “tinny.”

The two-pole compensation technique sustains high gain to a higher break fre-quency, where it then rolls off at −40 dB/dec (−2 slope) followed by a zero that restores the magnitude to that of dominant-pole compensation. The difference from dominant-single-pole compensation is shown below.

The high loop gain is extended from the dominant-pole break frequency at pd to p, where two poles reside. The gain then decreases with a −2 slope to z, the frequency of the zero. Above z, the response follows the dominant-pole response, with a −1 slope. The zero restores the phase margin lost by the additional pole.


134 Chapter 2

The above Bode plot can be expressed algebraically by the generic voltage-gain transfer function:

VV

s zas bs

s zs p

s z

ss

o

i

n n

= ++ +

= ++( )

= +⎛⎝⎜

⎞⎠⎟ + ⋅⎛

⎝⎜⎞⎠⎟ ⋅

11

11

122 2 2

ωζ

ω++ 1

where wn is the pole radius and z is the damping ratio. For z = 1, the pole pair is critically damped and the two poles are equal, at p. The pole angle is cos−1(z) for z ≤ 1. We will assume identical, real poles for now.

Two-Pole Compensator Circuit

A two-pole compensation circuit is shown below. For the ideal op-amp, static (dc) gain, K, is infi nite, and the compensation poles reside at the origin – a dominant-pole amplifi er. In a typical feedback amplifi er loop, however, K can be fi nite. From the Bode plot above, as frequency increases, the reactance of the capacitors decreases relative to R until XC << R. Then the equivalent circuit consists of the two capacitors in series, shunting the op-amp. The series capacitance forms an op-amp integrator with a dominant-pole response. The zero of the circuit is located at the frequency for which R becomes negligible relative to XC. At the zero, the frequency response breaks from a slope of −2 to −1.

-1

-2

pd p z log w

Dominant-polecompensation

Two-polecompensation

K

log⏐ ⏐⏐Av



The above circuit has a loop gain of

GH Ks RR C C

s RR C C s RC RC R Ci

i i

= ⋅+ + +( ) +

21 2

21 2 1 2 2 1

where G = −K.The closed-loop voltage gain includes a preloop transfer function of

T RsR C C

s RR C C s RC RC R Ci i

i i

= ⋅ +( ) ++ + +( ) +

1 22

1 2 1 2 2

11

and is

VV

TGGH

KsR C C

s RR C C K s RC RC R Co

ii

i i

= ⋅+

= − ⋅ +( ) ++( ) + + +( )1

11

1 22

1 2 1 2 2 ++ 1

where Vi = RiIi. For an ideal op-amp, K → ∞, and the voltage gain becomes

VV

sR C Cs RR C C

o

i K i→∞

= − +( ) +1 22

1 2

1

As K increases, the quadratic term in the closed-loop voltage gain dominates, shifting the poles to the origin. This results in loop-gain rolloff from 0 Hz,

Vo−K

Ri

Vi

R

Ii

C1C2


136 Chapter 2

defeating the two-pole compensator. Consequently, the above circuit can be used as a two-pole compensator under the condition that K remain fi nite. The two-pole compensator, with its poles far removed from the origin, cannot use the open-loop gain of an op-amp for G.

Another simplifi cation of the circuit is to let Ri → ∞. This is the case of a transimpedance amplifi er with input Ii. Its transresistance is

VI

KsR C C

sC s K RCo

i Ri →∞

= − +( ) ++( ) +[ ]

1 2

2 1

11 1

The pole dependent on Ri moves to the origin. Without a fi nite Ri, the poles cannot be equal and two-pole compensation is not realized under this condition either.

For an op-amp transimpedance amplifi er, both Ri and K → ∞. In this case,

VV

sR C Cs R C C

o

i R Ki , →∞

= − ⋅ +( ) +⋅ ⋅

1 22

1 2

1

This amplifi er behaves as a dual integrator with a fi nite zero. For the special case of C1 = C2 = C:

VV

s R Cs R C

o

i R K C C Ci , ,→∞ = =

= − ⋅ ⋅ ⋅ +⋅

1 2

2 12 2

As R → ∞, Vo/Vi becomes

VV

KsR C C K

o

i R i→∞

= − ⋅ ( )⋅ +( ) +1

1 11 2

With R open, the circuit defaults to dominant-pole compensation. (The factor C1||C2 is the series combination of C1 and C2; || is a mathematical operator, not a topological descriptor.) In the case of an ideal op-amp, as K → ∞, the pole approaches the origin and the gain is



VV sR C C

o

i R K i, →∞

= − ( )1

1 2

This is a dominant single-pole amplifi er response with an amplifi er shunt capaci-tance of C1 and C2 in series. For comparison, the plots of Vo/Vi for K → ∞ and R, K → ∞ are shown below.

12π R(C1 + C2)

z = log f

R finite

log

R → ∞

Two-Pole Compensator Design Constraints

The above algebraic expressions for closed-loop gain do not of themselves satisfy the requirements for two-pole compensation. The following conditions must also hold:

1. The poles must be equal (or close): p1 = p2 = p.

2. The poles must be less than the zero: z/p > 1.

The fi rst condition is satisfi ed for real poles when the coeffi cients of the qua-dratic pole factor of the closed-loop voltage gain have the relation

ab= ⎛

⎝⎞⎠2

2

where a is the quadratic coeffi cient and b is the linear coeffi cient. Under the above condition, the quadratic polynomial factors into a perfect square. Because the K + 1 factor is in a only, its variation produces the loci of poles for a constant b, shown below.


138 Chapter 2

The poles are equal when their value is −b/2a, and the corresponding gain is found by setting the discriminant, b2 − 4a, to zero and solving for K + 1:

KR C C R R C C C R C

R RC Cp pi i

i

+ = +( ) + +( ) +=1

241 2

21 2

21 2 2

222

1 2

K is a fi nite amplifi er open-loop gain that can be implemented as an op-amp inner-loop fi xed-gain stage. But this requires additional circuitry and the feed-back network that sets the gain of the op-amp must not interfere with the two-pole feedback network. The two-pole circuit is usually made to be one of the stages in the forward path (G) of a feedback amplifi er, within a larger loop.

Instead of setting the compensator by adjusting K, solve the K + 1 equation above for one of the compensator elements, R:

RR C

C CK C C C K KC Ci=

+( )⋅ +( )⋅ − ± ⋅ ⋅ +( )⋅ −( )⎡⎣ ⎤⎦

2

1 22 1 2 1 1 22 1 2 1

where p1 = p2 and, of course, R is positive and real, requiring that KC1 > C2. This equation for R is rather involved and can be simplifi ed by approximation to

R RK C CC C

K K C C p pi≅ ⋅ ⋅ ⋅( )+

⎡⎣⎢

⎤⎦⎥

>> ⋅ >> =411 2

1 21 2 1 2, , ,

+

−

−

+

s

jω

b > 0

a = 0

a increasing

1b

1b= −

a = 0

−− b

b = constant

2a2b



The second constraint on two-pole compensator realization is that z > p. From Vo/Vi,

zR C C z

=+( ) =1 1

1 2 τ

and the positive value of the two poles is

pba

R C C R CR RC C K

i

i p

= = +( ) ++( )

=2 2 1

11 2 2

1 2 τ

Because the poles are equal, a = (b/2)2, and they are located on the real axis at

ba b2

2=

Then the condition z > p becomes

1 2 1τ τz pb

> =

From the voltage-gain expression, b = tz + RiC2. Substituting

1 2 1

2τ τ τz z i pR C>

+=

or

R C R C Ci z2 1 2> = +( )τ

Solve for RiC2 in terms of (z/p) from the inequality for 1/tz, and

R Czp

i z2 2 1= ⋅ ⋅ −⎛⎝⎜

⎞⎠⎟

τ


140 Chapter 2

Then solving z > p, using b/2a instead of 2/b results in

R Czp K C C C z p

zp

KC

C Ci

z2

1 1 2

1

1 22 12 1= ⋅

⋅ +( )⋅ +( )[ ] −< ⋅ +( )⋅

+⎛⎝⎜

⎞⎠⎟

τ,

The additional constraint on z/p is weak for large K but suggests that C1 be made larger than C2 for maximum pole-zero separation. A special case of RiC2 is

zp

KC

C CR Ci z≅ ⋅ +( )⋅

+⎛⎝⎜

⎞⎠⎟

>>2 1 1

1 22, τ

When RiC2 dominates b, the pole-zero separation is pushed to the limits of RiC2. In this case, with large K,

R RCKC

R C K p pi i z z≅ ⋅⎡⎣⎢

⎤⎦⎥

>> >> =2

12 1

41, , ,τ

Finally, from 1/tz, the constraint on the capacitors is

CC

RR

i1

2

1< −

These formulas can now be used to design two-pole compensators with real and equal poles, and gain values typical of either op-amps or low-gain amplifi ers.

Example: Two-Pole Compensation

A two-pole amplifi er has the following circuit values:

K R C Ci= = = =100 33 10 1001 2, , ,k pF pFΩ

For this amplifi er,



R = ⋅( )( )

⎡⎣⎢

⎤⎦⎥ =33

1004 100 10

825kpF

pFΩ Ω

τz R C C= ⋅ +( ) = ( )⋅( ) =1 2 825 110 90 75Ω pF ns.

The conditions for application of the equation for R are satisfi ed:

R RCKC

R C K p pi i z≅ ⋅⎡⎣⎢

⎤⎦⎥

>> >> =2

12 1 2

41, , ,τ

All element values are determined, and the natural frequency of the pole factor, which is the break frequency of the two poles, is found either from 1/tz or directly from a:

fa R RC C K

ni

= =+( )

=12

12 1

96 51 2π π

. kHz

As a check, when the poles of a quadratic factor are equal, damping ratio, z = 1. From the pole factor of the closed-loop voltage gain, ζ = =b a2 1 03. . The zero is located at

1 2 1 751 2π ⋅ ⋅ +( ) =R C C . MHz

Vo

100 pF

33 kΩ

10 pF

−100

Ri

R

Vi

C1C2

+

−


142 Chapter 2

From the SPICE simulation, the phase is −90° at 100 kHz, where the poles should be. The Bode plot from circuit simulation is shown below.

Frequency

40

0

−50

−100

−150

Mag

nitu

de, d

Bf

−180

°, d

eg

−20

0

20

−4010 kHz 30 kHz 100 kHz 300 kHz 1.0 MHz 3.0 MHz 10 MHz

Frequency

10 kHz 30 kHz 100 kHz 300 kHz 1.0 MHz 3.0 MHz 10 MHz

The zero is located at 1/2pR(C1 + C2) = 1.75 MHz. From the SPICE simula-tion, the phase is −90° at 100 kHz, where the poles should be. As a check, the magnitude will be down −6 dB (for two poles) at the break frequency. At 34 dB (down from a static gain of 40 dB), it is 91 kHz. The maximum closed-loop phase lag occurs at 631 kHz and is −142°. The nonmonotonic phase plot, which dips down and comes back up due to the zero, is characteristic of two-pole-compensated amplifi ers. The magnitude plot rolls off with a −2 slope at the pole



frequency to the zero frequency at about 1.75 MHz. (Because the amplifi er is inverting, the Bode plot phase is offset by −180°.)

Generalized Two-Pole Compensator

The previous development assumed real poles. What happens if the circuit is modifi ed to allow for complex poles? The benefi t in doing this, if it can be done, is that for amplifi ers with other poles and zeros in the loop gain, complex pole-pair compensation can be achieved by the compensator while maintaining high loop gain over bandwidth.

A more general set of design formulas takes the given design constraints as independent variables and yields two-pole compensator element values. Starting with Ri, K, wn, and z of the pole factor (now no longer necessarily one), a useful design parameter, the pole-zero separation, will be given its own symbol as defi ned:

zp

z

n

= =ω

γ

Noting that the location of the zero, z = 1/tz, and that the quadratic pole is of the form

as bss

sn n

22

12

1+ + = ⎛⎝⎜

⎞⎠⎟ + ⎛

⎝⎜⎞⎠⎟ ⋅ +

ωζ

ω

then z can be expressed in terms of design parameters as follows:

z a

K RR C C R C C

nn

z z

i

= ⋅ ⇒ = ⋅ ⇒ = ⋅

⇒ +( )⋅ = ⋅ ⋅ +( )

γ ωω

γ τ γ τ

γ

1

1

2 2

1 22 2

1 22

where a is taken from the voltage gain of the compensator circuit. Solving for R,


144 Chapter 2

R RK C C

C Ci= ⋅ +( )⋅( )

⋅ +( )1 1 2

21 2γ

z is now brought in as

ζ ω τ ω= = ⋅ = + ⋅ba

b R Cn

z in

2 2 22

The compensator element C2 results from solving the equation for z and is

CR

z

i2

2 1 12

= ⋅ ⋅ −( )⋅ >⋅

ζ γ τ ζγ

,

C2 is expressed entirely in given parameters and is thereby determined. Next, the equation for z,

zR C C z

=+( ) =1 1

1 2 τ

is solved for C1:

CR

Cz1 2= −τ

It is then substituted into R. This results in an expression for R in given param-eters and C2, which is known;

RC K R C

R CK

z z

ii= ⋅ −

+⎛⎝⎜

⎞⎠⎟

⋅⎛⎝⎜

⎞⎠⎟

⎡⎣⎢

⎤⎦⎥

>+

⎛⎝⎜

⎞⎠⎟

⋅τ γ τ γ τ2

2

22

2

11 1

, zz

Finally, since R is now known, it is substituted into C1 to yield

C CK R Cz i

1 2 22

11 1

1= ⋅− +( )[ ]⋅[ ] −

⎡

⎣⎢

⎤

⎦⎥γ τ



Example: Two-Pole Compensator Design

An amplifi er has a gain of K = 10 k, Ri = 10 kΩ and is to be two-pole compen-sated to have a zero at 500 kHz and begin its roll-off a decade lower, at 50 kHz. Furthermore, an MFED pole response (30° pole angle) is desired, where z ≅ 0.866. Component tolerances are 5%. The required parameters are

τπ πz

zf= = ( ) =1

21

2 500318

kHzns

γω

= = =z

n

50050

10kHz

kHz

First, calculate C2; it is 519 pF. The closest 5% part is

C2 520= pF

Next, calculate R, using the calculated value for C2 (instead of the 5% value) to keep the calculations accurate. (This is important when C1 is calculated, because the difference of two large numbers is taken.) Then R = 613 Ω. The closest value is

R = 620Ω

Finally, C1 is calculated from its equation, or from

CR

Cz1 2= −τ

if care is taken to retain numerical consistency. It is 0.32 pF. This is a very small discrete capacitor value and suggests that it might be diffi cult to realize this reliably as a discrete circuit in manufacture because this value is on the order of parasitic capacitances. The circuit-board layout between the output node and R must minimize stray capacitance.


146 Chapter 2

One way to implement C1 is with a small trimmer capacitor of about 1 pF maximum value. If such a small C1 is not feasible, then the given parameters must be adjusted to result in larger capacitance. C1 increases if R increases due to a decrease in C2. And C2 decreases when z, g, or tz decrease or Ri increases. The amplifi er design is shown below.

Vo

520 pF

620 Ω

10 kΩ

0.33 pF

−104

Ri

R

Vi

C1C2

+

−

To check these results, we turn from synthesis to analysis and calculate a and b of the pole factor:

a RR C C K fi n= +( ) = × ⇒ = ≅−1 2

11 21 1 06 10 48 8 50. .s kHz kHzb R C C R Ci= +( ) + = + =

⇒ = ≅1 2 2 318 5 19 5 51

0 85 0 87

ns s s. .

. .

μ μζ

Both fn and z are within the 5% tolerance of the components.Finally, check these results against the constraints in the formulas for C2 and

R:

ζγ

= > = = ( )0 871

21

200 05. . checks



CR K

z

i2

2

0 331

0 32= >+( )

= ( ). .pF pF checksγ τ

The lower limit of C2 is approached because C1 and C2 are so widely separated.

The fi nal check of this example is made from the SPICE frequency-response simulation, shown below.

80

60

40

20

0

Mag

nitu

de, d

B

1.0 kHz 10 kHz 100 kHz 1.0 MHz 10 MHz

Frequency

f−18

0°, d

eg

Frequency

−150

−100

1.0 kHz 10 kHz 100 kHz 1.0 MHz 10 MHz

−50

0


148 Chapter 2

Can the Compensator Circuit Be Statically Stabilized?

The above amplifi er has no static (dc) feedback and behaves like an integrator at 0 Hz. Unless it is within a larger feedback loop, the output drifts out of its linear range due to offset errors. For standalone applications, Rf must be included for static stabilization, as shown below. (The resulting compensator has the topology of a bridge-T fi lter.)

Vo

Rf

−K

Ri

Vi

R

Ii

C1C2

The transfer function, with Rf included, is approximately the same as before under the conditions that

RR

sC sC Rfi>>

+ ( )⎧⎨⎩1 12 1

Under these conditions, the static-path feedback through Rf is small compared with the capacitive path (yet enough to statically stabilize the amplifi er), and Rf negligibly shunts Ri and does not affect the transfer function of the capacitive path. Two-pole compensation can be achieved with limited, but often adequate, static feedback, and all the theory developed thus far can be applied.

What happens if an op-amp is used? The voltage gain for K → ∞ is



VV

RR

sR C Cs R RC C sR C C

o

i K

f

i f→∞

= − ⋅ +( ) ++ +( ) +1 2

21 2 1 2

11

As Rf → ∞, the voltage gain approaches Vo/Vi for K → ∞, as it must. This gain differs from the generalized Vo/Vi in that b = tz and does not have the extra degree of freedom that Vo/Vi does, with the RiC2 term. Consequently, z and g are not independent but are related by

ζ ω τ ω ζγ

γζ

= = ⇒ = ⇒ =bn

z n

2 21

21

2

Proceeding similar to the derivation of C1,

RC R C

CR

z z

f

z

f

= ⋅ −⎛⎝⎜

⎞⎠⎟

>τ τγ

τγ2

22

2 21 ,

C2 is chosen to satisfy the above constraint that R > 0. This choice depends on Rf and interacts with it. The pole locus of Vo/Vi was varied by (K + 1) since it was in a but not b. For this compensator, variation with constant b is due to Rf instead. To achieve g > 1, as required for a two-pole compensator, the poles must be complex and have a pole angle greater than 60°, as plotted below.

s

jω

ωn

Rf increasing

60°

− z


150 Chapter 2

Although the pole-zero separation is zero, 60° establishes the minimum Mm as 1.15 (or 1.25 dB) and minimum Mp as 16%. For a useful compensator with one octave of pole-zero separation, g = 2. Then z = 0.25 (f = 76°), Mm = 2.97 (or 6.3 dB), and Mp = 44%.

Infi nite (op-amp) forward path gain drives the circuit poles to the origin, defeating the two-pole scheme. With nonlarge Rf, the poles again become fi nite, but because of the unavoidable underdamped response that accompanies ade-quate pole-zero separation, the bridge-T two-pole op-amp compensator is very limited for two-pole compensation. It functions better as a notch fi lter, which is a typical application for bridge-T networks.

The design equations and a design example of the two-pole compensator circuit have been presented. With the math worked out, use of this design procedure is not diffi cult and can result in better feedback amplifi er accuracy and linearity at higher frequencies than dominant-single-pole compensation. Remember: two-pole compensation is used to increase not amplifi er stability but upper-frequency loop gain. Two-pole compensation tends to decrease stability and must be applied carefully, making sure that no uncompensated poles exist in the loop below the two-pole break frequency.

Second, this compensation technique, when implemented using the given circuit, is best placed within a larger feedback loop or else static errors will cause it to drift out of range. This problem can usually be corrected by simply placing a large-value feedback resistor around the fi nite-gain amplifi er. However, if an op-amp is used, the pole-zero placement for two-pole compensation is con-strained excessively, rendering the attempt a failure. Not every “good idea” results in something useful.

OUTPUT LOAD ISOLATION

In some feedback amplifi er applications, the load impedance is highly reactive, and the amplifi er has a signifi cant output resistance Ro. This combination can add a load-dependent output pole to the loop. A method for isolating capacitive loads is shown below, where CL is the load, and Ro is the amplifi er open-loop output resistance.



The noninverting version is show below.

Ri

Vi

Rf

RoVo

Vh

V−

Cf

V1

CL

R

−

+ −

+

The compensation scheme has two feedback paths, an accurate low-frequency path and a load-isolated high-frequency path. The feedback compensation capacitor Cf is isolated from the load by output decoupling resistor R. The low-frequency feedback through Rf is taken at the output to eliminate static error due to Ro and R.

With no load isolation or compensation,

R C f= = 0

The load introduces a pole in the loop at −1/(Rf ||Ro) ⋅ CL. If Cf is then added to compensate for this pole, the loop gain becomes

GHR R

R RR

R Rs R R C sR Cf o

f m

i

f i

f m f f= −−( )

⎛⎝⎜

⎞⎠⎟

⋅+

⎛⎝⎜

⎞⎠⎟

⋅−( )[ ]⋅ +{ }⋅1 ff

f o f L f i fs R R C C s R R C+( )

( )⋅ +( ) +[ ]⋅ ( )⋅ +[ ]1

1 1

Ri

Vi

Rf

Ro

Vo

Vh

V−

Cf

V1

CL

R

−

+−+


152 Chapter 2

where Rm = Ro/(−K). When CL = 0 and Ri >> Ro, the poles are well separated. As CL increases, pole separation decreases as the higher pole moves down in fre-quency, reducing stability. Cf introduces a feedback zero and pole as a phase-lead network. The zero can be placed to cancel the amplifi er output pole by setting

CRR

Cfo

fL= ⋅

× ×G G

σ

H

−1 −1 −1

H

R = 0

(Rf || Ro)(CL +Cf) (RI || Rf)Cf R1C1

jw

Cf increasing

−1(Rf ||(−Rm))Cf

From the parameter-variation plot above, as Cf increases, all poles and zeros shift toward the origin. For CL >> Cf, the load pole shifts little, and the pole and zero in H move together and away from the load pole.

When R is added and the topology is redrawn, the output network forms a bridge.

V1Ro

Rf

Ri

R

Vh

Cf

Vo

CL

−KV−

V−



The exact solution for this circuit, a nontrivial exercise, can be found by revert-ing to KCL, applied at the nodes with voltages: V−, V1, Vh, and Vo. This results in the fl ow graph for the inverting amplifi er.

Vi Vo

V− −K V1 Vhak

gh

gc

ac

ab

db

gf

df

where

aR R sC

bR

c sC dZ R R

fR

gR sC R

hR

i f f ff

L f

o f

= ( ) = = = ( )= = ( ) =

11

1 1

1 11

1

, , ,

, ,oo i

kR

, = 1

The amplifi er gain is −K and V1 = −KV−. Some simplifying assumptions can be made that reduce the complexity of the fl ow graph (such as removing b/d, c/d, and-or f/g), but the remaining circuit analysis is still unwieldy. We need a more functionally oriented approach.

The low- and high-frequency (lf and hf) feedback paths have been approxi-mated below, along with their Bode plots. The lf path has transmittance,

VV

RR R s R R C s R R Clf

i

f i o L f i f

− =+

⎛⎝⎜

⎞⎠⎟

⋅+( ) +

⎛⎝⎜

⎞⎠⎟

⋅ ( ) +⎛⎝⎜

⎞⎠⎟1

11

11

,,

,RsC

R R R Rof

o f i<< + << +1

where the simplifying assumptions are that Cf and Rf + Ri do not load the smaller output resistances Ro and R.


154 Chapter 2

The hf path is

VV

sRCs R R C

s R R Cs R R Chf

L

o L

f i f

f i f

− = ++( ) +

⎛⎝⎜

⎞⎠⎟

⋅ ( )( ) +

⎛⎝⎜

⎞⎠⎟1

11 1

,

RR RsC sC

Rof L

f, ,<< <<1 1

The hf-path approximations are similar to those of the lf path. At high frequen-cies, this feedback transmittance approaches

RR Ro +

The composite feedback transmittance is the sum of the two paths, or

VV

RR R

s RC R C sR Cs R R C s R R C

i

f i

L f f f f

o L f i

− =+

⎛⎝⎜

⎞⎠⎟

⋅+ +

+( ) +[ ]⋅ ( )1

2 11 ff +[ ]1

Without R, there is one less LHP zero, as in GH. The feedback path is an all-pass network when the coeffi cients of the pole and zero terms are equated. This results in

Ro Rf

CL Ri Cf

RV−

V1

−

+

log

logw1(Rf ||Ri)Cf

Rf+Ri

1(Ro +R)CL

Ri



RRR

R CR R

RR R

RCi

fo f

o

f

f i

fL=

⎛⎝⎜

⎞⎠⎟

⋅ = +⎛⎝⎜

⎞⎠⎟

⋅+⎛

⎝⎜⎞⎠⎟

⋅,

The load capacitance pole is removed from the loop gain. The closed-loop response, however, is still affected by CL. The constraints of V−/V1 for lf and hf paths require that 1/RoCf be checked after applying these formulas for R and Cf, to make sure that this pole is well above fT.

Example: Load Capacitance Compensation

A fast op-amp with K = 105 and poles at 100 Hz and 4 MHz is used in the invert-ing confi guration to drive a 10 nF load with a voltage gain of −3. Rf = 30 kΩ and Ri = 10 kΩ. The open-loop output resistance is 10 Ω. The feedback capacitor Cf and decoupling resistor R are calculated from the R, Cf formulas:

R = 3 3. Ω

and

C f = 5 9. pF

For the uncompensated amplifi er, the step response shows obvious ringing.

Ro

CL

CfR

V−

V1

−

+

log

Rf ||Ri

logw

1

1(Rf ||Ri)Cf

1RCL

1(Ro +R)CL


156 Chapter 2

Peaking is evident in the frequency response and group delay plots.

5.0

4.0

3.0

2.0

1.0

0.00.0 μs 0.4 μs 0.8 μs

Time

Unc

ompe

nsat

ed -

v o’ V

1.2 μs 1.6 μs 2.0 μs

20.0

10 Hz 100 Hz 1.0 kHz 10 kHz 100 kHz

Frequency

1.0 MHz 10 MHz 100 MHz

−40.0

−80.0

0.0

500.0

200.0

0.0

400.0

Unc

ompe

nsat

ed

gro

up d

elay

, ns

Unc

ompe

nsat

ed

mag

nitu

de, d

B

Compensation is now applied, and the response improves. No ringing is evident in the step response



No peaking appears in the group delay or frequency response (below).

3.0

2.5

2.0

1.5

1.0

0.5

0.00.0 μs 0.2 μs 0.4 μs

Time

Com

pens

ated

-v o

’ V

0.6 μs 0.8 μs 1.0 μs

10 Hz 100 Hz 1.0 kHz 10 kHz

Frequency

100 kHz 1.0 MHz 10 MHz 100 MHz

−50.0

−100.0

0.0

250.0

200.0

0.0

Com

pens

ated

g

roup

del

ay, n

sC

ompe

nsat

ed m

agni

tude

, dB

The schematic diagram of the compensated amplifi er shows how the op-amp is modeled, using RC integrators and buffers to create the poles.


158 Chapter 2

The SPICE program used for the simulation is listed below.

Load-Compensated Amplifi er

.OPT NOMOD OPTS NOPAGE

.AC DEC 30 10 100MEG

.TRAN 2n 2u

VI 10 0 AC 1V PULSE (0 1V)

RI 10 15 10k; amplifi er with pole at 100Hz and 4MHz

EA 50 0 15 0 -1E5RA 50 60 10kCA 60 0 0.159uFEB 70 0 60 0 1RB 70 80 1kCB 80 0 39.8pFEC 30 0 80 0 1RO 30 40 10

R 40 20 3.3CL 20 0 10nFCF 40 15 5.9pFRF 20 15 30k

.PROBE

.END

Capacitive loads can also be isolated by placing a shunt RL in series with the amplifi er output. At 0 Hz, the transmittance to the load is one. At high-frequencies, L appears open, leaving R as isolation. For excessive inductive loading, the load is often characterized by a series RL. If it is fi xed, a series RC in parallel with it can form a constant-impedance network.

vi

Ri RA RB

CB

Ro

CL

Vo

R

Cf

Rf

CA−

+

10

10 kΩ 10 kΩ 1 kΩ−105 1 1

30 kΩ

10 Ω 3.3 Ω

100 Hz 4 MHz 5.9 pF

10 nF30.8 pF

0

15 50 60 70

0.159 μF

80 30 20

40



COMPLEX POLE COMPENSATION

Previous compensation techniques involved real poles and zeros. Open-loop complex poles appear as resonances that can sometimes be damped by identify-ing the circuit elements involved in the undesired resonance. This identifi cation is not always successful, especially when the circuit has many possible parasitic reactances.

(a)

(b)

jw

jw

s

s

From root-locus criteria, pole angle can be reduced by the addition of a real pole at a lower frequency, as shown above in (a). As the pole increases in fre-quency due to static loop gain, K, the complex pole radius (wn) decreases, but so does the pole angle f. This decrease in f is slight in a narrow range of K, making this a marginally useful technique.

A real zero, placed at a higher real frequency than that of the complex poles, draws them out to a larger pole radius and lower pole angle with increasing gain, as shown in (b).


160 Chapter 2

Complex poles can be compensated directly by complex pole-zero cancella-tion. Complex zeros are realized by a series RLC network at the output of a transconductance amplifi er. Typically, the network is placed in parallel with a transistor load resistor.

(a)

(b)

Gm Vi

Vo

jw

s

RL R

L

C

The transfer function of this circuit is

VI

Z Rs LC sRC

s LC s R R Co

oo L

L

= = ⋅ + ++ +( ) +

2

2

11

The pole-zero placement is shown in (b). In addition to the desired zeros, there is another pair of poles with a larger linear coeffi cient (due to RL). This is similar to phase-lead compensation; the added poles are at a decreased pole angle from the poles canceled by the zeros, with no loss of pole radius.

Empirical compensation of hidden complex pole-pairs begins by observing the ring frequency fr (which is the damped frequency fd) and the time constant



of its decay, tr, from a step response. The value of tr can be calculated from the peak overshoot Mp. The relationship among tr, fr, and Mp is

ταr

r pf M=

⋅=

⋅ ⋅ ( )1

21

4 1ln

Compensator element values for an MFED response are calculated by using these empirical parameters:

RR

f

L

r r

=⋅ ⋅( ) +

−2

12 32

2π τ

CR f

r

r r

=⋅ ⋅( ) +⎡⎣ ⎤⎦

24 12

τπ τ

LR r= τ

2

It is usually easier to measure the peak overshoot Mp than to estimate tr. By using the formula for Mp, the compensator values for a pole angle of cos−1z are

RR M

M M

L p

p p

=⋅ ( )

+ ( )[ ] − ( )ln

ln ln

1

1 12 2ζ π

CM MR f

p p

L r

=+ ( )[ ] − ( )ζ π

π

2 2

2

1 1ln ln

LM R

f M M

p L

r p p

=+ ( )[ ]( )

⋅ + ( )[ ] − ( )π

π ζ π

2 2

2 2 2

1

4 1 1

ln

ln ln

Example: Compensation by Complex Pole-Zero Cancellation

An amplifi er has an excessively underdamped response. A maximally fl at ampli-tude (MFA) response is desired. A transadmittance stage in the amplifi er is free to be compensated and has a load resistance of 1 kΩ. The response to a step shows a ring frequency of 30 MHz and a peak overshoot of Mp = 0.25.


162 Chapter 2

By substituting these values into the formulas for R, L, and C, and noting that an MFA response has a pole angle of 45° and that ζ = 2 2, the compensator element values are

R C L= = =1 33 3 52 4 10. . , .k pF HΩ μ

COMPENSATION BY THE DIRECT (TRUXAL’S) METHOD

The direct approach to calculation of G and H for a given closed-loop response M is to begin by specifying what M should be. Neglecting Ti and To, if any, since they are cascaded with the feedback loop, we describe M as

MGGH

=+1

Solving for the loop gain, we get

GHHM

HMN N

D D N NH M

H M H M

=−

=−1

where N and D are numerators and denominators of H and M. For a given G we can solve directly for H:

HG M

GM M GN D N D

N NG M M G

G M

= − = − = −1 1

Not only M must be chosen to satisfy the system requirements, but also the resulting H must be physically realizable. For a high-order system, M must be high order for a realizable H. The familiar criteria of amplifi er per-formance are consequently more diffi cult to express in M. Therefore, this method is of limited use. If the amount of calculation were the limitation, a computer solution would be feasible, but creative design judgment is required in selecting M.



POWER SUPPLY BYPASSING

The elimination or compensation of parasitic capacitance and inductance is not a dynamic response compensation method in itself but is related. Before a feed-back amplifi er loop can be compensated, the individual stages of amplifi cation must be stable. Parasitic elements arise from both circuit components and layout.

−

−

−

−V

+

+

+

+V

Ri

Rin

Cin

CinLout

CL RL

VcRout

C1

L1

C2

L2

Rf

Vi

The diagram shows some of the more common parasitic elements for op-amp circuits. The connections of the amplifi er to the power supplies involves conduc-tors (wire or circuit-board traces) with a corresponding inductance. Circuit-board trace inductance is diffi cult to estimate accurately but is roughly 10 nH/cm for a rectangular trace that is much longer than its cross-sectional dimensions (Ruehli 1972). Capacitive bypassing of trace inductance shortens the loop length and decreases the characteristic impedance Zn to a low value.


164 Chapter 2

Oscillation can commonly occur due to the series LC resonance formed by the stray power-supply inductance and stray capacitance from the local supply node to an amplifi er input. As L increases, Zn becomes sizable with a small C. Consequently, the series resistance required to damp the resonance also must be large. By adding bypassing, L is decreased and C greatly increased. Both effects reduce Zn so that a smaller input-node resistance damps the series resonance.

Example: Damping Oscillation through Bypassing

+V

5 nH

10 nF

6 cm

IiRs50 Ω

The circuit has a source resistance of 50 Ω shunting the relatively high-resistance base input. Cbc = 3 pF. The collector supply connection is about 6 cm long.

The inductance is about (6 cm) ⋅ (10 nH/cm) = 60 nH and the characteristic impedance of the series resonance is

Zn = =603

141nHpF

Ω



Rs is smaller than Zn and oscillation is likely. If a 10 nF bypass capacitor with 5 nH of parasitic series inductance is connected to the collector, then

Zn = =510

0 7nHnF

. Ω

and the series LC resonance is well damped.



Designing High-Performance Amplifi ers


Raleigh, NC.


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10 9 8 7 6 5 4 3 2 1

ISBN: 9781891121845Series ISBN: 9781891121876

Library of Congress Cataloging-in-Publication DataFeucht, Dennis. Designing high-performance amplifi ers / D. Feucht. p. cm. – (Analog circuit design series ; v. 3) Includes bibliographical references and index. ISBN 978-1-891121-84-5 (pbk. : alk. paper) – ISBN 978-1-891121-87-6 (series) 1. Amplifi ers (Electronics)--Design and construction. 2. Electronic circuit design. I. Title. TK7871.2.F478 2010 621.3815′35--dc22 2009028290

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Contents

Chapter 1 Wideband Amplifi cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Multiple-Stage Response Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Amplifi er Stage Gain Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Pole Determination by Circuit Inspection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Inductive Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Bootstrap Speed-Up Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Source-Follower Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Emitter Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Cascode Compensation of the Common-Base Stage . . . . . . . . . . . . . . . . . . . . 55Compensation Network Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Differential-Amplifi er Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Shunt-Feedback Amplifi er Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Shunt-Feedback Cascode & Darlington Amplifi ers . . . . . . . . . . . . . . . . . . . . . . 82Closure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Chapter 2 Precision Amplifi cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Causes of Degradation in Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Intrinsic Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Extrinsic Noise: Radiation & Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Extrinsic Noise: Conductive Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Differential Amplifi ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Instrumentation Amplifi ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Low-Level Amplifi cation and Component Characteristics . . . . . . . . . . . . . . . 133Isolation Amplifi ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141Autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

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Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Transconductance Linearity of BJT Diff-Amp . . . . . . . . . . . . . . . . . . . . . . . . . 152BJT and FET Diff-Amp Temperature Characteristics . . . . . . . . . . . . . . . . . . . 157Thermal Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167Complementary Emitter-Follower Output Amplifi er. . . . . . . . . . . . . . . . . . . . 180Buffer Amplifi er Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Chapter 3 High-Performance Amplifi cation . . . . . . . . . . . . . . . . . . . . . . . .199Current-Input & Current-Feedback Amplifi ers . . . . . . . . . . . . . . . . . . . . . . . . 199Split-Path, Low-Frequency Feedback and Feedbeside Amplifi ers . . . . . . . . . 209Feedforward and Linearized Differential Cascode Amplifi ers . . . . . . . . . . . . 221α-Compensated Gain Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228fT Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232High-Performance Buffer Amplifi ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Unipolar Voltage-Translating Amplifi ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243Bootstrapped Input Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249Composite-Feedback & Large-Signal Dynamic Compensation . . . . . . . . . . . 251The Gilbert Gain Cell and Multiplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257Programmable-Gain Amplifi ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

vi Contents

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1Wideband Amplifi cation

Some amplifi ers are performance limited mainly by speed. Oscilloscope vertical amplifi ers, pulse and function generator output amplifi ers, and video and nuclear signal-processing amplifi ers are often speed limited. Fast amplifi ers are usually open-loop, limited-gain stages, such as those analyzed at low frequency in Design-ing Amplifi er Circuits, with one or two transistors per stage. New techniques have increased the speed of operational amplifer (op-amp) circuits, but the fastest amplifi ers consist of limited-gain stages. For the fastest speed, these amplifi ers are integrated to reduce parasitic reactances. Examined fi rst is the strategy of amplifi er design before analyzing various bandwidth extension techniques.

MULTIPLE-STAGE RESPONSE CHARACTERISTICS

The speed of an amplifi er can be expressed by its response to a step input. For a single-pole amplifi er with pole p = 1/t, the response to a unit step input can be characterized by its risetime. A single-pole amplifi er has a transfer function of the form

A s Ks p

( ) = ⋅+

11

with pole at −p. The pole is also at the bandwidth

ωbw p=

From the risetime formula, the single-pole risetime is

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2 Chapter 1

tp f

rbw

= ⋅ ( ) ≅ ⋅ = ≅τ τln 9 2 22 2 0 35

.. .

The unit step response is

v t K esteppt( ) = ⋅ −( )−1

These equations assume a linear amplifi er (or that small-signal analysis is valid). Large-signal amplifi er behavior occurs when a waveform reaches the limit of its linear range. What often results is waveform slewing, in which waveform change is rate limited and characterized by its slew rate. The maximum slew rate of a waveform is determined by its maximum instantaneous slope and amplitude. The full-power bandwidth fBW of an amplifi er is related to the maximum slew rate of a sinusoid that spans the dynamic range of the amplifi er. Differentiating the sinusoid and solving for the maximum value,

max sin maximum slew rate = ⋅( ) = ⋅ddt

V t Vm BW BW mω ω

The sinusoid changes over its full range in the slewing time:

tV

V fslew

m

BW m BW

= ≅2 0 32ω

.

When fbw = fBW, tslew is nearly the same as the risetime given above. A more general comparison of large- and small-signal risetime follows by fi nding the time it takes to slew from 10% to 90% of the fi nal value. This time is

slewing tV

V fr

m

BW m BW

=( )⋅ ⋅

⋅≅

0 8 2 0 26. .ω

When an amplifi er operates with some slewing, the bandwidth lies between fBW and fbw where always fBW < fbw.

Another quantity that characterizes speed is time delay td, defi ned as the time that the response to a unit step input takes to reach half of its fi nal value. It is found by setting vstep to 0.5 and solving for t :


Wideband Amplifi cation 3

tp p f

dbw

= ⋅ ( ) = ≅ ≅τ ln 2ln2 0 69 0 11. .

Delay time is useful for measuring the propagation delay of linear logic circuits, such as logic gates.

Fast amplifi ers usually consist of several cascaded gain stages. An amplifi er with n single-pole stages with poles at −p has a transfer function of the form

A s Ks p n( ) = ⋅

+( )1

1

The unit step response of A(s) is

n v A ss

Kp etk

stepn pt

k

k

n

-stage = ( )⋅{ } = −⎛⎝⎜

⎞⎠⎟

− −

=

−

∑L 1

0

111

!

Calculation of the risetime from this equation can be diffi cult. A simpler alter-native is to derive expressions for bandwidth. The bandwidth of a single-pole amplifi er is the pole frequency, or

wbw = p

The magnitude at bandwidth of a single-pole stage with static gain of K is found by setting w to p:

A jp Kp

Kp( ) = ⋅( ) +

= ⋅=1

1

122ω

ω

An n-stage amplifi er with single-pole stages has a transfer function of the form

n A s Ks p n-stage ( ) = ⋅

+( )1

1


4 Chapter 1

When the magnitude of A(jw) has rolled off to that of a single-pole stage, as in ||A(jp)||, this is the n-stage bandwidth:

A j Kp

Knωω

( ) = ⋅( ) +⎡⎣ ⎤⎦

= ⋅1

1

122 2

Solving for w = wbw, and expressing it as a fraction of p by defi ning the bandwidth shrinkage or bandwidth reduction factor, S, then

S npbw n( ) = = −ω

2 11

Fast amplifi ers usually have stages with quadratic pole factors in their transfer functions. The same kind of derivation of S(n) assumes an n-stage amplifi er transfer function of the form

A s Ks sn n

n( ) = ⋅+ +( )

1

2 12 2τ ζτ

Setting the magnitude of A(s) to that of a single-pole amplifi er at bandwidth results in the expression

A j K Kn n

n

ωτ ω ζτ ω

( ) = ⋅−( ) + ( )

⎛

⎝⎜⎞

⎠⎟= ⋅1

1 2

122 2 2 2

2

The pole factor of A(s) does not contain p, and the bandwidth is related to the single-pole stage by wn. (See Designing Dynamic Circuit Response, “Optimization of Time-Domain and Frequency-Domain Response” for derivation of bandwidth.) Solving for w in terms of wn, the result is

S n bw

n

n( ) = = − + + +( )ωω

ζ ζ ζ1 2 4 4 22 4 2 11 2

For n critically damped stages,



S n n( ) = − =2 1 11 2 , ζ

A one-stage critically damped amplifi er has S = 0.64, whereas for four stages S is about 0.3. For maximally fl at envelope delay (MFED) stages (ζ = 3 2), with n = 1, S ≅ 0.786; with n = 4, S ≅ 0.4. When the number of stages increases to 10, S ≅ 0.25. For MFED response, n stages have the approximate S of

Sn

MFED ≅ 0 786.

With these developments, we return to consider the risetime of multistage amplifi ers. The transfer-function magnitude for a general amplifi er of n poles is of the form

A jK

p p p

K

ii i jji ii

ωω ω ω τ

( ) =+ ( ) + ( ) +⎡⎣ ⎤⎦

≅+( )∑ ∑∑ ∑1 1 1 12 2 4 2 2 1 2 2 2 1 2

�

where 1/pi = ti. The higher-order terms in w are negligible for widely separated poles at much higher frequencies. The sum of time constants in the w2 term can be regarded as an equivalent single-pole time constant of

τ τ≅ ∑ ii

2

From tr, an approximate risetime is therefore

t tr ii

ii

rii

≅ = = ( ) =∑ ∑ ∑2 2 2 2 2 22 2 2. . .τ τ τ

In other words, the approximate risetime of a multistage amplifi er is the square root of the sum of the squares of the risetimes of the individual stages. For n identical stages, risetime degrades by approximately n that of a single stage.


6 Chapter 1

Example: Oscilloscope Risetime

A 100 MHz oscilloscope has a probe with a 2 ns risetime. The total risetime is found by fi rst calculating the risetime of the oscilloscope. Applying the tr equation,

tr ≅ =0 3510

3 58

..

Hzns

Then the total risetime is approximately

tr ≅ ( ) + ( ) =3 5 2 42 2. ns ns ns

An accompanying approximation to bandwidth can also be made since t is an equivalent single-pole time constant. From single-pole bandwidth,

ωτbw

ii p≅ = ∑1 1

2

For n repeated poles, bandwidth, like risetime, degrades by approximately n .

AMPLIFIER STAGE GAIN OPTIMIZATION

As the number of amplifi er stages increases, bandwidth decreases. For a fast-amplifi er design strategy, therefore, the number of stages should be minimized. However, most amplifi er designs also require a given overall gain. Reducing the stage count demands increased gain per stage. Amplifi er stages have a gain-bandwidth product, fT, affected mainly by the active device. An increase of stage gain decreases stage bandwidth. An optimum stage gain, A1(s), that maximizes amplifi er bandwidth, wbw, for a given amplifi er gain, A(s), is derived by fi rst noting that

ω ωbw S= ⋅ 1



where w1 is the single-stage bandwidth. Then the gain-bandwidth product of the amplifi er is expressed in relation to its stages as

A A Snbw

11 1⋅ = ⋅( )ω ω

assuming the n-stages have the same gain,

A A n1

1=

Solving for wbw yields

ω ωbwnA A S n= ⋅ ⋅ ( )⋅−

11

1

The optimum number of stages is found by differentiating wbw with respect to n to maximize bandwidth:

ddn

Ad

dnS n Abw

nω ω= ⋅ ⋅ ( )⋅[ ]−1 1

1

For single-pole stages, S is substituted. S can be expressed differently by noting that

22

121 2

0

n nk

ke

nk n

= = ( ) ≅ +( )

=

∞

∑ln ln!

ln

Then

S nn

n( ) ≅ ⎛⎝⎜

⎞⎠⎟

= ⋅ −ln2ln2

1 21 2

Substituting for S in the derivative above, the right side becomes

Ad

dnA n

A A n A

n

n n

1 11 1 2

1 11 3 2 1

2

212

⋅ ⋅ ⋅ ⋅( )

= ⋅ ⋅ ⋅ −⎛⎝⎜

⎞⎠⎟⋅ +

− −

− − −

ω

ω

ln

ln ⋅⋅ ⋅ ⋅⎛⎝⎜

⎞⎠⎟

−nn

A1 22

1ln


8 Chapter 1

To fi nd the optimum number of stages nopt, set the derivative to zero and solve. Then

n Aopt = ⋅2 ln

The optimum stage gain is

optimum A A A e en Aopt1

1 1 2 1 2 1 65= = = = ≅ln .

This is not a large voltage or current gain. In practice, the optimum gain is somewhat larger than this value, usually around 2 to 3, due to bandwidth loss from interstage coupling.

Multistage amplifi er frequency-response magnitude approaches a gaussian function as the number of stages increase. This gaussian response is quickly approached in practice by a few stages. It is derived by fi rst rewriting ||A(jw)|| in terms of wbw from S. Given p = wbw/S, then

A jK

bwn nω

ω ω( ) =

( ) −( ) +⎡⎣ ⎤⎦2 1 2

2 1 1

Next, as n → ∞ in 21/n, and using the fi rst two terms of the exponential series expansion,

2 121 n

nn− → → ∞ln

,

Substituting this into ||A(jw)||, then

A jK

n

K

nn nω

ω ω ω ω( ) ≅

+ ( ) ( )⎡⎣ ⎤⎦=

+ ( )( ) ( )⎡⎣ ⎤⎦1 2 1 2 2 212 2

12 2

ln ln

||A(jw)|| is of the exponential form,

exn

x

x

n

= −⎛⎝⎜

⎞⎠⎟→∞

−

lim 1



So as n → ∞,

A j K e nωωω( ) = ⋅ → ∞

−( )⋅⎛⎝⎜⎞⎠⎟ln

,2 2

1

2

This ex 2

form of ||A|| is the gaussian response function.The maximum achievable bandwidth of an amplifi er with a gaussian response

is derived based on the unity-power-gain frequency fMAX. If ||A|| is a power gain, then it can be expressed in decibel scaling as

A j K eff

A cff

ω( ) = ⋅ − ⋅⎛⎝⎞⎠ ⋅( )⋅⎛

⎝⎜⎞⎠⎟

= ( ) − ⋅dB dB10 102

20

1

2

1

logln

log⎛⎛⎝⎜

⎞⎠⎟

2

where c reduces to

c = ⋅ ≅5 2 1 51log .

The maximum bandwidth is achieved when ||A|| passes through fMAX at unity power gain (0 dB). From ||A(jw)||db,

A cf

fMAX0 0

1

2

( ) − ⋅⎛⎝⎜

⎞⎠⎟

=dB

Solving for c and substituting it into ||A(jw)||db,

A Af

fMAXdB dB= ( ) ⋅ −⎛

⎝⎜⎞⎠⎟

0 12

2

The bandwidth is the frequency at which ||A||dB has rolled off by −3 dB:

A A Af

fMAXdB dB dB− ( ) = − = ( ) ⋅ −⎛

⎝⎜⎞⎠⎟

0 3 02

2


10 Chapter 1

The solution of this equation for f is the power-gain bandwidth fbw and is

f fA

bw MAX= ⋅( )30 dB

Example: Oscilloscope Vertical Amplifi er

A wideband analog oscilloscope has a vertical defl ection sensitivity of 2 V/cm at the cathode-ray tube (CRT) and a defl ection plate termination resistance of 350 Ω. The input sensitivity is 50 mV/div into 100 Ω from the source when ter-minated by the 50 Ω scope input. The power gain is

A 0 102 350

50 10026 6

2

2( ) = ⋅ ( )( )

⎛⎝⎜

⎞⎠⎟dB

V div

mV divdBlog .

ΩΩ

�

The fMAX is 2 GHz. The maximum fbw is

fbw = ⋅ =23

26 6672GHz

dBdB

MHz.

The actual bandwidth of the amplifi er (without the CRT) is 550 MHz. The use of maximum bandwidth as a performance index can be taken as the ratio of actual to maximum theoretical bandwidth, or

550672

82MHzMHz

≅ %

That is, 82% of the maximum achievable bandwidth is realized in the vertical amplifi er, within 18% of the theoretical limit.

POLE DETERMINATION BY CIRCUIT INSPECTION

Circuit complexity increases as the number of reactive elements increases and makes derivation of the transfer function more diffi cult. At some complexity



threshold (which varies among engineers), the urge to simulate the circuit by computer overwhelms the desire to achieve an intuitive understanding of it. Even for complexity that requires simulation, it is necessary to know what to simulate. Until circuit design is computerized, the choice of numeric values of circuit ele-ments must be based on estimation techniques and qualitative reasoning.

Most circuits can be decomposed into modules with well-defi ned interfaces. Intrastage behavior is relatively free of interaction with other noncoupled stages. Interaction among modules can be considered apart from interaction within modules. The dynamic behavior of each circuit module can thus be determined individually, reducing the complexity of analysis.

A technique described by Cochrun and Grabel (1973) and streamlined by Rosenstark (1986) makes estimation of pole locations in active RC circuits simpler than solving the circuit for the transfer function. The degree of the characteristic equation (the transfer function denominator set to zero) equals the number of poles and the number of reactive circuit elements. Each capaci-tor in an RC circuit is associated with a pole. The characteristic equation in a normalized transfer function can be written as

D s a s a s a snn

nn( ) = + + + + =−

−1

11 1 0�

The technique allows determination of the an from inspection of the circuit. The coeffi cients, in terms of circuit elements, are found as follows. The equation for a1 is

a R Cii

n

i i11

= ( )⋅ = ( )=∑ ∑open openτ

a1 is calculated as a procedure as follows

a1 Procedure1. Order the C by numbering them.

2. For each C, beginning with C1, fi nd the equivalent resistance across its termi-nals with all other C open. This is Ri (open). Multiply Ri (open) by Ci for ti (open).

3. Sum the ti (open) to obtain a1.


12 Chapter 1

This procedure is expedited by writing the time constants in the fi rst column of a table beginning with t1 (open) in the top row and tn (open) in the bottom row.

Next, for a multi-capacitor circuit, a2 is needed and is

a R C R C Cij i

n

i

n

i j i j ij i

211

1

= ( )⋅ ⋅ ( )⋅ = ( )= +=

−

= +∑∑ open shorted openτ

111

1 n

i

n

j iC∑∑=

−⋅ ( )τ shorted

The procedure for a2 continues the table by fi lling in the second column and then using the ti (open) from the fi rst column. All C not shorted are open when R is being found.

a2 Procedure1. For each Ci, do the following:

a. Short Ci. For each C after Ci (in the order they were numbered in the a1 procedure), fi nd the terminal R for C (Cj). Multiply this Rj(Ci shorted) by Cj for tj(Ci shorted).

b. Multiply the tj(Ci shorted) by ti (open).

2. Add the time-constant products from step 1b to obtain a2.

Each entry in the fi rst column of the table from the a1 procedure will have n − i entries in the second column for each Cj.

For a3, three summations are made, extending the a2 procedure. For the third column, two capacitors are shorted at a time (indices i and j), and k is indexed:

a R C R C C R Cik j

n

j i

n

i

n

i j i j k311

1

1

2

= ( ) ⋅ ⋅ ( )⋅ ⋅= += +

−

=

−

∑∑∑ open shorted ii j kC C, shorted( )⋅

A way to keep the indexing straight is to base the entire procedure around the time-constant table. This Rosenstark table for three capacitances is sketched below.



a1 a2 a3

C1 t1 (open)t2 (C1 shorted) t3 (C1, C2 shorted)

t3 (C1 shorted)

C2 t2 (open) t3 (C2 shorted)

C3 t3 (open)

The column numbering is for the i index. The procedure amounts to fi lling in the table and then, for a1, summing the ti in column 1; for a2, summing the products of t in column 2 with t from column 1; for a3, summing the products of t in column 3 with t from columns 2 and 1. The summation always involves the t of a column multiplied by the t of the columns to the left. When a t is found, the capacitors indexed in the columns to the left are shorted.

Active devices can change the resistance at a capacitor, for example, due to the Miller effect, and must be taken into account when fi nding equivalent resistances.

Example: Op-Amp Circuit Poles from the Cochrun-Grabel Method

+

–

Rc

Rs Ri

Rf

Cc

Ci

Vo

Vi

AR

R RsR C sR C

s R R C s R R Cv

f

i s

c c i j

i s i f c c

= −+

+( ) +( )[ ] +( ) +[ ] +( )

1 11 1

This op-amp circuit, with transfer function as shown, can be analyzed using the Cochrun-Grabel method. The Rosenstark table is given below.

a1 a2

Ci (Ri ⏐⏐ Rs) · Ci (Rc + Rf) · Cc

Cc (Rc + Rf) · Cc


14 Chapter 1

The ordering of capacitors, as shown in the table, is Ci, Cc. This ordering is arbitrary. The a1 column is fi lled in, beginning at the Ci row, by fi nding the open-circuit resistance across the terminals of Ci. An active device (i.e., the op-amp) requires fi rst a determination of its effect on resistance. The V_ input is a virtual ground for the ideal op-amp. Knowing this, the Ci terminals have across them Ri||Rs because Vi has zero resistance. The time constant for the fi rst entry, Ci row, a1 column, is complete. For the Cc row, a1 column, examine Cf. Rc is in series with the Cc terminal and goes to ground. From the other terminal, we determined that the Vo node has a resistance of Rf to Rc. Thus, the total resistance across Cc is Rc + Rf. The second entry is complete.

Now, begin with the a2 column. Short Ci (from the fi rst column) and deter-mine resistance across Cc. Again this is Rc + Rf. The table is complete. The an are now found from the table. The sum of the fi rst column is

a R R C R R Ci s i c f c1 = ( )⋅ + +( )⋅

Then a2 is found from the second column by multiplying its entries by the fi rst column and adding them. Since there is only one, no addition is needed here, and

a R R C R R Cc f c i s i2 = +( )⋅ ⋅( )⋅

The characteristic equation is

a s a s22

1 1 0+ + =

This quadratic equation is easily solved by noting that the a1 terms are the a2 factors, and the poles are therefore

pR R C

pR R Ci s i c f c

1 21 1= −

( )⋅= −

+( )⋅,

This result agrees with the reactance chart method, as shown below.



Example: BJT Amplifi er Poles from the Cochrun-Grabel Method

log

log w

⏐⏐ ⏐⏐Av

1⏐⏐Ri( Rs Ci)1

RcCc

1RiCi

1( )+Rf Rc Cc

Rf

+Ri Rs

⏐⏐Rf Rc

Rs

iV

+

–

RB

Vo

(a)

RLrπ

b1 kΩ 100 Ω

br ′

1 kΩ

b ′

C528 pF

π

Cμ

3 pF

RE 220 Ω

b erm

V ′

1 kΩCL22 pF

a1 a2 a3

28.96.30Cπ 3.41

22.0

0.479C 19.7

22.0

ns units

a3 = 621 ns 3

a2 = 827 ns 2

a1 = 70.6 ns

CL

(b)

c

= b e10.1 V ′

Ω

μ


16 Chapter 1

The poles of the BJT amplifi er of (a) are found by the Cochrun-Grabel method using the Rosenstark table in (b) to obtain the characteristic equation. The third-degree equation can be solved by computer or approximated by a lower-degree equation that retains an approximation of the dominant poles.

b erm

Vr RE

′

RB br ′

b ′

e

p

Begin with R of Cp in the fi rst column. With all the other Cs open, the resis-tance is found by the following steps. First, the equivalent circuit is Nortonized.

b erm

Vr

RB

′

b ′

RE

RERB RE+( )+br ′

br ′

e

p

Then the substitution theorem is applied and two branches are combined.

r

b ′

RE1 +

RB RE+ +

rm

br ′

e

p

The resistance is

R rR R r

R rE B b

E mπ π=

+ + ′( )+( )1



This has the form of Miller’s theorem, in which K = RE/rm. Rp = 54.8 Ω, and the resulting time constant is 28.9 ns.

For Cm, the equivalent circuit is shown below.

RE

πrb erm

V

RB

′

RL

b eV ′

b c′

+

–

br ′

Applying the b transform to RE results in the equivalent circuit:

( + 1) β

πr

b erm

V

RB

′RL

b eV ′

b c′

+

–

RE

br ′

The resistance at the b′ node to ground is

R r R r Rb b B e E′ = ′+( ) +( )⋅ +( )β 1

The collector current source is controlled by Vb ′e. From the base loop,

V Vr

r RV

rr R

b e bE

be

e E′ ′ ′= ⋅

+ +( )⋅⎛⎝⎜

⎞⎠⎟

= ⋅+

⎛⎝⎜

⎞⎠⎟

π

π β 1


18 Chapter 1

At the collector,

V RVr

Rr R

V K Vc Lb e

m

L

e Eb b= − ⋅ = − ⋅

+⋅ = − ⋅′

′ ′α

Current injected into the b′ node causes the voltage across b ′c to change by 1 + Vc /Vb′ = 1 + K. This Miller effect causes the voltage across the injecting current source to be larger by 1 + K times. This makes the effective resistance 1 + K times larger also.

Next, change the Norton circuit of the collector loop to a Thevenin source as shown below using the collector equation.

bR ′

RL

c

bKV ′

–

+

b ′

The voltage across Rb′ is now (1 + K) Vb′, making Rb′ appear (1 + K) times larger. This Miller resistance is in series with RL. Thus, the resistance sought is

R R K R r R r Rr

r RRb L b B e E

e

e ELμ β α= ⋅ +( ) + = ′+( ) +( )⋅ +( )⋅ + ⋅

+⎡⎣⎢

⎤⎦⎥

+′ 1 1 1

Substituting circuit values gives Rm = 6.57 kΩ and t = 19.7 ns.The time constant for a1 due to CL is RL·CL = 22.0 ns. For the a2 column, the

fi rst capacitance Cp is shorted, and R across b′c is again determined. With Cp shorted, Vb′e = 0, and the transistor current source is nulled. This simplifi es the resistance to

R C r R R Rb B E Lμ μ shorted( ) = ′+( ) +

which is 1.18 kΩ. The time constant is 6.30 ns. Next, Cp remains shorted as we fi nd the resistance across CL. It is RL, and t = 22.0 ns. The last entry in the a2



column is found by shorting Cm and fi nding the resistance across CL. The col-lector current source is now across the b′e branch, and the substitution theorem reduces it to rm. Applying rm||rp = re,

R C R r R r RL L e E b Bμ shorted( ) = +( ) ′+( )

This resistance is 160 Ω and t = 0.479 ns.The fi nal entry, for a3, is the resistance across CL with Cp and Cm shorted.

R C C r R R RL b B E Lπ μ, shorted( ) = ′+( )

This value is 155 Ω and t = 3.41 ns. The table is complete.Next, fi nd the an as follows:

a1 28 9 19 7 22 0 70 6= + +( ) =. . . .ns ns

a22 26 30 28 9 22 0 28 9 0 479 19 7 827= ( )( ) + ( )( ) + ( )( )[ ] =. . . . . . ns ns

a33 33 41 6 30 28 9 621= ( )( )( ) =. . . ns ns

The characteristic equation is therefore

621 827 70 6 1 03 3 2 2ns ns ns( )⋅ + ( )⋅ + ( )⋅ + =s s s.

This equation was solved by computer, producing real roots at

− − −2 83 11 6 198. , . ,MHz MHz MHz

A SPICE simulation shows a damped response due to the dominant real pole with magnitude roll-off of −3 dB at 2.7 MHz. The two slowest poles combine to yield an approximation bandwidth of 2.75 MHz.

If a computer is not used to solve the characteristic equation for the poles, some approximations can be made by ignoring higher-degree terms. By drop-ping the s3 term, two poles are found at 2.85 MHz and 10.7 MHz. By dropping the quadratic term also, the single pole is at 2.25 MHz, a 16% error. This error is acceptable for many pole estimates and leads to a simplifi ed version of the Cochrun-Grabel approach; instead of building a table, build only the fi rst


20 Chapter 1

column. That is, sum the open-circuit time constants for each capacitor and invert it for the radian pole frequency. The hard work is in fi nding Rp and Rm, but we have done that already, and the equations for them can be used for BJT analysis (and, for fi eld-effect transistors, with the BJT-to-FET transform) generally.

The fT specifi ed by transistor manufacturers is defi ned as the frequency at which b is one with the collector dynamically (ac) shorted to the emitter. Then Cm shunts Cp. This implies that

mfg f r C C r CTT

T= = ⋅ +( ) ≅ ⋅12πτ

τ π π μ π π,

The manufacturer’s fT for the transistor in the previous example is 300 MHz and bo = 99. For the single-pole BJT model (see Designing Dynamic Circuit Response, “Derivation of BJT High-Frequency Model”) fT is defi ned with Cm = 0 to make the resulting theory simpler. This should cause no problem if the manufactur-er’s fT and Cm (given as Cob) values are used to compute fb and fT as defi ned here. In most cases, fT is close enough already. In this example, the error is 0.6%.

The Cochrun-Grabel method produces only poles. One technique for deter-mining zeros begins by fi rst writing the nodal equations of the circuit. A fl ow graph is especially helpful here. Those transmittances that lead from input to output are examined for evidence of zeros.

Pole estimation is often applied to interstage coupling, to the pole formed by the load resistance of a common-emitter (CE) or common-base (CB) stage and the following CE stage input.

RC

Ic1

C

Cr Ic2 RL

RE

Vo

m

pp



The input impedance of the loading BJT stage Zi has branches through Cm and Zp.

Zi

ViRm

C

Ii

Vi

+

–

Vo

RL

Gm–

m

Consider fi rst the branch involving Cm. The circuit is idealized above to eliminate the effect of the Zp path. The BJT is represented by a transconductance ampli-fi er. Its output current, representing collector current, is shown fl owing into the amplifi er with value Gm · Vi = Vi/Rm. The input current to the amplifi er fl ows into Cm and is

IV V

sCsC V V

VR

VR

ii o

i oo

L

i

m

=−

= ⋅ −( ) = +1 μ

μ

Solving this Kirchhoff’s current law (KCL) equation for Vo, substituting it into the fi rst expression for Ii, and solving for Vi/Ii,

Zs R R C

RR R s K C

RK

iL m

L

L m v

L

vμ

μ μ=

+ ( )[ ]⋅+

+ ( )[ ]=

+( )⋅+

+1

1 11

1 1

Besides the Miller capacitance, RL is reduced by Kv + 1. For large voltage gain, this branch presents a nearly capacitive impedance.

The impedance through Zp is

Z r Rs R r R

si o e E

o T E e Eπ

ββ α τ

τ= +( )⋅ +( )⋅

⋅ ⋅ +( )( ) ++

11

1

For RE >> re and ao ≅ 1, Zip is the hf Zb(RE). If the series-peaking wn << wT, we can ignore the zero in Zip. The result is a shunt RC with Ri shunting


22 Chapter 1

tb/Ri ≅ tT /RE. Ri is large and usually presents negligible shunting. Consequently, Zip reduces to tT/RE. It shunts Zip so that

Z Z Zi i i= μ π

When the branches are combined, Zi as shown below results.

C

Zi

( + 1)Kv

RLKv+ 1

tTRE

RE

m

This simplifi es, under these assumptions, to the following circuit.

CZi ( + 1)KvtTRE

m

Unless the transistor is very slow (large tT) or RE is small (not much larger than re or less), the only signifi cant capacitance is the Miller capacitance. Therefore,

Zs K C

R r f fR

Ki

vE e o T

L

v

≅+( )⋅

>> >> <<+

≅11

11

0μ

β, , , ,

Another assumption of this equation is that the capacitance loading RL from the stage following it is negligible. If not, shunt capacitance across RL further reduces the impedance in series with Cm, making this a better approximation.

A more exacting estimate is based on Zi of the previous (more exact) network above. Let the elements be designated more generally as R1 in series with C1 shunting R2 in series with C2. Then,



ZsR C sR C

s C C s R R C Ci =

+( )⋅ +( )+( )[ ]⋅ +( )⋅( ) +[ ]

1 1 2 2

1 2 1 2 1 2

1 11

When element values are substituted, the zeros are at frequencies of 1/tT and 1/RL · Cm; the poles are at the origin, and 1/(R1 + R2) · (C1||C2) (where || is a math operator, not a topological designator). The capacitance C1 + C2 dominates Zi until 1/RL · Cm. The second pole causes Zi to appear capacitive out to fT.

INDUCTIVE PEAKING

Interstage coupling often degrades bandwidth due to parasitic reactances. For example, collector output capacitance shunts the input base capacitance of the next stage in the circuit shown below.

R

Ic1C1out C2in

C1out C2in+=C

The load resistor R is shunted by C = C1out + C2in. An unwanted pole is created at 1/R · C.

The addition of an inductor can extend the bandwidth by creating a series or parallel resonant circuit with a peak in the frequency or transient responses – hence the technique name of inductive peaking. Below are some series peaking circuits.


24 Chapter 1

The transfer function is not changed by exchanging R and C. In both cases, L is in series with C. The transfer function for series peaking has a quadratic pole factor,

VI

Rs LC sRC

o

i

= ⋅+ +1

12

This has a familiar quadratic-pole response. The basic parameters are

ω ζ ζnn

na LC RC

ba

RZ

ZLC

= = = = = =1 1 22 2

; ,

Usually, R is chosen to set the gain, and C is parasitic. This leaves L as the design parameter. For a desired z,

LR C

=⋅

⋅

2

24 ζ

Because L is in a (the s2 coeffi cient) only, the poles move with increasing L as shown below.

Ii RC Vo

+

–

(b)

L

Ii R C Vo

+

–

(a)

L

–1RC

L

jω

σ–2RC



It is worth noting that if R were varied instead, the pole locus would be as shown below.

1

R

jω

σ–2

RC

LC

And for increasing C, the direction of the root locus is vertical downward, split-ting along the real axis.

C

jω

σ–2

RC

When the poles become complex as L increases, pole radius wn shrinks and z decreases. The most desirable pole locations for a wideband amplifi er are in a range slightly off the real axis, near the critically damped pole location −2/RC. Here, wn is maximum and z is in a range that gives a desired response.

For variation in R, wn remains constant as z changes proportionally. Variation in C causes the most trouble. While z varies with the square root of C, wn varies inversely. Consequently, with C usually parasitic, control over its range of values is least, and though response peaking (in time or frequency) is not so much affected by ΔC, the risetime and bandwidth are. Causes for C, such as transistor process parameters and circuit-board layout, are signifi cant in control of pole radius.

How much improvement in bandwidth can series peaking offer? To deter-mine this, compare bandwidth improvement with the uncompensated RC circuit by expanding the meaning of the bandwidth reduction factor S to include


26 Chapter 1

bandwidth extension. Both defi nitions of S are useful here and are separately denoted as

S Sp RC

nbw

np

bw bw≡ ≡ =( )

ωω

ω ω,

1

Sn compares bandwidth with respect to pole radius; Sp compares it with the uncompensated RC circuit.

In the time domain, tr · wn has been used to express relative risetime. Com-parison against the risetime of the RC circuit also is a measure of improvement. The risetime improvement factor is

tt RC

tRC

r

r

r

( )≅

⋅2 2.

All of these performance indicators are combined with those already derived in Dynamic Response Compensation, “Optimization . . .”, in the following series-peaking summary table.

z L wnww

bw

n

wbw

pMp,% tr · wn

tRC

r

2 2. ⋅

1.00 R C2

42/RC 0.644 1.288 0 3.36 0.765 critical damping

0.866 R C2

31.73/RC 0.786 1.361 0.433 2.73 0.717 MFED

0.707 R C2

21.41/RC 1.000 1.414 4.32 2.15 0.692 maximally fl at amplitude

0.500 R2C 1/RC 1.272 1.272 16.3 1.64 0.746 f = 60°

For z = 0.5, the poles are at a 60° angle and a = 1/RC, the same as the single-pole case. From the root-locus plots above, at critical damping, both poles are at −2/RC and have twice the pole radius of a single-pole RC circuit. As L varies,

ω ωω

ζ ζbw bw

np n

pS S

⎛⎝⎜

⎞⎠⎟

= ⎛⎝⎜

⎞⎠⎟ ⋅ ⋅( ) ⇒ = ⋅ ⋅2 2



By adding L for series peaking, the critically damped (z = 1) bandwidth increases by 36% and the risetime by 28%. This is a signifi cant improvement caused by the addition of one component, but greater improvement is possible.

Example: Series Peaking

L1R470 ΩiZ μC

πC

L

c1I πr

L2R200 Ω

3 pF

c2I

ER20 Ω

= 50 nsτβ

The amplifi er stage output is loaded by the input impedance of a CE stage. The CE transistor has tT = 500 ps and bo ≅ 100. The collector capacitance to ground of the fi rst BJT is negligible. A MFED response is desired.

The fi rst step is to fi nd the input impedance Zi of the loading stage. The poles involved in inductive peaking will be in the hf region of the CE BJT stage. The emitter branch hf capacitance is 500 ps/20 Ω or 25 pF. Zp in series with it is negligible. The voltage gain is about

RR

L

E

2 10=

and the Miller collector capacitance is 11 · (3 pF) = 33 pF. Because RE is so small, tT /RE is signifi cant. The collector output resistance, taking into account the Miller effect, is less than 20 Ω. The capacitance in series with L is thus


28 Chapter 1

Ci ≅ + =25 33 58pF pF pF

The uncompensated bandwidth is

fRC

bw uncomppF

MHz( ) =⋅

≅⋅( )⋅( ) =1

21

2 470 585 8

π π Ω.

And risetime is

t RC tf

r rbw

≅ ⋅ = ≅ =2 2 600 35

60..

ns or ns

From the inductive peaking table, for MFED response,

LR C= ⋅ ≅ ( ) ⋅( ) =

2 2

3470 58

34 3

Ω pFH. μ

The value of R = RL assumes negligible series resistance in Zi. Each path in Zi has about 20 Ω. Zi becomes resistive at 1/RL · Cm or 265 MHz. This is about 50 times larger than fbw(uncomp), and the assumption that Zi is purely capacitive over the frequency range of interest is valid.

The compensated bandwidth (from the table) is 1.36 times higher, or 7.9 MHz, and the risetime is 43 ns. The series resonance is at fn = 10 MHz.

An alternative to series peaking is shunt peaking, as shown below. The addition of L in series with R places it in parallel with C and creates a parallel resonance. For a step of input current, most of it charges C at fi rst because current does not change instantaneously in an inductor. Consequently, C charges faster and response speed increases.

Ii

R

C Vo

+

–

L



The transfer function of the shunt peaking circuit is

VI

Rs L R

s LC sRCo

i

= ⋅ ( ) ++ +

112

The addition of a zero over series peaking improves response speed but also peaks the response more. To compare shunt with series peaking, we need formulas for the performance parameters of a two-pole, one-zero circuit. We now digress to derive them generally and then apply them to shunt peaking.

The two-pole, one-zero transfer function can be generally expressed in terms of tn = 1/wn and Q as

VI

RsQ

s Q so

i

n

n n

= ⋅ ++ ( ) +

ττ τ

112 2

In narrow-band amplifi er terminology,

Q ≡ 12ζ

This quantity quantifi es the amount of peaking and occurs frequently in resonant-circuit equations. The time constant of the zero of Vo/Ii is

τ τ ττz n

z

n

Q Q= ⋅ ⇒ = ⎛⎝⎜

⎞⎠⎟

Bandwidth is found in the usual way by setting the magnitude of Vo/Ii to 1 2 . The general result is

ω ωbw nQ

QQ

Q= − + + − +⎛⎝⎜

⎞⎠⎟

+11

22 1

12

2 12

22

2

2


30 Chapter 1

The overshoot, Mp, is expressed in z as

M p = ⋅ −−

− − −⎧⎨⎪

⎩⎪

⎫⎬⎪

⎭⎪+ −( )− − −1

2 1

32

12

1 12

1

ζζζ

π ζ ζζ

ζexp . cos tan sin⎛⎛

⎝⎜⎞

⎠⎟⎡

⎣⎢

⎤

⎦⎥

where 3p/2 = 270°.The unit-step response for z < 1 is

v t e tstepw t

nn( ) = −

−⋅ − + + −⎧

⎨⎪

⎩⎪− − −1

1

2 11

12

2 1 12

ζ ζω ζ ζ ζ

ζζ sin cos tan

⎫⎫⎬⎪

⎭⎪

⎛

⎝⎜⎞

⎠⎟

The 10% and 90% times are found by numerical computer solution for shunt peaking as tr · wn . This is a convenient representation since wnt is the indepen-dent variable.

For z = 1, the poles are repeated, and the step response is

vpz

p t estepp t= −⎛

⎝⎜⎞⎠⎟⋅ ⋅ −⎡

⎣⎢⎤⎦⎥⋅ + =− ⋅1 1 1 1, ζ

This function also has no closed-form solution and is numerically solved by computer.

We now apply these general results to shunt peaking and Vo/Ii, where the zero is

zL Rz

n= = = ⋅ ⋅1 12

τζ ω

and the repeated poles have a frequency of

22

pRC

n= = ω

It then follows that, when z = 1,

pz

= 12



and vstep reduces to that for shunt peaking:

v t estep ntn= − ⋅ ⋅ −⎛

⎝⎞⎠ ⋅ +−1

21 1ω ω

The values of tr · wn are numerically computed from this equation.A table similar to that for series peaking can now be constructed for shunt

peaking.

z Qww

bw

n

wbw

p Mp,% trwntRC

r

2 2. ⋅f

1.00 0.500 0.786 1.572 0 3.071 0.699 0°

0.866 0.577 1.086 1.881 0.620 2.319 0.609 30°

0.707 0.707 1.554 2.198 6.70 1.559 0.502 45°

0.500 1.000 2.279 2.279 29.8 0.940 0.428 60°

Shunt peaking is faster than series peaking for the same pole parameters but is less damped in response. It achieves an 88% increase in bandwidth over the RC circuit and 39% decrease in risetime for a MFED pole response. Comparing the shunt and series peaking tables directly can be misleading, however. A pole angle of, say, 30° is not an MFED response for shunt peaking because of the zero. The values of z for MFED and maximally fl at amplitude (MFA) responses must be derived as in Designing Dynamic Circuit Response, “Graphical Representa-tion . . .”. For an MFED response, z = 0.881, and for MFA, z ≅ 0.777. These values are somewhat higher than those without the zero.

L1 L2a b

c

(a)

M

L1a b

c

(b)

–M

+ M L2 + M

Greater speed improvement can be achieved by using a T-coil (a). This is a transformer with controlled coupling and a common connection at c. An equivalent circuit is shown in (b) where the polarity of coupling determines the


32 Chapter 1

polarity of the mutual inductance −M to terminal c. With the coupling as shown,

L L L M L M L L Mab= = +( ) + +( ) = + +1 2 1 2 2

The addition of −M in the equivalent circuit produces the correct self-inductances:

L L M M L L L M M Lac bc= +( ) − = = +( ) − =1 1 2 2,

If terminals a and b are shorted, the inductance from a or b to c is

L L M L M Mab c, = +( ) +( ) −1 2

Let the mutual inductance be signed. Then the coupling coeffi cient is always positive and is

kM

L L=

⋅1 2

The use of the T-coil for bandwidth extension has resulted in the general form of the bridged T-coil circuit, shown below.

L1

RL

L2

s

Rs

CB

CL

ZL

Zin

Vo



The coil is terminated in R, but the load is connected to the centertap. A general load,

Z sL RsC

L s sL

= + + 1

(or series RLC) is similar to the input impedance of BJT stages. The equivalent circuit is shown below.

L1

R

L

+ M L2 + M

s

Rs

CB

CL

–M

Vo

At 0 Hz, the input impedance of the T-coil is R. Because of the bridging capaci-tor CB, at high frequencies it is also R. For a given ZL and by proper choice of L1, L2, M, and CB, Zin = R and is independent of frequency. For this circuit behav-ior, the resulting design equations are

LC

R R RR C LLs s L s1 2

2

41

14

= ⋅ +⎛⎝⎜

⎞⎠⎟

⋅ +( ) − −ζ

LC

R R LLs s2 2

2

41

14

= ⋅ +⎛⎝⎜

⎞⎠⎟

⋅ +( ) −ζ

MC

R R R R LLs s s= ⋅ − − +( )⎛

⎝⎜⎞⎠⎟

+4

14

2 22

2

ζ


34 Chapter 1

CC R

RB

L s= ⋅ +⎛⎝

⎞⎠16

12

2

ζ

In addition to these design equations, the equivalent inductor element values are

L MRC

R R LLs s1

2+ = ⋅ −( ) −

L MRC

R R LLs s2

2+ = ⋅ −( ) −

L R C LL s= −2 2

The transfer function has two poles at

pRC

jRCL L

1 2

224 4

1, = − ± ⋅ −ζ ζ ζ

The form of transfer function is the same as for series peaking but with twice the speed improvement! For MFED response, wbw/p = 2.72, nearly three times better than the original RC circuit. The greatest improvement is 2.83 for an MFA response.

For ZL = 1/sCL, the transfer function for the load is

VI

Rkk

R C s RC s

o

iL L

= ⋅⋅ −

+⎛⎝ )⋅ + ⋅ +

114

11

12

12 2 2

Ckk

C L R C L LLk

B L L= ⋅ −+

⎛⎝⎜

⎞⎠⎟⋅ = = =

⋅ +( )14

11 2 1

21 2, ,

As k increases, the pole angle decreases for complex poles. With perfect cou-pling, k = 1, and the s2 term is zero, leaving a single-pole response but with twice the bandwidth of a simple RC circuit. This is a simpler, lower-performance T-coil



circuit with no bridging capacitance and with L1 = 4 · L2. MFED response is achieved when k = 1/2, a relatively loose coupling not hard to implement. Then CB = CL/12, L1 = 3 · L2, and L = R2 · CL. A balanced T-coil (L1 = L2) that meets the above conditions has no coupling between the coils, CB = CL/4, and the pole angle is 60°. L1 > L2 is necessary to meet these conditions with a capacitive load.

The basic theory of T-coils, including the full derivation of the above equa-tions (and others), was originally worked out at Tektronix by Robert I. Ross and Carl Battjes (1982), inventor of T-coil compensation. Subsequently, Peter Staric and Erik Margan presented the derivation in Wideband Amplifi ers (2006).

Even greater bandwidth improvement is possible by taking advantage of the constant-resistance input of the T-coil circuit. Series peaking can be cascaded in front of the T-coil, as shown below.

L1

R

L2

CB

Cin

Ls

Ii Cout

M

Vo

The input and output capacitances of the uncompensated circuit are separated and become part of different peaking circuits. Because the interstage coupling satisfi es the requirement for series peaking, the bandwidth improvement of each circuit remains unchanged. Thus the total improvement is the product of the individual improvement factors.

Amplifi ers with bandwidths under 100 MHz usually have had T-coils con-structed as tapped cylindrical coils wound on a plastic bobbin. The magnetic path is through air and plastic. For higher frequencies, a common T-coil is made of a bifi lar-wound loop of magnet wire. The two wires are twisted together and then formed into a loop, or circuit-board traces can be spiraled on opposite


36 Chapter 1

sides of the board and connected at the center via plated-through holes. Two traces can be run next to each other to form coupled inductors. For very-high-speed circuits, integrated circuit (IC) bonding wires have even been used to form T-coils.

CLQ2

RL

Q1

VCC

VB

RB

Vo

An inductive peaking circuit used in ICs, sometimes referred to as “emitter peaking,” realizes a shunt inductance by the high-frequency gyration of a BJT base resistor. The emitter appears inductive. (See Designing Dynamic Circuit Response, “High-Frequency Impedance Transformations.”) The adjustment of RB adjusts the emitter inductance RB · tT.

Example: T-Coil Compensation

The circuit of the previous example is T-coil compensated. The T-coil formulas are applied directly. The loading is CL = 58 pF, and Rs = Ls = 0. Also, R = RL = 470 Ω. For MFED response, z = 0.866. The results are

L L M CB1 2 4 3 2 1 4 8= = = =. , . , .μ μH H pF

From the equation for k, the coupling of the inductors is k = 0.5. This is loose coupling and is easily implemented. The bandwidth has improved to 15.8 MHz and risetime to approximately 22 ns.



BOOTSTRAP SPEED-UP CIRCUIT

How can the speed of an amplifi er be increased without increasing its power dissipation? Amplifi er bandwidth can be extended by a simple technique that requires no inductors or complicated adjustments. In its simpler form, a collector- or drain-loaded transistor amplifi er, as shown below, has a single-load resistor, RL, followed by a buffer amplifi er, usually an emitter- or source-follower.

RL

Q2

Q1

+V

The buffer stage keeps the output from directly loading RL by providing current gain and approximately a ×1 voltage gain. This two-stage cascaded amplifi er is typical in high-speed circuit design as a place to start before increasing amplifi er “speed” (bandwidth).

What mainly can limit speed is the capacitance, Co, at the collector node of the fi rst stage. It forms a time constant with RL that slows the dynamic response. To increase speed, it is possible to introduce various inductive peaking tech-niques. However, for IC and some discrete design, inductors are problematic. A speed-up technique that uses capacitance instead is the bootstrap speed-up circuit, shown below, where Q 1 has been replaced by a current source, i, and the Q 2 stage by an ideal ×1 buffer amplifi er. RL has been split into R1 and R2, and a bootstrap capacitor, C, added between the output and the split-RL node.


38 Chapter 1

The idea behind this circuit is that if the voltage at the top of R1 can track the voltage at the bottom of R1, the voltage change across R1 will be zero. Then none of i will be diverted into the load resistance. With all of i fl owing into Co, it charges faster and the circuit response is quicker. In effect, C bootstraps the voltage across R1 to accomplish this, and the buffer amplifi er output has the needed current drive to provide R2 current.

To analyze the dynamic response of this circuit, the s-domain (pole-zero) expressions need to be derived. The full analysis takes some algebraic effort. To provide further insight into the circuit and guidance for checking the full result later, a simpler analysis omits Co. By setting Co = 0, the output-node voltage is

v i R RsC

vR

R sCv vo o1 1 2

2

21

11

= ⋅ +⎛⎝⎜

⎞⎠⎟

+ ⋅+

⎛⎝⎜

⎞⎠⎟ =;

After some algebraic simplifi cation, this becomes

v i RR

sR Cv

sR CsR C

o1 12

2

2

21 1= ⋅ +

+⎛⎝⎜

⎞⎠⎟

+ ⋅+

⎛⎝⎜

⎞⎠⎟

Then the fi rst-stage amplifi er gain, a transresistance (current in, voltage out), is

vi

RR

sR CsR C

sR C

R R s R R Co =+

+

−+

= +( )⋅ [ ]⋅ +( )1

2

2

2

2

1 2 1 21

11

1

R2

R1

V1

V2

V

× 1

oC

C

i

o



From this result, RL = R1 + R2 is the static gain, followed by a zero at z = −1/(R1||R2) · C. The absence of a pole is due to bootstrapping. The pole formed by R2 and C is cancelled by the ×1 buffer gain. If its gain were a value of K other than one, a fi nite pole factor would appear at s ·(K − 1) · R2 · C + 1.

Now, include Co in the analysis such that Co ≠ 0. Then the circuit can be modeled as shown below. The input current source is omitted but attaches to the output node, at v1. The two-loop circuit reduces to a single loop by Theve-nizing vo, C, and R2, as shown in the second circuit. Then superposition of the two sources, vo and i, results in the following two equations:

v vsR C

sR CsR C

s R R CC s R R C R Co

o o1

2

2

22

1 2 1 2 211= ⋅

+⎛⎝⎜

⎞⎠⎟⋅ +

( ) + +( )⋅ +[ ] ++⎛⎝⎜

⎞⎠⎟ =

10, i

v isC

R R sC

i R Rs R R C

s R R CC s R

o

o

1 1 2

1 21 2

21 2

11

1

= ⋅ +( )⎛⎝⎜

⎞⎠⎟

= ⋅ +( )⋅ ( ) ++ 11 2 2 1

0+( ) +[ ] +

=R C R C

vo

o,

R1

R1

R2

V1

V1

vo

C

Co

Co+sR2 1C

sR2C

+sR2 1C

R2

⎛⎝

⎛⎝

.+

−

Vo

+

−


40 Chapter 1

The fi rst equation simplifi es quickly to

v vsR C

s R R CC s R R C R Cio

o o1

22

1 2 1 2 2 10= ⋅

( )+ +( )⋅ +[ ] +⎛⎝⎜

⎞⎠⎟ =,

Applying the buffer condition, vo = v1, and by superposition,

vi

R Rs R R C

s R R CC s R R Co

o o

= +( )⋅ ( ) ++ +( ) +1 21 2

21 2 1 2

11

The bootstrap capacitor, C, provides for the additional zero. Without it (C = 0), the uncompensated circuit pole remains at −1/(R1 + R2) · Co, as in the uncom-pensated amplifi er. The design question is now one of determining the optimal value of C and the split between R1 and R2.

The contour (not root-locus) plot of the poles of this circuit is shown below. C appears only in the quadratic term, leading to a locus that varies with increas-ing C as shown.

σ

+

+−

−

−

×

×

jwC

1⏐⏐R1( R2 ·C)

− 1+R1( R2 ·Co)

− 1⏐⏐R1( R2 ·C2· )

The conjugate poles are marked with their polarities to show that the positive pole originates at the center of the pole-pair circle, −1/(R1 + R2) · Co (the pole location of the uncompensated amplifi er), and the negative pole at −∞. The contour plot itself begins at the frequency of the zero, −1/(R1||R2) · C, and at the circle center. As C increases, the poles move toward each other and meet at −1/2(R1||R2) · C before splitting off the real axis and eventually terminating at



the origin for excessively large (infi nite, shorted) C. For equal poles on the real axis,

2 1 212 1 2R R C R R Co( )⋅ = ⋅ +( )⋅

from which the design constraints are obtained: R1 = R2 and C = Co.Optimal amplifi er response usually has the poles off the real axis for a com-

promise between time- and frequency-domain response performance. For poles alone, the MFED angle is 30°. The relevant formulas are as follows. The damping factor is

ζ =⋅

= ⋅+( )⋅

( )⋅b

a

R R CR R C

o

212

1 2

1 2

where the pole angle is

φ ζ= −cos 1

The pole radius is

ωnoa R R CC

= =1 1

1 2

Then for a pole angle of f = 30°, z = cos(30°) = 3/2 and

R R CR R C

o1 2

1 2

3+( )⋅

( )⋅=

Given R1, R2, and an estimate for Co,

CR R C

R Ro=

+( )⋅⋅( )1 2

1 23

For R1 = R2, then

C Co= ⋅43


42 Chapter 1

Co is an undesirable parasitic circuit element, is typically small, and takes on a small range of possible values. Because of its only approximate value, C might need to be adjustable to tune the pole angle for optimal response.

Because of its small size, C is also small, approximately the value of Co. Con-sequently, small-variable-C methods might need to be applied. One simple discrete-circuit approach is to use what used to be called a “gimmick.” Twist a length of insulated wire, strip and solder-coat one pair of ends as C terminals, then snip the length of the pair for optimal C. Varnish or glue C to retain its geometry and its C value. This works for relatively slow high-speed circuits. Better methods can also be applied. If approximate dynamic behavior is ade-quate, or by using a response trim elsewhere, no adjustment is needed. In this case, a circuit-board or IC capacitance, though approximate, can be suffi cient.

SOURCE-FOLLOWER COMPENSATION

Common-source (CS) stages are often used at the input of instrument amplifi ers to minimize resistive loading. Unlike their BJT counterpart (the CC), FET CGS is typically much smaller than Cp of BJTs. Consequently, the Zp term of Zb (described in Designing Dynamic Circuit Response, “High-Frequency Impedance Transformations”) cannot be ignored as it usually can for the BJT. Applying the transformation for FETs and including the effect of CGD,

ZsC

Zs

s sCg

GSS

T

T GD

= + ⋅+⎛

⎝⎜⎞⎠⎟

⎡⎣⎢

⎤⎦⎥

1 1 1ττ

where tT = rm · CGS. The equivalent circuit is shown below.

CGD

Vi

+

–

VGS+ –

CGS

Zs

Vo

VGSrm



It is transformed by applying the substitution theorem to result in the circuit shown below.

Vi

+

–

Zs

Vo

CGS

CGD

VGrm

VSrm

Then Norton-to-Thevenin conversion of the current source results in the fol-lowing circuit.

Vi

+

–

Zs

Vo

CGS

rm

Vi

+

–

CGD

For a capacitive load of CS, Vi drives a capacitive divider that causes an input voltage step to immediately rise to a fraction of the step amplitude,

CC C

GS

GS S+

and then continues to rise exponentially, due to rm, to the input step value. The transfer function of the above circuit is

VV

sr Csr C C

ss r C

o

i

m GS

m GS S

T

T m S

=+

+( ) +=

++( ) +

11

11

ττ

The pole is less than the zero, resulting in the response of a phase-lag circuit. The initial response step is p/z with a time constant of rm · (CGS + CS). The


44 Chapter 1

response can be compensated by adding a phase-lead circuit at another stage in the amplifi er.

A second anomaly of the CS is its input impedance. From Zg, the gyrating factor can be expressed in topological form as

Zs

sZ

sS

T

TS

T

⋅+⎛

⎝⎜⎞⎠⎟ = ⋅

− +( )τ

τ τ1 1

1 1 1

Substituting ZS = 1/sCS, Zg reduces to

ZsC sC sC C sC

gGD GS S

T

S S

= + − −⎛⎝⎜

⎞⎠⎟

⎛⎝⎜

⎞⎠⎟

1 1 1 1τ

A more useful form is

ZsC

s C C Cs C C

sC s C C

gGD

GS S T GS

GS S T

GD GS S

=+( ) +⎛

⎝⎜⎞⎠⎟

=( )

⎛⎝⎜

⎞⎠

1

1 1

2

ττ

⎟⎟ − ⋅+

−( )

⎛⎝⎜

⎞⎠⎟

rC CC C s C C

mGS S

GS S GS S

1

This equivalent hf gate impedance is shown below and is compensated by the method used to compensate the CC, that of shunting the gate with a series RC, which produces a purely capacitive input. (Keep in mind that || is a mathemati-cal operator, not a topological descriptor.) The values of the compensating elements are derived from the expression for Zg.

(a)

Zg CGD CS

τ TCS

– CS

CGS

(b)

CGD CGS CS⏐⏐

CGS CS⏐⏐– ( )

CGS CS⏐⏐– rm CGS CS( )+

–



A source follower is usually used to prevent loading of a high-impedance source. If the source impedance is resistive, then it forms an uncompensated voltage divider with Zg. This can be compensated by introducing a shunt RC in series with the input.

Vi

+

–

Ri

C

R2

+VDD

C

R

R1

C1

CSR

Vo

It forms a compensated divider with Zg, resulting in a resistive input.The last CS problem to be considered is distortion due to large-signal effects.

When a large-amplitude square-wave is applied to the compensated CS, CGS and rm both change signifi cantly between levels. If C1 is adjusted for compensation of the positive transition, then for the negative transition, rm and CGS increase causing tT to increase. An increase of CGS increases the step fraction, causing negative overshoot or undershoot. The transfer function is also affected. Both pole and zero decrease, but with signifi cant CS, the pole decreases less. Conse-quently, p/z decreases, causing the compensator to overcorrect and produce undershoot. FETs with large CGS have reduced undershoot, and if they also have a large tT, undershoot error diminishes more quickly. Similarly, FETs with large pinch-off voltages have less rm variation with VGS.

Example: CD Input Buffer Compensation

A source-follower FET has a transconductance of 50 mS (rm = 200 Ω), CGS = 6 pF and CGD = 2 pF. Maufacturer data sheets give FET capacitances as

C C C C Ciss GS GD rss GD= + =,


46 Chapter 1

With a load capacitance of CS = 10 pF, a series RC shunting the gate compensates the FET input. To calculate their values, tT is needed:

τT m GSr C= ⋅ = 1 25. ns

Then, from the above circuit diagram,

R rC CC C

mGS S

GS S

= ⋅+⎛

⎝⎜⎞⎠⎟

= ⇒853 820Ω Ω,

C C CGS S= = ⇒3 75 3 9. .pF pF

The input now is a shunt RC, where Cg = C + CGD = 5.9 pF and R2 = 1 MΩ. To compensate this pole, a shunt RC is placed in series with the input (as in the fi gure above). In applications in which the input comes from a probe or passive attenuator, the compensating RC is in the probe body so that the probe itself contains the top part of the voltage divider. For a 10 MΩ input,

R CR C

RCg g

1 12

1

99

0 66= = = =M pFΩ, .

For such large R1, C1 is an extremely small capacitance. The R1 resistor probably has more parasitic shunt capacitance than the value C1. As a consequence, prac-tical values of capacitors make it infeasible to try to compensate the input divider. That is why, for example, oscilloscope vertical inputs are marked with labelings such as 1 MΩ, 22 pF.

The following circuit takes an alternative approach to common-drain (CD) compensation. It has two paths: the main path through the FET and a compen-sation path through the CB BJT. The FET path transfer function is given by Vo/Vi, whereas for the compensation path, C forms a divider with Zp/(b + 1). The BJT-path voltage gain is

BJT FET

FET

VV

sr Csr C C sr C C

o

i

m

m GS S e

= ⋅⋅

⋅ +( ) +[ ] ⋅ +( ) +[ ]α

π0

1 1



The paths add to produce the total transfer function. Both paths share the pole with time constant

r C C r Cm GS S T m SFET FET FET⋅ +( ) + +τ

Then if the BJT time constant

r C C r Ce T e⋅ +( ) = + ⋅π τ BJT

is much smaller than that for the FET path, its pole can be ignored and the transfer functions of the paths added:

VV

s r Cs r C

r Co

i

T o m

T m ST e≅ +( ) +

+( ) ++ →τ α

ττFET FET

FET FETBJT

11

0,

For fl at response, the time constants are equated and

α αo S S oC C C C⋅ = ⇒ ≅ ≅, 1

For step inputs with fast edges, the voltage differentiation of C can cause cur-rents that exceed IE and drive the BJT into cutoff.

Vi

+

–

+VDD

CS

Vo

C

–VB

IE


48 Chapter 1

EMITTER COMPENSATION

An impedance in series with the emitter (or source) of CB and CE (or CG and CS) amplifi ers creates series feedback (see Designing Amplifi er Circuits, “Nonin-verting Feedback Amplifi er Examples”) and can improve speed. Compensation networks can be connected to the emitter node that correct for speed limita-tions at the collector. The fi gure shows a CB stage with capacitive output loading.

A series RC is placed in parallel with RE to provide correction. In the lf region (or for tT → ∞), the transfer function is

VV

Rr R

o

i

L

e E

= ⋅+

α ⋅ +( )⋅ ++( )⋅ +( ) +[s R R C

sR C s R r R CE

L L e E

11 1

For compensated response, the zero cancels the collector pole at frequency 1/RL · CL, leaving a much higher-frequency pole. For a fl at frequency response, the compensating elements must have the values

Vi

+

–

+VCC

VB

Vo

CL

R

C

RE

α

RL



R R R C CL E L= − =,

and for bandwidth extension,

R r R C R Ce E L L+( )⋅ << ⋅

For re << R and RE, then R << RL.

Vi

+

–

RE

re

CLRL

Vo

R

C

ib

β ib

Compensation of CE (or CS) amplifi ers is similar. In the circuit shown above, a similar network is connected to the emitter, resulting in a negative Vo/Vi. In both cases, transistor reactances have been ignored, and the resulting equations are useful for amplifi ers for which the output pole is below fb.

Analysis in the hf region uses the hybrid-p BJT model (and its extension to FETs). The CB stage has the advantage over the CE of no Miller effect. However, Zp forms an uncompensated voltage divider with RE, requiring an additional shunt CE around RE for compensation. At the output, Cm contributes to CL.

The CE suffers from the Miller effect, the cause of its dominant pole. Also, the input impedance includes a hf-gyrated emitter impedance. Networks in the


50 Chapter 1

emitter circuit that compensate for output poles have the side effect of creating input anomalies. To design a fast amplifi er with CE input, the Miller effect must be minimized and input impedance controlled. The Miller effect is essentially eliminated by following the CE with a CB (thus creating a cascode) or operating the CE as a shunt-feedback amplifi er.

First, consider the input side of the CE by assuming a cascode confi guration. This simplifi es analysis and allows us to ignore Cm for a while and regard the CE as a transadmittance amplifi er.

Vi

+

–

RE

re

CLRL

Vo

R

C

ib

β ib

The transresistance method (now generalized to the transimpedance method) applies in the hf region, using the hf BJT model. CE output current is b(s)·Ib(s). The transadmittance is derived from the equivalent circuit, shown above, and is

IV

s IV

sZ

ss Z

s Ys

Yo

i

b

i b EE

TE=

( )⋅= ( ) = ( )

( ) +[ ]⋅= ( )⋅ =

+⋅

β β ββ

ατ1

11

Because of a(s), the emitter network admittance YE must have a (stT + 1) factor to cancel hf effects. A simple compensation is to let ZE be a shunt RC:

ZR

sR CE

E

E E

=+ 1



Then,

IV R

sR Cs

o

i E

E E

T

= ⎛⎝⎜

⎞⎠⎟ ⋅

++

1 11τ

The response is fl at when

R CE E T⋅ = τ

In the hf region, the input impedance of the CE is

Z s Zs

sR

sR Cb E

T

T

E

E E

= ( ) +[ ]⋅ =+⎛

⎝⎜⎞⎠⎟ ⋅

+⎛⎝⎜

⎞⎠⎟

β ττ

11

1

When the compensated tT condition is applied,

Zs R sC

bT E b

= ( ) =1 1τ

The input is a capacitance of value Cb = tT/RE = CE.In the base circuit, Cb forms a pole with the base node resistance. A more

complete hf model includes rb′ and Cm at the internal (b′) base node, shown below.

Vi

+

–

RB

rb′

Cμ

ZE

Ie( )sα


52 Chapter 1

A general expression for the transadmittance is

IV

II

IV

VV Z

sCZ

sCZ

o

i

o

e

e

e

e

i E

E

= ⋅ ⋅ ≅+

⎛⎝⎜

⎞⎠⎟

⋅ ⋅+( )⋅

+( )⋅

ββ

β

β

μ

μ

11

11

11 EE S

E S S E

R

Z R s R Z C

+

=+( ) +

⋅+( )⋅[ ]⋅ +

ββ β μ1

11 1

where b is bhf = 1/stT and

R R rS B b= + ′

When emitter compensation is added – that is, when ZE and compensated tT are applied – then

ZR

sE

E

T

=+τ 1

and the transadmittance reduces to

IV R sR R C

o

i E S T E

= ⋅ ( ) +[ ] +1 1

1τ μ

In the low-frequency (lf) region, for Ii = Vi/RB,

KII

RR r R

io

io

B

S o e E

= = ⋅+( ) + +

αβ 1

The hf model has ao = 1 and re = 0 Ω. For dominant RE the lf current gain is then

KRR

iB

E

≅

High-speed amplifi ers are usually analyzed in terms of current gain because the input variable to a stage is usually a current. The low input-resistance cascode



CB effectively has a current input. The input to a CE is usually the collector of another transistor, modeled as a current source. The Thevenin voltage source input of the above circuit is changed to a Norton equivalent input by setting

V I Ri i B= ⋅

Then Vo/Ii is used to express current gain as

II

IV R

KsR R C

o

i

o

i B

i

S T E

= ≅ ( ) +[ ] +τ μ 1

Ii RB

rb′Cμ

ZE

Ie( )sα

Both Vo/Ii and Io/Ii are approximate because the path to the output through Cm is ignored. It introduces a right half-plane (RHP) zero at 1/RE · Cm. This fre-quency is usually much higher than the others and can be ignored. The passive path through Cm causes an output response to occur sooner than the inverted response of the active path. This passive path current is the cause of preshoot in the output step response. Instead of rising, the step fi rst dips negative.

Preshoot


54 Chapter 1

The effect of rb′ and Cm is to degrade speed. Without them, the time constant of the pole in Io/Ii is at

RR

KBT

Ei T⋅ = ⋅τ τ

Given Ki by design choice, there is an optimum value of RB that minimizes the pole time constant, which can be written in terms of Ki. By multiplying out the pole time constant in Io/Ii and setting its derivative to zero,

ddR

K R Cr K

Rr C

Bi T B

b i T

Bb⋅ + + ′ + ′⎛

⎝⎜⎞⎠⎟ =τ τ

μ μ 0

The optimum RB is

optimum RK r

CB

i T b=⋅ ⋅ ′τ

μ

For this value of RB, the current-gain pole has a time constant of

Kr CK

i Tb

i T

⋅ ⋅ + ⋅′⋅⋅

⎛⎝⎜

⎞⎠⎟

ττ

μ1 2

A CE with a lf voltage gain of Kv has an effective Cm of Kv + 1 times, due to the Miller effect. The optimum RB and pole time constant are modifi ed by multi-plying Cm by Kv + 1.

If Cm is located at the external base node (on the outside of rb′), as in the previous circuit diagram, the current gain is

II

Ks K R C s R R C r R

Ks K R C

o

i

i

i T B B T E b T E

i

i T B

≅ ( ) + +( ) + ′[ ] +

= (

2

2

1τ τ τ

τ

μ μ

μ )) + + + ′( )[ ] +s R C K r RB i T b Bμ τ 1 1



Again, the RHP zero has been ignored. The CE input now consists of two cas-caded RC integrators. The minimum z is

minζ ττ

= + ′ =⋅

1rR K

b

B

n

i T

Pole separation is typically not signifi cant enough to approximate the response by a dominant single pole since fast amplifi ers have values of RB not very differ-ent from rb′. Consequently, the rb′ term in Io/Ii cannot be ignored. The value of RB at maximum pole radius occurs when the poles are repeated and z = 1. This results in a fourth-degree equation in RB. The optimum RB can be approximated by assuming independence of the time constants of the RC integrators. Then fastest response occurs when their time constants are equal, or

R C rK

RB b

i T

B

⋅ = ′⋅⋅⎛

⎝⎜⎞⎠⎟μ

τ

Solving for RB gives

optimum RK r

CB

i T b≅⋅ ⋅ ′τ

μ

Interestingly, this result is the same as the previous optimum RB. Whether Cm is largely internal or external to the base does not strongly affect the optimum RB value.

Peter Staric and Erik Margan have systematically developed wideband amplifi er emitter compensation in Wideband Amplifi ers (2006).

CASCODE COMPENSATION OF THE COMMON-BASE STAGE

Consider the cascode CB stage. Above fb of the CB transistor, base resistance is gyrated at the emitter to an inductance that resonates with the output capaci-tance, Co, of the CE shunting the input to the CB. This shunt RLC forms a paral-lel resonance with


56 Chapter 1

ζ τ=⋅

⋅ = ⋅⋅

12

12R

LC R C

T

B o

where RB is the CB base resistance. For a BJT with fT = 300 MHz, Co = 3 pF and RB = 100 Ω, z = 0.665 for a pole angle of 48°. With a transistor twice as fast, the pole angle is about 60°. This resonance can cause oscillation because Co is due largely to Cm of the CE and is connected to the base. The CE provides the gain that causes oscillation.

This resonance can be damped by adding resistor RS in series with the emitter of the CB, isolating it from Co. The series damping required for MFED response is 77 Ω. Typically, re′ is 1 Ω, far less than the resistance required. A series resis-tance damps the resonance but also creates an uncompensated voltage divider with the CB-gyrated base impedance. In addition, it causes voltage gain at the collector of the CE and the Miller effect. The CB transfer function is

II s R C R R s R C

o

i T B o S B T S o

=+ ( )[ ]{ } + +( ) +

11 12 τ τ

The pole radius wn, is reduced by

RR R

B

S B+

Compensation in the CB emitter is shown below in (a) as a shunt RC.

RB

Io

RS

IiCo

CS

(a)

RS

Co

CS

(b)

RB

τT RB



The hf equivalent emitter circuit (b) has a shunt RL due to the gyrated RB. When

R CS S T⋅ = τ

the hf model yields

II

s Is R C s R C

o

ie

T B o T S o

= ( ) =( ) + +( ) +

ατ τ

112

Co forms a current divider with the emitter branch; Ie is calculated from the current-divider formula. This compensation maintains the pole radius the same as the uncompensated CB. For design, the value of CS is determined by the tT

compensation formula above. RS is expressed in z from Io/Ii as

RC

RC

ST

o

T B

o

= − + ⋅⋅τ ζ τ

2

For RS = RB, the network of (b) forms an all-pass constant resistance of RB. The poles are located at −1/RB · Co and −1/tT.

An estimation of Co is required to use the expression for RS. Current in Cm of the CE is input current to the base. The resulting collector current is larger by the lf current gain. In effect, current in Cm results in a total current of Ki + 1. Thus, the effective capacitance of Cm is (Ki + 1) · Cm. (This result suggests a form of Miller’s theorem for current amplifi ers.)

RB

Io

IiCo

CB

VB


58 Chapter 1

A CB compensation scheme introduced by John Addis is shown above. CB shunts RB, and gyrates to hf damping resistance at the emitter. (See “Emitter-Follower Reactance Plot . . .” in Designing Dynamic Circuit Response.)

If an inaccessible RB is bypassed by CB on its current-supply side, then a series base RC results. Using the hf BJT model, the emitter impedance is

ZR sC

ssR C

s CE

B B T B B

T B

=+( ) +

=⋅ +( )

+( )⋅( )1

11

1βτ

τ

ZE shunts Co. The current gain of the CB is

II s R C s C C

o

i T B o T o B

=( ) + +( )[ ] +

11 12 τ τ

The pole radius is not reduced by this technique, but control of z is more limited:

ζ τ τ ζ τ= ⋅

⋅+ ⋅

⋅⋅

= + ⋅⋅⋅

12

12

122 2

T

B o

T o

B B

T o

B BR CC

R CC

R Cuncomp

The appearance of Co in both terms indicates a minimum z dependent on Co. Because of the unavoidable base spreading resistance, rb′, RB is partly constrained in value by the BJT. The design value of CB is found by solving the above equation:

CCR C

CB

o

T B o

o=⋅ −

=−2 1 1ζ τ ζ ζuncomp

The lower bound on z is that

ζ ζ> uncomp

One remaining pole in the cascode requires compensation. At the output, the CB transistor output capacitance forms a pole with the load resistance. This pole can be compensated by peaking the CE. The CE is already compensated by



R CE E T⋅ = τ

Output compensation thus requires a more complicated emitter network. The strategy is to cancel the output pole with a zero. Poles of the emitter network impedance are zeros of the cascode transfer function.

RE

C

RCE

This network meets the requirements. Its impedance is

Z RsRC

s R C RC s R C R C RCE E

E E E E E

= ⋅ +( ) + + +( ) +

112

Input impedance compensation requires one of the poles of ZE to be at tT. For pole-zero cancellation of the output pole, with time constant tL, the other pole of ZE must be at −1/tL. Therefore, the denominator is constrained to be of the form

s s s sT L T L T Lτ τ τ τ τ τ+( )⋅ +( ) = + +( ) +1 1 12

The zero must lie between tT and tL. The network behaves as a phase-lead com-pensator, shifting the load pole to the higher frequency at 1/RC. The cascode transimpedance with ZE compensation is


60 Chapter 1

VI

R Ks K s K RC

o

iL i

i T L i T

= − ⋅ ⋅( ) + +( ) +

112 τ τ τ

For design, RL, Ki, tT, and tL are given. We can choose RC based on the desired damping ratio without affecting the pole radius:

RC K Ki T L i T= ⋅ ⋅ ⋅ − ⋅2ζ τ τ τ

With RC determined and RE constrained by Ki, the coeffi cients of the ZE denomi-nator and its constrained form are equated to yield

CR R C

ET L

E

=⋅

⋅ ⋅τ τ

CR C R C

RT L T L

E

=+ − ⋅ − ⋅ ⋅τ τ τ τ

R · C is known from the above formula, and R is easily found once C is known. Note that with R and C added, the value of CE is different from that given by RE · CE = tT.

Example: Cascode Dynamic Response Compensation

The cascode amplifi er is to have approximately MFA response and a transresis-tance of 1 kΩ with maximum bandwidth. The transistors have fT = 600 MHz, Cm = 2 pF, and rb′ = 50 Ω.

The input current source terminates in a 100 Ω base resistor RB. The output has 5 pF of load capacitance.

To analyze and compensate this amplifi er, begin with some transistor calculations:

τπT

Tf=

⋅=1

2265ps

C C Co L2 2

2 5 7

= += + =

μ

pF pF pF



With RB given, the optimum RE or Ki can be determined from the optimum-RB equation by solving for RE (in Ki):

optimum RR C

rET

Bb=

⋅⎛⎝⎜

⎞⎠⎟

⋅ ′= ⇒τμ

66 3 68. Ω Ω

Then Ki = RB/RE = 1.47. With RE calculated, RL can be found:

RVI

VI

II

R K RRK

mo

i

o

o

o

iL i L

m

i

= = ⋅ = ⋅ ⇒ = = ⇒680 680Ω Ω

The output pole is at

fR C

LL L o

=⋅

=⋅ ⋅

=⋅( ) =1

21

21

2 4 7633 4

2π τ π π ..

nsecMHz

R

C

CRE E

RBiI100 Ω

Q1

Q2

C

5 pF

Vo

RL

+V CC

+V BL


62 Chapter 1

To maximize bandwidth, compensation of tL is required. Proceed to compen-sate for both tL and the input impedance of the CE. For MFA response (and assuming a single pole-pair),

ζ = ≅2 2 0 707.

Also,

Ki T⋅ =τ 390 ps

Applying the formula for RC, the series RC compensator in the emitter circuit has a time constant of

RC K Ki T L i T= ⋅ ⋅ ⋅ − ⋅ = ( )⋅ ( )⋅( ) − =2 1 414 390 4 76 390 1 54ζ τ τ τ . . .ps ns ps ns

Continuing with CE,

CR R C

ET L

E

=⋅

⋅ ⋅= ⇒

τ τ12 0 12. pF pF

and from C,

CR C R C

RT L T L

E

=+ − ⋅ − ⋅ ⋅

= ⇒τ τ τ τ

39 2 39. pF pF

With C known, R can readily be found from the previous calculation:

R = = ⇒1 5439

39 3 39.

.ns

pFΩ Ω

From series compensation, the new pole is at 1/2p · R · C = 104 MHz.The CB base spreading resistance of 50 Ω may require compensation. At the

emitter it forms a shunt RLC circuit with Cm1 with

τ τ μn T br C= ⋅ ′⋅ = ⇒1 163 978ps MHz



and

ζ τμ

= ⋅′⋅

= ⇒ °12

0 814 361

T

br C.

Because this resonance has a high value of z relative to the MFA value and has fn at nearly 1 GHz, this pole is not likely to affect the response much and is not compensated.

With RE now known, we can calculate the CE input time constant. The uncom-pensated time constant, with only RE in the emitter circuit, is approximated as

uncomp pF nsτ τμi B b E

T

E

R r R CR

≅ + ′+( )⋅ +⎛⎝⎜

⎞⎠⎟ = ( )⋅( ) =218 5 9 1 29Ω . .

This corresponds to a frequency of 124 MHz. The compensated ti is

comp ps MHzτ τμi B b

T

E

R r CR

≅ + ′( )⋅ +⎛⎝⎜

⎞⎠⎟ = ⇒885 180

The series RE and (tT /RE) is replaced by tT /RE alone, and the speed increases. The uncompensated bandwidth is calculated by single-pole approximation of the time constant, from the risetime formula,

uncomp ns ps ns

ns

τ τ τ τ= + + = ( ) + ( ) + ( )=

i CB L2 2 2 2 2 21 29 1 63 4 76

4 93

. . .

. ⇒⇒ 32 3. MHz

With compensation,

comp ps ps ns ns MHzτ = ( ) + ( ) + ( ) = ⇒885 163 1 54 1 78 892 2 2. .

Shunt or series inductive peaking at the output could increase the bandwidth above 100 MHz.

The choice of ζ = 2 2 leads to MFA response for only one pole pair. However, in this circuit, the CB pole and CE input pole also infl uence pole angle. The combination is not exactly MFA but is slightly overpeaked from MFA due to the additional poles.


64 Chapter 1

The value of Cm is not given in manufacturer’s data sheets. Cm depends on VBC; its value cannot be specifi ed except at a given voltage. The typical value is at VBC = 0 V and is Cjc(0) or Cj 0. Then Cm is the junction capacitance Cjc:

CC

Vjc

j

BC Cm=

− ( )[ ]0

1 φ

where fC is the barrier potential and m depends on the junction grading. Typically,

φC m= =0 75 0 5. , .V

For linearly graded junctions, m = 0.33. The SPICE parameters corresponding to these quantities are

C mj C0 ⇒ ⇒ ( ) ⇒ ( )CJC VJC PC MJC MC, ,φ

For a normal-mode NPN, VBC is negative, and the subtraction in Cjc is the addi-tion of a positive voltage ratio. With the typical values, at 5 V reverse bias a junction has one third of the capacitance it has at zero volts.

COMPENSATION NETWORK SYNTHESIS

RE

C

RCE



The emitter compensation network, shown above, was chosen because its impedance provided the poles and zero required for compensation. In general, compensation requirements are known in terms of poles and zeros, whereas the topology and equations for element values are unknown. The compensa-tion of hf-gyrated impedances is simplifi ed by deriving the equivalent circuits and noting that all-pass networks can be formed with them. Because of the need for compensation networks, a few common synthesis techniques can be useful.

Z

Zc

(a)

Z

(b)

Zc

One compensation technique is to make a reactive network with impedance Z resistive and thus independent of frequency. A compensating impedance Zc is added in series (a) or parallel (b) with Z.

R

(a)

R

L

Zi

C

R

(b)

C

R

Zi

L

For the above networks, Zi = R whenever

L C R= 2


66 Chapter 1

A shunt RL, such as an emitter-gyrated base resistance, is compensated by adding in series a shunt RC. Then from the all-pass constraint equation,

R R CR

BT

B

= =,τ

RBτT

R

Vi

C

Vo

RE

+

–

This creates a resistive voltage divider at the emitter. If the load is capacitive, C is made larger to compensate the divider. Then Z of the network from the emitter must still be equivalent to a shunt RC, satisfying the all-pass constraint.

More generally, a shunt RC can similarly be compensated by adding a shunt RL in series with it. Or a series LC can be compensated by the two resistors shunting each of them, as in (a) above. In these cases, Zi = R when the all-pass constraint is satisfi ed.

A series RC, such as a base-gyrated emitter resistance, can be compensated by shunting it with a series RL, as in (b). The input of a common-collector (CC) with signifi cant Cm at the internal base node and resistance in the collector supply return line forms a series RC that can compensate the series RL of the base. Base R and L are both parasitic (rb′ contributes to R and lead inductance to L) and can be made to appear resistive at b′. Adjustment of the collector and base resistance and series base inductance make it possible to satisfy the all-pass constraint. For rb′ = 100 Ω, Lb = 10 nH, and Cm = 3 pF, the impedance at b′ toward



b is resistive and is 100 Ω when the collector resistance is 100 Ω and 20 nH is added to the base circuit. This added inductance might be from the inductive peaking of the previous stage.

R

R

L

Zi

C

Lc

c

C

More complicated networks are also possible, such as the one shown above. Here, the conditions for a resistive input of Zi = R are

L C L C Rc c= = 2

This network is a compensated shunt RLC, or a shunt RC in which the capacitor, Cc, has parasitic inductance, Lc. This is typical of electrolytic capacitors, which have resonant frequencies around 1 MHz or, for higher frequencies, any capaci-tors with leads. A monolithic multilayer ceramic capacitor has about 5 nH of inductance with leads of a length needed for insertion into circuit-board holes. Leadless chip capacitors are sometimes required for good high-frequency bypass or decoupling of the power supply terminals of active devices.

Zb

Vi

+

–

Vo

Za

R R


68 Chapter 1

A common network, the bridge-T, is shown above. A special case of the bridge-T is applied in T-coil compensators. The input is Zi = R when

Z Z RVV Z R

a bo

i b

⋅ = ⇒ =+

2 11

Za and Zb must be dual reactances (or reciprocal impedances); if Za is capacitive, Zb must be inductive.

Vi

+

–

Za

Zb

Vo+ –

Zb

Za

R

Another common network, shown above, is the lattice or bridge. The lattice network has the same resistive input conditions but a different transfer function:

Z Z RVV

Z RZ R

a bo

i

a

a

⋅ = ⇒ =−+

2 11

Two general methods can be applied to the synthesis of passive networks with a given Z(s):

1. Partial-fraction synthesis, for factored poles or zeros.

2. Continued-fraction synthesis, for explicit network topology.

Partial-fraction synthesis is based on partial-fraction expansion of Z(s). This requires factoring the denominator. If the numerator is easier to factor, expand Y(s) = 1/Z(s) instead. Various network topologies can result, however, and other design considerations could constrain the choice of topology.



Example: Partial-Fraction Network Synthesis

A network is described by the following Z(s):

Z Rs

s s= ⋅

++( )⋅ +( )

ττ τ

3

1 2

11 1

Z can be written as

ZA

sB

s=

++

+τ τ1 21 1

When Z is partial-fraction expanded, A and B are

A R B R= ⋅−−

⎛⎝⎜

⎞⎠⎟

= ⋅−−

⎛⎝⎜

⎞⎠⎟

τ ττ τ

τ ττ τ

1 3

1 2

2 3

2 1

,

A and B are resistances. The expanded Z can be written as

Zs A A s B B

s A A s B B=( ) +

+( ) +

= ( )[ ] + ( )[ ]11

11

1 11 2

1 2τ ττ τ

Z has the form of two shunt RCs in series.

Continued-fraction synthesis produces a continued-fraction form of Z. A desirable feature of continued-fraction impedances is that the topology is explicit in the form of the expression. The general procedure is to invert rational expres-sions that are less than one and to divide by synthetic division.

Example: Continued-Fraction Network Synthesis

An impedance of the form of the previous example is

Z Rsc

as bs= ⋅ +

+ +1

12


70 Chapter 1

R is fi rst multiplied to the numerator in s and the fraction inverted:

Zas bs

sRc R

=+ +

+⎛⎝⎜

⎞⎠⎟

112

The denominator is now greater than one and can be divided to become

Z

saRc

bc aRc

sRc Rc bc a

c

=

⎛⎝ ) + −⎛

⎝ ) + +− +⎛

⎝⎜⎞⎠⎟

11

2 2

2

The remainder is divided by s · R · c + R and then inverted. Division is carried out once again, and the fi nal continued fraction results:

Zs

aRc

bc aRc

sRc

c bc aR

cc bc a

=⋅⎛⎝ ) + −⎛

⎝ ) +⋅

− +⎛⎝⎜

⎞⎠⎟

+ ⋅− +

⎛⎝⎜

⎞

11

2 3

2

2

2 ⎠⎠⎟

The terms in the denominator of Z are admittances. The capacitance a/Rc is in parallel with resistance

Rc

bc a⋅

−⎛⎝⎜

⎞⎠⎟

2

and with the series RL, where the resistance is

Rc

c bc aRS⋅

− +⎛⎝⎜

⎞⎠⎟

=2

2

and the inductance is c · RS.



Continued fractions represent shunt topologies, and partial fractions represent series topologies. In continued-fraction expansion, divisions are executed the usual way, beginning with the highest power in s. If, instead, division begins with the lowest power, the divisor grows in powers of s. The remainder is then a power of s higher than that of the dividend. This approach does not produce the circuit topology of the desired network but can be useful in approximating a network by truncating the quotient. No s2 term represents a circuit element, but it can be transformed into an equivalent network with negative element values. (See Designing Dynamic Circuit Response, “High-Frequency Impedance Transformations.”)

Example: Differentiator

The circuit shown below in (a) is a differentiator with resistive input and output, suitable for transmission-line coupling. The circuit is analyzed by transforming it to (b) using the T-coil theory of inductive peaking. This topology is recognized as an approximate bridge-T when RL = R, and the coupled inductors are ideal as a transformer element. Then leakage inductances L 1 = L 2 = 0, and Za = sM, where M is the mutual inductance of L 1 and L 2, and Zb = 1/sC. Applying the all-pass constraint,

VV Z R

sRCsRC

o

i b

=+

=+

11 1

and Zi = R.The circuit differentiates to a frequency of 1/RC. A 50 Ω transmission line

can drive the differentiator and be terminated properly when R = 50 Ω. For wideband differentiation to 100 MHz, RC = 1/2p · (100 MHz) = 1.59 ns. Then C = 31.8 pF and M must be the pulse transformer magnetizing inductance:

M R C= =2 79 6. nH

The output-terminating resistance can be the characteristic impedance of another transmission line. In other words, the differentiator can be inserted


72 Chapter 1

into a transmission line without causing discontinuity. For example, high-speed differentiation of a ramp can be performed by driving a 50 Ω coaxial cable into a 50 Ω test section wherein the differentiator has been built. This section then terminates in the 50 Ω input of an oscilloscope vertical amplifi er.

DIFFERENTIAL-AMPLIFIER COMPENSATION

The two-transistor differential amplifi er (diff-amp) shown below has, at each BJT emitter, a voltage divider formed by R and Ze of the other transistor. This divider can be compensated by shunting R with a compensating C. The approach is the same for both Π (above) and T (below) emitter networks, since they are equivalent. The design goal is to compensate

iV

+

–

RSVo

RR

L1 L2 RL

C

(a)

iV

+

–

RSVo

RR

Ll1 Ll2

RL

C

(b)

M



ZZ Z

sr

sZ s

se

B e

o T

B

o o T

=+

( ) +=

++

+⎛⎝⎜

⎞⎠⎟

⋅+

+⎛⎝⎜

⎞⎠⎟

π β

β α τ βτ

α τ1 1 11

1

Below fT, the fi rst term is approximately re. In the hf region, ZB is gyrated.

RB

Vi

I

RB

C

R

I

+

–

RB

Vi

RB

C+

–

2

R2

R2

I

The situation is similar to that of the CB of the cascode. For ZB = RB, the resis-tive network shown below is formed.

R

R

L

Zi

C

To present a resistance to the emitter of the other BJT, the compensator time constant is


74 Chapter 1

R CR

RC

RR

T B T B⋅ =⋅

⇒ =⋅τ τ

2

In practice, signifi cant stray capacitance is often present at the emitter (or current source) node(s). The circuit is then represented by the circuit shown below, in which Co is the stray capacitance.

RB

Io

RS

IiCo

CS

(a)

RS

Co

CS

(b)

RB

τT RB

The previous results for the cascode can be applied. From the equation for z, increasing Co decreases z, causing the circuit to be less damped.

Transistor compensation techniques apply to differential as well as single-ended amplifi ers. For balanced differential amplifi ers, the shared networks between sides experience twice the drive of a single-ended network. Where gain is involved, their effective impedances are halved.

SHUNT-FEEDBACK AMPLIFIER DESIGN

The frequency-independent shunt-feedback amplifi er was analyzed in Designing Amplifi er Circuits and the closed-loop transresistance was derived. A shunt-feedback topology was also considered in Designing Dynamic Circuit Response with capacitive Zf. The general topology has a transimpedance of

VI

Z ZZ Z Z R

Z Z Z R Z Z Zo

if i

f L f m

f L f m i f i

= ( )⋅ ( ) −( )+ ( ) −( )[ ]⋅ +( )[ ]1



A wideband realization of a shunt-feedback amplifi er is the BJT amplifi er shown below, with frequency-dependent b and general impedances.

iI

Z f

ZL

Vo

Zi bs I( )βIb

Vi

This amplifi er is equivalent to the previously developed topology but is explicit in b(s) so that hf behavior can be analyzed.

iIbI

oV

( )Zβ f L|| Z–

1

Z f

Z LZ L+

Z f Zi+

Z f

Z fZ i+

Zi

Assuming a general b(s) at fi rst, the transimpedance is found by solving its fl ow graph.

VI

ZZ Z

Z Z Zo

iL

i f

f i L

= ⋅− ⋅

+ + +( )⋅ββ 1

The fi rst term in the numerator represents the passive noninverting path to the output, and the second term represents the active path through the BJT. The input impedance is derived after rin in Designing Amplifi er Circuits, “Shunt-Feedback Amplifi er Feedback Analysis”:

ZZ Z

GHZ

Z ZZ Z Z

ini f

if L

f i L

=+

= ⋅+

+ + +( )⋅1 1β

Similarly, following the quasistatic development,

Z ZZ Z

ZZ Z

Z Z Zout L

f iL

f i

f i L

=++

⎛⎝⎜

⎞⎠⎟

= ⋅+

+ + +( )⋅β β1 1


76 Chapter 1

The hf BJT model has Zp = 0. If Zp is not Zi, then it is a shunt contributor to it, and when set to zero causes Zi to be zero. The hf approximation of b(s) is 1/s tT. Making these hf approximations to the fl ow graph, the hf fl ow graph for the hf transimpedance results.

iIbI

oV

Z f L|| Z–

s T1

1Z f

τ

Solving for the transimpedance, based on this fl ow graph,

VI

Zs Z Z

Z Zo

i

f

T f LL f

hfhf= −

⋅ +( ) += − ⋅

τα

1 1

Zin is trivially zero, and the hf output impedance is

Zs Z

s Z ZV I

outT f

T f L

o ihf hf

hf

( ) =⋅

⋅ +( ) += − ( )τ

τ β1 1

These general results are applied to a less general single-BJT shunt-feedback amplifi er, shown below, where

Z RsC

RsR C

Z RsC

RsR C

f ff

f

f fL L

L

L

L L

= =+

= =+

11

11

;

CLiI

o

Tτ

Cf

Rf

CC+V

RL

V



Substituting into (Vo/Ii)hf and simplifying yields

VI

Rs R C C s R R R C

o

i

f

T f f L T f L f f

=+( ) + +( ) +[ ] +2 1 1τ τ

Before analyzing this transimpedance, easily obtained from Zout(hf) is the expres-sion for output impedance:

Zs R

s R C C s R R R C

R RC

outT f

T f f L T f L f f

f LT

f

=+( ) + +( ) +[ ] +

=⎛⎝⎜

⎞⎠

ττ τ

τ

2 1 1

⎟⎟ +( ) ⋅1s C C

s Rf L

T fτ

This impedance is represented topologically below as a shunt RLC.

RLZout CL Cf RfCf

TτTτ Rf

From Vo/Ii, the complex pole-pair damping ratio is

ζτ

τ= =

⋅ +( ) + ⋅⋅ ⋅ +( )

ba

R R R C

R C CT f L f f

T f f L2

1

2

The desired response is set by choosing z and solving for the element that is free to be varied. For a given transistor, tT is fi xed, and the required gain for the stage is also determined by the amplifi er design strategy. This sets Rf. Biasing constraints can set RL, and Cf is partly determined by Cm of the BJT. This leaves CL; its minimum is determined by the capacitive loading of the next stage. The best design insight is gained from the loci of poles when various elements are allowed to vary parametrically. The loci are determined by extending the tech-nique of “Loci of Quadratic Poles” in Designing Dynamic Circuit Response.


78 Chapter 1

The pole locus is described by geometric equations in the real and imaginary s coordinates, s and w. The two basic equations are

σ = − ⎛⎝

⎞⎠

ba2

ω221

2= − ⎛

⎝⎞⎠a

ba

and

ω σ2 2 1+ =a

Starting fi rst with Rf as parameter, substitute into s from Vo/Ii:

στ

τ= − = −

+( ) ++( )

ba

R R R CR C C

T f L f f

T f f L212

Solving for Rf,

RR

R C R C Cf

T L

T L f T L f L

= −+ + +( )

ττ τ σ2

The 1/a equation leads to

ω στ

τ τ στ

2 22

1 1 2+ = =

+( ) = −+ + +( )

+( )a R C CR C R C C

R C CT f f L

T L f T L f L

T L f L

Simplifying the right side and collecting s terms on the left side yields

ω σ στ

ττ

2 22

2+ +⎛⎝⎜

⎞⎠⎟ = −

+ ⋅⋅ ⋅ +( )T

T L f

T L f L

R CR C C

Completing the square in s by adding 1/t 2T to both sides,



ω στ

ττ τ τ

τ22

2 2

1 1 1+ +⎛⎝⎜

⎞⎠⎟ = −

+ ⋅⋅ ⋅ +( ) + = ⋅

⋅ −T

T L f

T L f L T T

L L TR CR C C

R CRLL f L

rC C⋅ +( )

⎛⎝⎜

⎞⎠⎟

=2

2ω

This equation describes a circular locus centered at s0 = −1/tT = −wT with a radius of wr. Unlike previous loci, the circle does not contain the origin but is offset to the left, as shown below.

jω

σωT–

ωr

Rf increasing

In practice, usually,

R CL L T⋅ >> τ

and wr simplifi es to

ωτ

τrT

L

f LL L T

CC C

R C≅ ⋅+

⋅ >>1,

At Rf = 0, the poles are at −∞ and −wT. As Rf increases, they move together and become complex, following the circular locus with decreasing s. At the s axis they split; as Rf → ∞, one goes to zero and the other to

−+

⋅ +( )τ

τT L f

T f L

R CC C


80 Chapter 1

The locus equation for parameter tT is derived similarly to that for Rf. It is also circular, centered at −1/Rf · Cf with

ωrf f

f f

f L f Lf f L L

R CR C

R R C CR C R C=

⋅⋅ −

⋅( )⋅ +( )

⋅ < ⋅11 ,

This constraint is required for real wr. When RL is replaced by a current source, this simplifi es to

ωrf f

L

f LL

R CC

C CR=

⋅⋅

+→ ∞1

,

At tT = 0, the poles are at −1/Rf · Cf and −∞. As tT increases, the poles move together.

( ) ( )

σ

ωr

Tτ increasing

1Rf

–Cf

1Rf

–CRL|| f L+C

jω

The low-frequency pole actually increases in frequency with a slower transistor. The poles form a circular locus with s decreasing until they separate along the s axis. As tT → ∞, one pole is at the origin and the other is at

− ( )⋅ +( )1

R R C Cf L f L



The locus of CL is derived similarly and has the same form as before. The center of the circle is in the RHP at

στ0

11

=⎛⎝⎜

⎞⎠⎟

⋅⋅ − ⋅ +( )⋅( )

CC R C R R C C

L

f f f T f L L f

with

ωτ

τ τ

rf f T f L L f

f f T f L L f T

R C R R C C

R C R R C C C

=⋅ − ⋅ +( )⋅( ) ⋅

⋅ − ⋅ +( )⋅( ) + ⋅

11

1 LL f

T

C( )2

τ

Often it is the case that

C C R CRR

L f f f Tf

L

<< ⋅ >> ⋅ +⎛⎝⎜

⎞⎠⎟

, τ 1

and Zf dominates the response. The locus for CL simplifi es to

σ ωτ0

1 1≅⎛

⎝⎜

⎞

⎠⎟⋅

⋅≅

⋅ ⋅CC R C R C

L

f f fr

T f f

,

For left half-plane (LHP) poles, wr > s0, and the equation for s0 satisfi es this condition for typical values.

The locus for Cf would also be useful but cannot be put in a form similar to the previous parameters. When r ′b is taken into account, the transimpedance gains a pole, and the denominator is cubic. The effect of r ′b is to slightly undamp the amplifi er. Under the above conditions,

ba T2

12

= =τ

constant

Variation in Rf or Cf moves the poles along the vertical locus. An increase in Cf or Rf reduces pole angle, though pole radius is also reduced somewhat. When CL = 0 and RL → ∞, the poles are located at −1/Rf · Cf and −wT.


82 Chapter 1

The astute observer will recognize that Zout from the equivalent circuit is similar to what would be expected of emitter impedance due to a gyrated shunt RC in the base. The coincidence is not accidental. Bruce Hofer observed that the topology of the shunt-feedback amplifi er and emitter-follower are identical.

Zi

Z f

ZL

CC

CE

oV

–

+iV

+

–

CB

I i

The fi gure above shows a general BJT circuit with impedances shunting each BJT terminal pair. Which of the three confi gurations (CE, CB, or CC) is rep-resented depends on where ground is placed, as shown. Since ground is an arbitrary 0 V reference node, the port impedance of the Vo node is the same for CC and CE. For the CC, Zf is a shunt base impedance; for the shunt-feedback CE, the output port is the same, except in relation to ground. Because port impedances are independent of grounding conventions, Zout is the same.

This observation also applies to inverting and noninverting op-amp confi gura-tions; their topology is identical. In the case of the noninverting op-amp, the input is added (in series) with the amplifi er.

SHUNT-FEEDBACK CASCODE AND DARLINGTON AMPLIFIERS

The unavoidable presence of Cm in the shunt-feedback amplifi er has led to a minimization of parasitic feedback capacitance by use of a cascode amplifi er as the forward path G, shown in (a) below.



This involves the additional factor a2 of the CB. The fl ow graph (b) reduces to a transimpedance of

VI

R s R C C s R R R C Co

if T T f f L T T f L T f f L= − +( )[ ] + +( ) + +( )[3

1 22

1 2 11τ τ τ τ τ ]]{ +

+( ) +[ ] + }s R R R CT f L f fτ 1 1 1

An additional pole due to a2(s) results in a cubic denominator. For

R Cf f T T⋅ >> τ τ1 2,

the denominator of Vo/Ii can be factored approximately to yield

VV

RsR C s C C s C C

o

i

f

f f T T L f T L f

≅ −+( ) +( )[ ] + +( )[ ] +( )1 1 1 12

1 2 1τ τ τ

CL

iI

o

(a)

T1τ

Cf Rf T2τ B+V

CC+V

RL

iI1 bI

oV( )α 2 Zβ1 f L|| Z–

1Z f

(b)

V


84 Chapter 1

In the complex pole factor, tT2 is present only in a and not b. This results in a circular locus for tT2 and a vertical (constant-s) pole locus for the other parameters.

iV

+

–

Cf

CL

Vo

iRm

V

(a)

R

(b)

mZiCf

CL

CLCf( )1 +

An amplifi er of transconductance 1/Rm with load capacitance but with no Rf is shown in (a). The voltage gain for a general load impedance ZL is

VV

ZR

sR CsZ C

o

i

L

m

m f

L f

= − ⎛⎝⎜

⎞⎠⎟ ⋅

− ++

⎛⎝⎜

⎞⎠⎟

11

For ZL = 1/sCL,

VV

sR CsR C C

o

i

m f

m f L

= −− ⋅ +

⋅ +( )1

This result has a familiar RHP zero. The equation can be envisioned as an uncompensated voltage divider in which the upper impedance is a shunt RC consisting of Cf and −Rm · (1 + Vo/Vi), and the lower impedance is due to CL.

The input impedance is

ZVI sC V V

ini

i f o i

= =⋅ −( )

11



and has the form of a Miller capacitance. After substitution of Vo/Vi and simplifi cation,

Zs C C

RCC

inf L

mL

f

=( )

⎡

⎣⎢

⎤

⎦⎥ ⋅ +

⎛

⎝⎜

⎞

⎠⎟

11

The equivalent input network is shown in (b) above. This is a surprising result because the input has a shunt resistance, but the actual circuit has only a capaci-tive connection to the input node. This circuit models CE amplifi ers with sig-nifi cant Cm and load capacitance.

Example: CE with Load and Shunt-Feedback Capacitances

The BJT amplifi er has an input impedance determined by the previous equation for Zin. Assume that the transistor has a = 1 and re ≅ 0. Then the transresistance of the BJT is approximately RE, or 1 kΩ. The base input impedance is infi nite and can be ignored. The analysis applies to the lf region and is not due to hf effects.

C

RE

L

re

iV

+

– 1 kΩ

9 pF

oV

Cf

1 pF

≅ 0β ←∞

An intuitive explanation begins by noting that the path through Cf directly presents a capacitance of the series combination of Cf and CL, or 0.9 pF, to the input. Second, if a 1 V step is applied to the input, it generates 1 mA of collec-tor current. This current divides between Cf and CL since they form a capacitive current divider. For Cf = 1 pF and CL = 9 pF, 0.9 mA fl ows through CL whereas


86 Chapter 1

0.1 mA fl ows from the input. This component of current corresponds to the resistive path in Zin circuit (b) above. The resistance is

10 1

10VmA

k.

= Ω

Now to check this result, use the equation for Zin. The series combination of capacitances follows immediately. The resistance should be

RCC

mL

f

⋅ +⎛⎝⎜

⎞⎠⎟

= ⋅ +⎛⎝⎜

⎞⎠⎟

=1 1 19

10kpF

1pFkΩ Ω

and the two solutions agree.

The amplifi er of (a) above is now modifi ed to conform to a BJT shunt-feedback circuit for the hf region.

CL

iV

+

–

oV

Cf

CiIb

Tτs

Ib

For a general output impedance ZL, the voltage gain is

VV

s Cs C Z

o

i

i

f L

= −⋅

+( )⋅ +β

β 1 1

Substituting bhf = 1/stT and ZL = 1/sCL,

VV

CC s C C

o

i

i

f T L f

= −⎛⎝⎜

⎞⎠⎟

⋅⋅ +( ) +

11 1τ



To avoid Cm, the amplifi er can be made a cascode. Then the above circuit is modifi ed by multiplying a2 of the CB to the current source. This leads to a complex pole-pair in the voltage gain:

VV

CC s C C s C C

o

i

i

f T T L f T L f

= −⎛⎝⎜

⎞⎠⎟

⋅+( ) + +( ) +

11 1 12

1 2 1τ τ τ

The response can be designed in the usual way for complex pole pairs. The damping ratio is

ζ ττ

= ⋅ +⎛⎝⎜

⎞⎠⎟

⋅⎛⎝⎜

⎞⎠⎟

12

1 1

2

CC

L

f

T

T

Comparing this with z for a single-BJT shunt-feedback amplifi er, Cf has the opposite effect of damping the response. In this circuit, increasing Cf undamps it.

Finally, the idea of isolating Zf from stray capacitance can be extended to the Darlington confi guration, shown below.

CL

iI

oV

T1τ

Cf Rf

T2τ

CC+V

CC+V

The transimpedance has a cubic denominator and a zero at wT1. Again assuming a dominant time constant of RfCf, the approximate transimpedance is

VI

R ssR C s C C C s C C

o

i

f T

f f T T L f T f

≅+( )

+( ) + +( )[ ] + +τ

τ τ τμ μ

1

21 2 2 1 2

11 1 1 (( )[ ] +{ }1


88 Chapter 1

The complex pole-pair has the same radius as the shunt-feedback cascode but has a different expression for z. Because CL appears only in a, its root locus has a circle in the LHP whereas the other parameters have a constant-s locus. Therefore, CL is the component of choice for adjustment of response.

CLOSURE

Rf 2Rf1

RL2RL1

0I0I

1I

+V

v o+ –

Q3 Q4

Q1 Q2v 1 v 2

RE

Fast amplifi ers consist of several of fast stages in cascade. Various combinations are used in fast amplifi er designs, such as the above diff-amp in cascade with a differential shunt-feedback amplifi er. Subsequent chapters continue develop-ment of the fast amplifi er repertoire, adding more precise, yet fast, amplifi er stages.


Designing Waveform-Processing Circuits


Raleigh, NC.


FPCPR.indd iiiFPCPR.indd iii 7/29/2009 10:38:14 AM7/29/2009 10:38:14 AM





Editor: Dudley R. KayProduction Manager: Robert LawlessTypesetting: SNP Best-Set Typesetter Ltd., Hong KongCover Design: Aaron LawhonPrinter: Docusource



10 9 8 7 6 5 4 3 2 1

ISBN: 9781891121852Series ISBN: 9781891121876

Library of Congress Cataloging-in-Publication DataFeucht, Dennis. Designing waveform-processing circuits / D. Feucht. p. cm. – (Analog circuit design series ; v. 4) Includes bibliographical references and index. ISBN 978-1-891121-85-2 (pbk. : alk. paper) – ISBN 978-1-891121-87-6 (series) 1. Signal generators. 2. Oscillators, Electric. 3. Signal processing. 4. Electronic circuit design. I. Title. TK7872.S5.F83 2010 621.3815′33–dc22 2009028291

FPCPR.indd ivFPCPR.indd iv 7/29/2009 10:38:14 AM7/29/2009 10:38:14 AM

Contents

Chapter 1 Designing Waveform-Processing Circuits . . . . . . . . . . . . . . . . . . . 1Voltage References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Current Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Hysteretic Switches (Schmitt Triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Discrete Logic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Clamps and Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Multivibrators and Timing Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Capacitance and Resistance Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Trigger Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Ramp and Sweep Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Logarithmic and Exponential Amplifi ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Function Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Triangle-Wave Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Absolute-Value (Precision Rectifi er) Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 121Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Chapter 2 Digitizing and Sampling Circuits . . . . . . . . . . . . . . . . . . . . . . . 135Electrical Quantities Both Encode and Represent Information . . . . . . . . . . 135Digital-to-Analog Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136DAC Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149Parallel-Feedback ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154Integrating ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Simple μC-Based Σ-Δ ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

FPCPR.indd vFPCPR.indd v 7/29/2009 10:38:14 AM7/29/2009 10:38:14 AM

Voltage-to-Frequency Converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176Parallel and Recursive Conversion Techniques . . . . . . . . . . . . . . . . . . . . . . . . 182Time-Domain Sampling Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186Frequency-Domain Sampling Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189The Sampling Theorem (Nyquist Criterion) . . . . . . . . . . . . . . . . . . . . . . . . . . 197Sampling Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201Switched-Capacitor Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205Closure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

vi Contents

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2Digitizing and Sampling Circuits

ELECTRICAL QUANTITIES BOTH ENCODE AND REPRESENT INFORMATION

An electrical quantity in time x(t) is a signal when it encodes information. The information is interpreted according to a representational theory, such as logic theory for digital signals or transforms based on analogy for analog signals. The theory of representation is independent of the encoding scheme. In communi-cations theory, encoding is called modulation. What the modulating signal rep-resents is independent of its encoding. A thermometer output, for example, can be encoded in analog or digital form but represents temperature, regardless.

Another way to think about information encoding is as two levels of representation. The encoding scheme is a representation at the electrical level, and the encoded information represents a quantity that is independent of elec-tricity. This “more abstract” level of representation has to do with the applica-tion. Consequently, electronics is useful in domains that have nothing to do with electronics because both signals and their processing operations have meaning-ful interpretations for the application.

Information can be encoded as discrete or continuous functions of either an electrical quantity (usually voltage or current) or of time. The information to be encoded and the encoding scheme can be either discrete or continuous. The compatibility of an encoding scheme with the encoded information is a design consideration. For example, discrete functions are often best represented by digital encoding. Engineers sometimes differ over the relative merits of discrete versus continuous encoding and processing of information. The difference between discrete, or digital, and continuous, or analog, encoding is so important that each constitutes a major subdiscipline within electronics.

FPC02.indd 135FPC02.indd 135 7/29/2009 10:37:43 AM7/29/2009 10:37:43 AM

136 Chapter 2

A digital signal is discrete in both x and t. Binary encoding is by far the domi-nant digital encoding of x, where x ∈ {XL, XH}. These two values or “levels” are named low (XL) and high (XH) and represent binary logic states of false and true, or, in Boolean algebra, 0 and 1. Whether the low level represents true or false depends on the polarity of the logic; a low level is false in positive logic and true in negative logic. Digital encoding can have more than two levels. The number of levels equals the modulus or base of the number representation. For example, decimal numbers can be encoded in a 10-level scheme. As the modulus increases, the representation approaches a continuous form.

An example is the output of digital-to-analog converters (DACs). For an 8-bit DAC, 256 discrete levels may adequately approximate a continuous function in some applications. The DAC could, however, be considered an encoder of base-256 numbers. In this sense, continuous waveforms are of infi nite modulus, and analog engineers are actually digital engineers who specialize in infi nite-base encoding.

Discrete functions can also be encoded in time. Frequency-shift keying, a kind of binary FM used in modems, is one approach. More common to computer electronics is synchronous and asynchronous serial encoding of alphanumeric characters in ASCII. Many other purely digital encoding schemes make digital encoding and communications a specialty in itself.

Continuous functions can also be encoded purely in time as the width of a (binary) pulse (pulse-width modulation [PWM]) or by its time difference rela-tive to another event in the signal (pulse-position modulation) or simply by the pulse frequency, as is the output of voltage-to-frequency converters (VFCs).

Finally, waveforms that are continuous in x and discrete in t are sampled wave-forms. These waveforms are of great importance in association with analog-to-digital (A/D) and digital-to-analog (D/A) conversion and with sampled-data systems in general, systems that contain discrete-time waveforms, such as a motor servo controller with a digital position encoder, or any system with sample-and-hold circuits.

DIGITAL-TO-ANALOG CONVERTERS

Digital-to-analog converters convert digital input codes to output voltages or currents. The transfer curve for a unipolar three-bit DAC has discrete voltages at the discrete (integer) values of the digital input code d.


Digitizing and Sampling Circuits 137

The digital code is an ordered set of bits that represent integers. Various number representations are possible, but the most common are shown in the table for three bits.

Integer Offset BinaryTwo’s

Complement Sign-Magnitude

3 111 011 011 +fs

2 110 010 010

1 101 001 001

0 100 000 000 100 zs

−1 011 111 ↑ 101 ↑

−2 010 110 0+ 110 0−

−3 001 101 111

−4 000 100 ↑ −fs

↵

inverted MSB

↵

(sign)

MSB 1 ⇒ −

These are signed (bipolar) representations of integers. The most common number representations are two’s complement and offset binary. They differ only in the polarity of their sign bit. Binary-coded decimal (BCD) is also some-times used, in which the fi rst 10 binary numbers represent a decimal number.

In the above table, the positive full-scale (fs) value is 3, and the negative fs value is −4, one greater in magnitude. This asymmetry results from assigning a state to zero. Sign-magnitude coding is symmetric, but it has two zero states. In general, for n bits, there are 2n states. The transfer characteristic for a unipolar n-bit DAC is

1 2 3 4 5 6 7 d0

Vfs

VR

vO

VLSB


138 Chapter 2

v Vd

O R n= ⋅⎛⎝

⎞⎠2

where VR is the DAC reference voltage. The fs voltage is less than VR because the

maximum d n= −2 1

Accordingly,

V V VV

V Vfs R

n

n RRn R= ⋅

−⎛⎝⎜

⎞⎠⎟

= − = −2 1

2 2LSB

That is, the fs output is less than VR by VLSB, the quantum voltage: the voltage difference corresponding to a difference of one input state. Because VLSB is the smallest output voltage difference of the DAC, it is also its resolution, its minimum ΔvO.

The DAC input often represents a continuous function, but because it is discrete (or quantized), for values between integers the DAC output remains constant. In the plot shown above, vO is zero over the interval [0, 1). (This is the least-integer function). At 1−, infi nitesimally below 1, vO = 0 V, though the correct value is infi nitesimally less than VLSB. The output is in error by VLSB at 1− and has no error at zero. The magnitude of the error can be split so that the error range is ±1/2 VLSB by offsetting vO by 1/2 VLSB. Then the DAC output fs magnitudes are also equal.

1 2 30

2

–2–3–4

Vfs +

vO

VLSB

Vfs –

d



Quantization error causes quantization noise, which is a sawtooth function that cycles between −VLSB/2 and +VLSB/2 between each state (Δd = 1). The rms value of this noise vn is

rms LSB LSBLSBv

dV

dd d d

VVn d

d= ⋅⎛⎝

⎞⎠ ⋅ ( ) = ≅ ⋅−

+∫

112

0 32

2

2

Δ ΔΔ

Δ.

A signal-to-noise ratio (SNR) defi nition for n bits is

SNRrms

LSB

LSB

= =⋅

= ⋅ ≅ ⋅Vv

V

VR

n

nn n2

1212 2 3 46 2.

In decibels, this is

SNR dB( ) = ⋅ ⋅( ) = ⋅ + ⋅ ⋅ ≅ + ⋅20 12 2 20 12 20 2 10 8 6 02log log log . .n n n

The dynamic range is about 6 ⋅ n dB, and quantization noise is about 10.8 dB independent of the number of bits. Each additional bit increases the range by ×2, an octave, and this is 6 dB/octave, the slope of a Bode plot zero.

A different characterization of the SNR is as the ratio of rms signal to rms noise for a sinusoid. The rms value of a sine of amplitude V is 2 2( )V . Then

SNRrms sine

rms noiseLSB

LSB

= =( )⋅( )⋅

= ⋅⎛⎝⎜

⎞⎠⎟

≅2 2 2 2

122

62

1 23n

nV

V. ⋅⋅2n

In dB scaling, this is

SNR dB( ) = ⋅⎛⎝⎜

⎞⎠⎟

+ ⋅ ≅ +206

220 2 1 76 6 02log log . .n n

The dynamic range remains the same under this defi nition of SNR, but the signal is less relative to the noise. This explains why the constant term of 1.8 dB is less than in the fi rst SNR(dB).


140 Chapter 2

In actual DACs, the step size of quantum VLSB is not constant, which affects the linearity of vO/d. A measure of this nonlinearity is the differential linearity error (DLE), or differential nonlinearity, the amount a step differs from VLSB:

DLE LSB= −Δv Vstep

If DLE exceeds VLSB, the transfer curve is nonmonotonic, decreasing in output value with increasing d. This behavior can wreak havoc in control system appli-cations. DACs also have offset and scaling (gain) errors, but these are nulled by external adjustment; the DLE cannot be.

DACs often output functions of time, vO(t); their dynamic response is impor-tant. This is characterized by the settling time to within ½ VLSB of error. A dynamic anomaly of DACs is that when a large number of bits change in d, the effects of individual bits on the output are not exactly synchronized. At the output, momentary pulses or “glitches” appear until all the bits settle. This phenomenon is especially evident at midscale, when d changes from 011 to 100 (for a three-bit DAC). The change in most-signifi cant bit (MSB) must be canceled by the com-bined changes of all the other bits, to within VLSB, the correct ΔvO.

When glitches are unacceptable, as in CRT display systems, the DAC is fol-lowed by a deglitcher. These are either hf limiters or samplers with a delay. In delayed samplers, the DAC output is allowed to settle. Then it is sampled, and this value is output. The sampling control signal is delayed from the clock that changes DAC input states.

2R

4R

8R

RQ3

Q2

Q1

Q0

Rf

–

+

4d

4-bit CMOS register

vO

Rf⏐⏐8

15 R



DAC designs are categorized as either bipolar junction transistor (BJT) or complementary metal-oxide semiconductor (CMOS). Both achieve binary weightings of voltage or current for each bit by a resistive network. Unless the number of bits is few (≤4), these are R-2R or resistive ladder networks. Otherwise, a set of binary-weighted resistors suffi ce. A four-bit binary-weighted resistor DAC is shown, voltage-driven by a CMOS register. The output is a function of each of the bits bi of d:

v RvR

bVR

bV

Rb

VR

bRR

VO fR R R R f

R= − ⋅ ⋅ + ⋅ + ⋅ + ⋅⎛⎝

⎞⎠ = − ⎛

⎝⎜⎞⎠⎟ ⋅ ⋅ −

3 2 1 02 4 8

2 iiib i⋅( ) =−3 0 1 2 3, , , ,

where b0 is the least-signifi cant bit (LSB) and VR is the CMOS register supply voltage, the DAC voltage reference. (CMOS digital outputs accurately approach the supply rails.) The resistors must have suffi cient precision to minimize DLE. The resistor requiring the most precision is at the MSB, R, since it must be within

ΔRR

RR

n n= ± ⋅ = ± ⋅ = ±− −( ) −12

12

2 21

LSB

A four-bit DAC must have a tolerance on R of 6.3%. A 5% resistor suffi ces. For eight bits, the tolerance is 0.4%. This is diffi cult to achieve in monolithic form when the resistor values have such a wide range.

2R

Q3

Q2

Q1

Q0

Rf

–

+

4d

4-bit CMOS register

vO

Rf⏐⏐R

2R

2R

2R

R

R

R

2R


142 Chapter 2

A standard alternative is the voltage-switching R-2R network, another four-bit DAC.

In general, the binary weighting,

W d bin i

i

n

( ) = ⋅−−

=∑ 2

0

is the essence of DAC function. This weighting is achieved in the R-2R network. Beginning with b0, if it is 1, Q0 output is VR; if it is 0, then the output is 0 V. For b0 = 1, the Thevenin equivalent circuit is shown below.

+VR

b01

0

R2

R

R2

R2

VR2

At each stage of an R-2R network, the input resistance is 2R and the voltage of the previous stage is halved. From the input end of the network, the b0 voltage is consequently halved four times. At the output, the op-amp is driven by a source resistance of R (another series R was not added to the network to make it 2R) and voltage of W(d)VR.

VR

R2 R2 R2 R2 R2

R R RI R

iO′

iO R

+

–vO

LSBMSB



CMOS DACs are typically designed as shown above, with CMOS switches at the output and VR at the input. This reversal does not change the operation except that the DAC outputs must be kept at ground (or virtual ground, as shown) to avoid errors in output current. This current-switching R-2R network is still voltage-driven, and the output is −WVR with op-amp feedback resistor R. Integrated circuit DACs often include this resistor to ensure its match with those in the network. The outputs are complementary currents that sum to a full-scale current,

i i IV V

RO O fs

R+ ′ = =− LSB

Switch resistance must be minimum (or binary-ratioed) for minimum network error. MOSFET switch areas are scaled to achieve equal voltage drops across all switches.

CMOS DAC output impedance changes with d. The two extremes are with all zero and all one bits (next page) for an AD7520, a 10-bit DAC with R = 10 kΩ and leakage current IL of 200 nA. Response compensation for op-amp input capacitance can be based only on an average or worst-case input state. Because output resistance varies extremely, op-amp bias-current compensation is also suboptimal.

–

+

RR

VR

IR

R

VEE–R R

VB

16 A 8 A

R2

IR

IR2

4 A

R2

IR4

2 A

R2

IR8

R

2 A

R2

IR8

A

R2

IR16

A

R2

= IR16LSB

iO′

Current switches4

d

MSB LSB

I

iO


144 Chapter 2

Typical BJT DAC design is based on a current-switching R-2R network. An input op-amp establishes a reference current IR in one of several BJTs with emitters connected to an R-2R network. The emitter areas are ratioed with the current each conducts, to maintain the same VE for all BJTs. The BJT collectors drive current switches. These can be differential amplifi ers (diff-amps) with logic-compatible inputs. Their collectors are connected to either the iO or iO′ outputs. CMOS DAC outputs have no voltage compliance, but the BJT current outputs from collectors need not be held at a fi xed voltage.

IL200 nA 37 pF

iO

120 pF

iO

IRn2

IL

200 nA

VR≈10 k Ω

d = 0000

120 pF

iO

IRn2

IL

200 nA

VR≈10 k Ω

′

IL200 nA 37 pF

iO′

(a)

(b)

d = 1111



The R-2R network is not switched but is a multiple binary current divider. The voltage in the series-R string doubles at each successive stage toward the termi-nation at the LSB. The reference current is established by the op-amp circuit as VR/RR. The output is

i W d IO R= ( )⋅

and the complementary output is

′ = − =−⎛

⎝⎜⎞⎠⎟

⋅ −i I i I iO fs O

n

n R O2 1

2

The equation for Ifs applies here. The relationship between IR and Ifs is the same as for the CMOS DAC:

I I I Ifs

n

n R R=−⎛

⎝⎜⎞⎠⎟

⋅ = −2 1

2LSB

The complementary output current is also related to W(d) as

′ = ( )⋅i W d IO R

where

W d b b bin i n i n i

i

n

( ) = ⋅ =−− − −

=∑ 2

0, logical complement of

That is, W—

is the complementary weighting, the result of the bit-wise negation (or one’s complement) of d.

Monotonicity among the LSBs, achieved with the scaled-emitter technique shown below, is used with the ladder network. The LSB terminating current of the ladder network, instead of being grounded, is fed to a second branch of emitter-scaled BJTs that switch the three LSBs. Monotonicity is ensured by branching.


146 Chapter 2

2 A A A

R-2R network

VEE–

A2 A2 A A4 AA

VB2

b4 b3 b2 b1 b0

iO′

iO

-bit DACm

Segmentdecoder

R

VEE–

A A

R

IR

A

R

A

R

A

R

A

R

4s3

iO′

iO

iO′

iO

s2s1s0

md

2

For DACs with a large number of bits, the branching idea can be realized in a different topology. The segmented DAC, shown above for a two-bit segmenta-tion, does current weighting with two networks. The input network is driven by a reference current as before. The two MSBs are decoded by a segment decoder.



They switch four equal currents to either output or to the branching input of an R-2R network of the remaining m LSBs. A segment decoder successively switches more segments with larger MSB codes to iO as the m LSBs divide the current from one segment (s1 in the fi gure) between iO and iO′ . The remaining segment currents go to iO′ . For m = 2, when d ≤ 0011, all segments except s0 are switched to iO′ . When d = 0100, s0 switches to iO, and s1 switches to drive the branch DAC, as shown. The remaining switches stay on iO′ .

Although the branching effect assures monotonicity, the transfer curve linearity can be much worse than the DLE. But in many applications, the DLE is all that matters for linearity. The match of the segment currents does not determine DLE, only the overall linearity. The segmented DAC uses fewer resis-tors since each segment requires only one resistor, not two as in a ladder network.

A very simple DAC design is the serial-output DAC, easily realized by one fi ltered output line of a computer. A PWM generator, either in hardware or software, drives a low-pass fi lter with break frequency far below the PWM frequency. The average output voltage is proportional to the duty-ratio. The disadvantage of this scheme is that it is slow and inherently noisy due to ripple from the fi ltered pulse. But if the pulse amplitude is accurate and the transitions are fast, a high-resolution output is achievable in direct trade-off with response time.

The ripple amplitude varies with pulse duration, which depends on the duty-ratio D. For high or low D, ripple is least and is highest at D = 50%. In steady-state, the ripple extends from vL to vH around the average, DV. The ripple amplitude,

Δv v vH L= −

is derived from the decaying exponential, when the pulse is low:

v vv

vv

ev

DVH L

H H

D T−= = ≅− −( )⋅Δ Δ1 τ

The approximation assumes that ripple is small relative to average output voltage and that vH ≅ D ⋅ V. Also, t is the fi lter time constant. Solving for the ratio of PWM frequency to fi lter break frequency for 1 LSB of ripple,


148 Chapter 2

ff

DD

v Vbw

nPWM

LSB≅ −⋅ −( )−( ) =−

2 11 2π

ln, Δ

For four bits, fPWM must be 23.5 fbw at D = 0.5 and 401 fbw for eight bits. At 10% duty-ratio for four bits, the frequency ratio is only 5.8 and is 8.7 for 90%. (At the extremes of D, the approximation fails. At D = 2−n and D = 1, the ratio is 0.) Other pulse waveforms from rate-multipliers or statistically biased digital pseudo-random noise have less ripple for the same clock-to-fi lter frequency ratio but are harder to generate.

VR

C1

S1

S2

S3

C2

vO

A serial-input DAC is shown above, with three switches and two equal capaci-tors C1 = C2. A serial digital input begins with the LSB. The DAC operates in two phases for each successive bit. On phase 1, switch S3 is open, and a serial input bit closes either S1 (for b = 1) or S2 (for b = 0), charging C1 to

q C b Vi i R= ⋅ ⋅

On phase 2, S1 and S2 are open, and S3 is closed. C2 contains the net charge from previous cycles. On the ith bit on phase 1, this charge is

q C vi i− −= ⋅1 1

On phase 2, S3 closes, and

vq q

CV

bv

ii i R

ii=

+⋅

= ⎛⎝

⎞⎠ ⋅ +− −1 1

2 2 2



For n bits, the voltage is

vV

bV

bV

bnR

nR

nR

n= ⎛⎝

⎞⎠ ⋅ + ⎛

⎝⎞⎠ ⋅ + ⎛

⎝⎞⎠ ⋅ +⎛

⎝⎞⎠

⎛⎝

⎞⎠

⎛⎝

⎞⎠− −

2 4 81 2 . . .

This iterative equation reduces to the closed form of

v b V W d Vni

n ii

n

R R= ⋅⎛⎝

⎞⎠ ⋅ = ( )⋅−

−=∑2

1

After n bits, vn is the converted voltage. It must be stored separately for output during the next conversion. The number of bits of monotonic conversion is limited by capacitor matching and switch leakage.

DIGITAL-TO-ANALOG CONVERTER CIRCUITS

In the fi gure below, a digital-to-analog converter is used as a component in a converter circuit. The DAC schematic symbol is used, with a small circle at iO′ to indicate the complementary output, after the convention of logic symbols. The op-amp output is bipolar and is offset by IR/2 by a resistor of 2R, where R is the current-reference resistor. Without this offset, vO is unipolar, ranging from 0 V to Ifs ⋅ Rf. By shifting iO down by IR/2, vO at negative fs is one VLSB greater in magnitude than positive fs. IR/2 corresponds to the midscale or zero state of d.

–

+

V+RfR2

iO

vO

iO

′

DAC

IR2

R

IR

= ( – )iOIR2

Rf


150 Chapter 2

The offset-binary output is

v iI

R W I RO OR

f R f= −⎛⎝

⎞⎠ ⋅ = −⎛

⎝⎞⎠ ⋅ ⋅

212

Some output values for a four-bit d are tabulated below.

d W - ½

1111 7/16

1000 0

0111 −1/16

0000 −1/2

A two’s complement coding of d produces the same results when the MSB is inverted.

In the following DAC circuit, the output range is symmetric about zero. The op-amp is driven differentially by the DAC output so that

v i R i R i i R W W I R i I RO O O O O R O fs= ⋅ − ′ ⋅ = − ′( )⋅ = −( )⋅ ⋅ = ⋅ −( )⋅2

The expression for vO in terms of W follows from the equations for iO and iO′ .

–

+

R

vO

iO

iO′

DAC

R

= ( – )iO RiO′

Compared with the offset-binary output, the symmetric-offset output range and step size are twice as large because iO′ is used. The last expression of vO, compared with the offset-binary vO, has twice the gain (2 ⋅ iO) and a comparable offset difference of



I I IR fsLSB

2 2 2= −

This leaves the symmetric vO with a VLSB/2 positive offset relative to the offset-binary output. Some four-bit output values are the following:

d W - W—

1111 15/16

1000 1/16

0111 −1/16

0000 −15/16

The extreme states have outputs of equal magnitude while zero is offset by VLSB/2. An inverted output results from exchanging the DAC outputs.

Q4

Q1

Q3

Q2

V+

R R

D1

D2

DAC

I1

I2 IO


152 Chapter 2

A DAC bipolar current source with a current mirror is shown above, taken from “Current Sources.”

Another circuit, one that does not require a current mirror, is shown below. It has similar topology to a Howland current source but is simpler in operation.

i L

–

+

R

vO

iO

iO′

DAC

RSR

1

2

The load current is

iv v

Ri

i R i RR

ii R i R R

RL

O L

SO

O O

SO

O O S

S

=−

− ′ =⋅ − ′ ⋅

− ′ =⋅ − ′ ⋅ +( )1 2 1 2

This reduces to

iRR

i i R R RLS

O O S= ⎛⎝⎜

⎞⎠⎟ ⋅ − ′( ) = +1

1 2,

The differential current output from the DAC is converted into a bipolar single-ended current output.

Because CMOS DACs are passive, switched ladder networks, they can be used “backward” as shown below. The reference voltage is applied across the iO ter-minals, and the voltage output is taken from where the reference voltage is normally applied. This scheme is similar to that of the discrete CMOS DAC without the op-amp. The CMOS switches are driven from the supply voltage VCC, and minimum switch resistance (and linearity error) results by keeping VR well below VCC.



DACs can be combined with op-amps to provide programmable gain. The programmable-gain amplifi er (PGA) in (a) above has a wide gain but can have signifi cant voltage offset errors, whereas in (b) the op-amp gain is limited to ×2. In both circuits, R is included in the DAC IC and matches and tracks the ladder resistances. The noninverting confi gurations are similar in concept. For applications in which the digital input is a dynamic waveform and not merely a scale factor, it is multiplied by vI; the DAC multiplies a digital by an analog quantity.

vODACVR

+

–

R

vO

DAC

vI –

+

(a)

RDAC

vO

–

+

vI

(b)


154 Chapter 2

PARALLEL-FEEDBACK ADCS

The inverse function of D/A conversion is analog-to-digital conversion, per-formed by A/D converters (ADCs). We consider here four categories of ADCs, which include many variations. Approximate ranges for conversion rate and precision are given below.

ADC Type Conversion Rate Precision, Bits

Integrating 0.1 Hz–100 Hz 14–22

Cyclic (serial) 1 kHz–100 kHz 10–16

Parallel-feedback 50 kHz–10 MHz 8–12

Parallel (fl ash) 10 MHz–1 GHz 4–8

Parallel-feedback converters are based on a concept similar to that of placing a function block in the feedback loop of an op-amp to achieve the inverse function.

+

–

nC

REGDAC

CNTR CLK

n

d

RV

Xv

C

The fi gure above shows a digital realization of the ramp converter. A counter driven by a clock generates a digital sawtooth output. It drives a voltage-output DAC that outputs the ramp in analog form. When it crosses vX, the comparator output clocks the register and holds the digital count. When the counter over-fl ows, the DAC output resets to its minimum value, and the comparator output goes low, completing the cycle. The comparator output is also an end-of-conversion signal indicating valid register data.



In the analog realization shown above, the same concept uses an analog current-source ramp generator. The counter overfl ow turns on the reset switch, discharging the capacitor at the end of the conversion cycle. The analog circuit is subject to errors in ramp slope relative to the clock frequency. The digital form, although not having these timing errors, must have an accurate DAC reference voltage.

A third realization of the ramp converter makes use of a microcomputer (μC) (or any computer) and minimal additional hardware: an n-bit DAC and a com-parator. The μC must have one digital input bit from the comparator and n output bits to drive the DAC. The software algorithm for ramp conversion uses software variable, VX, to hold the digitized value of vX, and OUT to hold the DAC output value.

+

–

n

CNTR CLK

REG

CV

n

C

I

vX

d

C


156 Chapter 2

The ramp ADC procedure is as follows:

0. Ramp ADC

1. Set OUT to zero: OUT ← 0.

2. Input the IN bit.

3. If IN = 0, then VX ← OUT; go to 1. Else increment OUT: OUT ← OUT + 1.

4. Output OUT; go to 2.

Conversion time is usually limited by the μC; however, for many applications, it is fast enough, and the few additional components are an advantage. The ramp ADC is a poor technique and is seldom used. The conversion time varies but can take up to 2n clock periods.

–

DAC

Xv

OUT

IN

C

n

+

μ

DAC

Xv

n

LOGIC+

–

d

CLK

Ramp ADC: counterTracking ADC: up/down counterSuccessive-approximation ADC: SAR

Parallel-feedback converters have a generalized topology. The type of logic block used determines the type of converter. The ramp ADC uses a simple counter. A slightly better ADC is the tracking converter. Its logic is a bidirectional



(up/down) counter. As vX changes, the comparator output causes the counter to count up if the DAC input d is low and down if it is high. The counter servos the DAC to minimize input error at the comparator. Since the counter counts either up or down, the error is always ±1 LSB. For a constant input, a converged counter dithers by one state around the correct value; the comparator output alternates logic levels each clock cycle.

The tracking ADC is an improvement over the ramp ADC because it can be used to follow an input waveform, digitizing it as it occurs (that is, in real time). For small input changes, the counter must change only a few states. This is done in a few clock periods, and conversion is fast. For large input changes, such as a square-wave step, the converter shows slew-rate limitations and a longer conver-sion time. The DAC output tracking slew-rate, if limited by the counting rate, is

dWdt

Vffs

n= ⋅

2CLK

The clock frequency is limited by the loop delay time: the DAC settling time, comparator delay time, and counter clock-to-output time. For a sinusoidal input,

v tV

tXfs( ) = ⋅ ⋅( )

2sin ω

its maximum slew-rate is w ⋅ Vfs/2 = p ⋅ f ⋅ Vfs. Equating to the tracking slew-rate and solving for the maximum fs sine frequency,

max fs sine CLKf fn

=⋅

⎛⎝⎜

⎞⎠⎟

⋅12π

The tracking converter can be implemented with the same hardware as the ramp converter. The general μC-based parallel-feedback ADC also applies gen-erally to parallel-feedback converters. Instead of hardware logic, the software logic distinguishes among parallel-feedback ADC types. A tracking ADC proce-dure, based on the same software variables as the ramp ADC, is given below,


158 Chapter 2

0. Tracking ADC

1. Output OUT.

2. Input IN.

3. If IN = 0, then decrement OUT: OUT ← OUT − 1. Else, increment OUT: OUT ← OUT + 1.

4. Set VX to OUT: VX ← OUT.

5. Go to 1.

This procedure is not more complicated than that for the ramp converter but has the performance advantages of the tracking ADC.

The tracking ADC is useful as a track-and-hold (T/H) circuit. The digital output follows the input signal until the clock is gated off or the count clocked into another register. Then the input value, in digital form, is held indefi nitely; no analog hold circuit can do this. As for sampling circuits, and also for peak detectors, a capacitor can accurately maintain its charge for only a limited time.

–

+

RvX

Oi

DAC

Parallel-feedback ADCs compare DAC voltage to vX at the comparator input, as shown previously. Current-output DACs require an additional I-to-V converter stage. In the ADC scheme above, a current-output, bipolar or CMOS, DAC forms a voltage difference with vX by dropping iO ⋅ R in series with it. The comparator now senses this difference against 0 V. This current-mode comparison works with bipolar inputs. The inputs of the comparator must be reversed from voltage-mode comparison, or the complementary current output of the DAC must be used instead.



A third parallel-feedback converter is the successive-approximation (SA) converter, a very common conversion technique and the most popular of the parallel-feedback converters. It takes n + 1 clock cycles to convert n bits using a bit-wise iterative algorithm. It determines one bit per clock cycle after an initial-ization cycle.

The parallel-feedback ADC logic block is a successive-approximation register (SAR). This register can be realized by an n-bit shift register (SR) and n latches. (A latch is a kind of fl op with a level-sensitive clock input. When the clock is asserted [high], its output follows its input. When the clock is unasserted [low], the output remains the value at the falling edge of the clock.) At the start of conversion, the SR bits are cleared, and the MSB is set. The latch feeds this digital midscale value to the DAC. If vX is larger than midscale, the comparator output is high. When the clock goes low, the MSB is latched. The next clock edge shifts the 1 bit in the SR to the n − 1 bit position, and the cycle is repeated. In effect, beginning with the MSB, n decisions are made, each of which narrows the range of possible values for vX by half. The convergence rate of this proce-dure is on the order of log2(n), and the conversion time is independent of vX.

C SR

SARCarry bit

Shift register

SA latch

The generic μC-based hardware is again used to implement a μC-based SA ADC. The procedure is only slightly more complicated than previous ones but is usually well worth the speed increase. Besides the IN and OUT address loca-tions, the software model is shown above. SAR is a variable that emulates the SAR latch. Variable SR emulates the shift register, which has an additional “carry-bit” stage that is included in the shift loop, as shown. This formulation suggests the effi ciency of assembly-language programming because most μCs have a carry bit and a “rotate right” instruction that includes the carry bit (C). Both software variables can be held in μC registers.


160 Chapter 2

In the following procedure, bit-wise logic operations of AND, OR, and NOT (logic negation) are used and are μC instructions. For μCs without a NOT instruction, X is complemented by using the exclusive-OR (EOR or XOR) instruction with binary 1111 . . . (all binary ones, a two’s-complement −1, or hexadecimal FFF . . .) and X.

0. Successive-approximation ADC

1. Clear SR and SAR: SR ← 0; SAR ← 0. Set C to one: C ← 1.

2. Rotate SR right.

3. If C = 1, then return.

4. SAR ← SAR OR SR

5. Output SAR to OUT: OUT ← SAR.

6. Input from IN.

7. If IN = 1, then go to 2.

Else, set SAR to SAR AND S—R : SAR ← SAR AND (NOT SR).

(Alternative: SAR ← SAR AND (SR EOR 1111 . . .).

8. Go to 2.

The 1 bit, initially in C, is shifted right, into SR, one bit per iteration. When it gets back to C (step 3 checks this), the procedure is done. Step 4 sets the SR 1 bit in the SAR. If the comparator (IN) is high, vX is still greater than the SAR value, and this test bit is left set. If IN is low, the set bit made SAR too large, and it is cleared in step 7. Each bit, beginning at the MSB, is tested and then left set or cleared in SAR.

A speed enhancement for SA converters is to increase the clock rate after the fi rst or second bit is determined. These bits have the most range and require the most slew time of the loop hardware. The less-signifi cant bits cause less comparator voltage change and can be determined more quickly, allowing an increased clock frequency at the expense of more digital hardware.

The ramp and SA converters do not function correctly unless vX is constant during conversion. For dynamic inputs, a sample-and-hold (S/H) circuit must precede the ADC.



INTEGRATING ADCS

–

+

R

–

+REGC

C

vOvX

VR

CNTRRV

C CLKRC

Toggle flopCounteroverflow

n

n

NX

A second category of ADC integrates vX and outputs its average value over the conversion period. The dual-slope ADC shown above is an instance. The input to an op-amp integrator is switched between input vX < 0 and positive voltage reference VR. The integrator output zero-crossing is detected by a comparator, and the count of a free-running counter is clocked as the digitized output. The conversion starts when the counter is reset and vX is switched into the integrator. The ramp output has a slope of −vX/RC and ramps up until the counter over-fl ows. For an n-bit counter, this phase lasts 2n clock cycles or T amount of time. In the second phase, the reference is integrated instead. Because its polarity is opposite that of vX, the slope changes polarity, as shown in the graph below.

vΔ

t XT

O

vO

VRRC

vXRC

––


162 Chapter 2

When the integrator output crosses zero, the comparator latches the count. The second phase lasts for tX time. The converter then begins another cycle.

The change in integrator output voltage, ΔvO, is the same for both phases:

ΔvvRC

TVRC

t tvV

TOX R

X XX

R

= ⋅ = ⋅ ⇒ = ⎛⎝⎜

⎞⎠⎟ ⋅

For a constant-frequency clock, the counts relate to the times by

N f t= ⋅CLK Δ

Therefore, the output count is

NvV

XX

R

n= ⎛⎝⎜

⎞⎠⎟ ⋅2

Dual-slope converter accuracy is not dependent on long-term drift in R, C, or fCLK, only VR. What this analysis assumes is a perfect op-amp and comparator. Their input offsets and delay times degrade converter accuracy.

+

–

R

vX

C

+

–

vO

+

–

Most actual dual-slope converters correct for offset by introducing a third auto-zero phase before phase 1. In addition, for digital voltmeters (DVMs), a high input impedance is desired, and a buffer amplifi er is added before the



integrator. An alternative is the noninverting integrator shown above. If the DVM ground is “fl oating” (not connected) to the measured source, then the ×1 buffer provides high input impedance as it supplies the charging current for C through R.

Bipolar inputs require another reference, −VR. Reference selection is deter-mined by the comparator output at the end of phase 1. Another design option for bipolar inputs is to exchange the input terminals by switching. This scheme, however, has diffi culty with vX near zero. Offsets can cause the readings for +vX and −vX to have different magnitudes. More signifi cantly, when offsets dominate the input, the converter can integrate with the wrong (shallow) slope. When the reference is integrated, it is of the same polarity, and vO never crosses zero. To avoid switching in the wrong polarity of reference, hysteresis around zero is sometimes added. But all of this is avoided with two references.

Another input circuit is a V/I converter and a current reference. This elimi-nates R from the integrator and could also eliminate the op-amp in some designs.

The accuracy of the dual-slope ADC is extended by the triple-slope ADC. An additional comparator senses that vO is approaching 0 V and switches in a smaller reference and another counter. The slope magnitude decreases for this next phase and the time duration is extended. The extra counts contribute additional LSBs.

–

+

R

–

+REGC

vOvX

CNTRV

C CLK

S

R

RS flop

n

n

NX

Q

–V R

VCR

C


164 Chapter 2

At somewhat less speed, the simpler modifi ed dual-slope converter uses only one switch and integrates the input during both phases. In phase 1, the negative reference −VR is integrated along with the input. If VR > ⎪vX⎪, the integrator output has a positive slope. When it reaches comparator threshold voltage VC, the reference is switched off, and vX integrates until the counter overfl ows at T. The integrator voltage, vO, at this time depends on vX. The next conversion cycle thus begins at a different initial vO.

t

VC

vO

VR

t X

T

vO ( + 1)i

v X –∝ v X∝

The conditions for convergence of vO (and a steady digitized value) are found by solving for vO(i) where i is the cycle index. For the new cycle,

v i v i u t i d T t iO O X X+( ) = ( ) + ⋅ ( ) + ⋅ − ( )[ ]1

where the slopes are

uv V

RCV v

RCd

vRC

v VX R R X XX R= −

−=

−= − >, ; , 0

Also, from the v-t graph,

t iV v i

uV v iV v

RCXC O C O

R X

( ) =− ( )

=− ( )−

⋅



Substituting for tX in vO(i + 1) gives

v idu

v i Vdu

dT a v i bO O C O+( ) = ⎛⎝

⎞⎠ ⋅ ( ) + ⋅ −⎛

⎝⎞⎠ +⎡

⎣⎢⎤⎦⎥

= ⋅ ( ) +1 1

This difference equation is solved by expanding several iterations, beginning with i = 0. The resulting recursion equation for i + 1 = n is

v n a vaa

b aOn

O

n

( ) = ⋅ ( ) + −−

⎛⎝⎜

⎞⎠⎟

⋅ <011

1,

and is attained by using the geometric-series formula

zzz

zk

k

N N

=

−

∑ = −−

<0

1 11

1,

The series converges only when ⎪z⎪ decreases with increasing k. For the con-verter, the convergence condition is

du

d uvRC

V vRC

vVX R X

XR< ⇒ − < ⇒ <

−⇒ <1

2

That is, vX must not exceed half the reference voltage VR. Or, in time, tX < T/2. The converged (steady-state) value of vO can be found by letting n go to infi nity in vO(n) or by setting

v i v iO O+( ) = ( )1

in vO(n + 1) and solving for vO:

v Vu d

u dTO C= +

⋅−

⎛⎝

⎞⎠ ⋅

where the second term is always negative, as required for vO < VC. With vO, the steady-state tX from tX(i), is


166 Chapter 2

td

u dT

vV

TXX

R

= −−

⎛⎝

⎞⎠ ⋅ = ⎛

⎝⎜⎞⎠⎟ ⋅

But this is the same as the previous tX, and the digital output is expressed by NX. The modifi ed dual-slope converter has the same transfer characteristic as the dual-slope ADC, though its dynamic response is fi rst-order and takes a few cycles to converge.

In this realization of the modifi ed dual-slope ADC, the Rs must match. VC need not be accurate – only stable during convergence. Both Rs can be elimi-nated by driving the integrator with a V/I converter for vX and replacing R and −VR with IR. The switch must then be a current switch. This can be accomplished by letting the fl op output divert IR through a diode. For low leakage, a transistor is used instead. The RS fl op consists of two cross-coupled NOR gates. The other two gates in a quad NOR-gate IC implement the clock generator.

Because tX must be kept less than T/2 for stability, the fs tX is set at T/4 by adding two additional bits to the counter (for n + 2 bits total). This wastes 50% of the available integration time but is easy to implement (by a dual-fl op IC) and gives the converter a near-100% overrange capability, an additional half-digit. Besides the register and counter, the total parts count is less than a dozen to implement a three-digit DVM. (A featureless converter such as this is usually called a digital panel meter [DPM].)

–

+

R

–

+

C

vOvX

CLK

–V R

RQD

C



Dual-slope ADCs require a large vO range to achieve precision. An idea that is the digital analog of the virtual ground is realized in the charge-balancing (or quantizing or sigma-delta, Σ-Δ) ADC, shown above. The circuit topology is very similar to the modifi ed dual-slope ADC, but it works differently. The big circuit difference is that the fl op driven by the comparator is clocked, a D-type fl op instead of an RS fl op.

On a given cycle of the clock, the reference is switched in or out of the inte-grator to keep vO near ground. The comparator output gives the sign of the error. In other words, vO is nulled by discrete-time feedback. The number of clock cycles that the fl op was high, NX, over the total number of conversion counts N, indicates vX.

The transfer characteristic is calculated by constructing the charge-balance equation for the total charge from vX and −VR input to the integrator. For vO = 0, they must be equal, or

Q QX R=

These charges are the sums of the per-cycle charges:

qvR

T qVR

TXX

RR= ⎛

⎝⎞⎠ ⋅ = ⎛

⎝⎞⎠ ⋅CLK CLK,

The total charge of each depends on the number of cycles each is integrated. Then

Q q NvR

N T Q q NVR

N TX XX

R R XR

X= ⋅ = ⎛⎝

⎞⎠ ⋅ ⋅ = ⋅ = ⎛

⎝⎞⎠ ⋅ ⋅CLK CLK,

Then substituting into QX and solving for the output,

NvV

NvV

XX

R

X

R

n= ⎛⎝⎜

⎞⎠⎟ ⋅ = ⎛

⎝⎜⎞⎠⎟ ⋅2

for an n-bit conversion-time counter. This result is, again, the same as for the previous converters.


168 Chapter 2

The charge-balancing circuit is also used as a modulator for serial digital telecommunications (in CODECs) and in audio and speech processing.

An advantage of the integrating ADC is its measurement of the average vX. By integrating, it has inherent noise rejection and does not need a S/H circuit. The noise rejection capability is quantifi ed by beginning with a constant VX with sinusoidal noise added:

v V V tX X N N= + ⋅sinω

The integrator averages vX over the conversion period T, so that

avg vT

v dt VV

TTX X

TX

N

NN= ⋅ ⋅ = + ⋅ −( )∫

11

0 ωωcos

The normal-mode rejection (NMR) of the noise is

NMRinput noise

output noise= = ( )⋅ −( )

=−

VV T T

TT

N

N N N

N

Nω ωω

ω1 1cos cos

For wN = 2p ⋅ fN, and 1 − cos(2x) = 2 ⋅ sin2 x, then

NMR =⋅ ⋅

⋅ ⋅( )π

πf T

f TN

Nsin2

In the decibel scale this is

NMR dB NMR( ) = ⋅ = ⋅ ⋅ ⋅( ) − ⋅ ⋅( )[ ]{ }20 20 2log log log sinπ πf T f TN N

NMR is plotted below on a log-log graph, for T = 1/60 Hz, and fN from 0.1 Hz to 1 kHz.



At fN = n/T, for whole-number n, NMR is infi nite. In practice it is typically about 60 dB of rejection. An exact number of noise cycles fi t the integration interval T, and the sum of the areas of their positive and negative half-cycles cancel, as in (a) below.

1·103

100NMR(f)

fHz

NMRmin(f)

10

10.1 1 10 100 1·103

vN

tT

tT

(a)

(b)

n = 1 n = 3


170 Chapter 2

As fN varies from n/T, the half-cycles of noise at the ends of the interval are truncated and contribute some fraction of a half-cycle. Figure (b) shows the second worst case after that of fN = 0.5/T, in which an entire extra positive half-cycle is integrated at fN = 1.5/T. For rejection of power-line noise, fN is often chosen to be a multiple of the power-line frequency.

More signifi cant are the NMR minima of p ⋅ fN ⋅ T. They occur midway between the maxima, at fN = 1.5 ⋅ n/T. As fN increases, according to NMR(dB), the NMR minima increase at 20 dB/dec. At noise frequencies of about n times 1/T, about n cycles of noise occur during T. The more half-cycles, the less each contributes to the integrated total. Thus, a fraction more of a half-cycle contributes less error the higher fN is. Note that NMR is the reciprocal of the integrator fre-quency response, which rolls off at 20 dB/dec with periodic notch fi lters.

SIMPLE mC-BASED S-D ADCS

Microcontrollers (μCs) often contain a comparator that can implement a precise ADC with the addition of only an external resistor and capacitor. The technique is to implement a charge-balancing or Σ-Δ (or Δ-Σ) ADC. The basic scheme uses a comparator that outputs μC input bit IN and requires one μC output bit, OUT. The circuit is shown below.

+

–

C

OUT

INXV

cV

R

In μC software, the ADC routine is best implemented as an interrupt routine, driven by a timer of period tINT, the interrupt period. In the circuit above, the ADC reference voltage is the μC supply (VR = VCC). This assumes that the μC has



CMOS output bits, so that the outputs for negligible current are near the rails:

OUT bit CMOS levels:V ground0 0

1

→ ( )→

⎧⎨⎩ VCC

If greater accuracy than VCC is required, instead of driving R directly from OUT, use it to switch accurate analog switches between reference ground (for 0) and an accurate VR (for 1). If the OUT-bit voltage levels are close enough to the rails, then an accurate VCC can be supplied as the reference.

S-D RC Constraint for n-Bit Accuracy

The charge-balance voltage waveform on the capacitor is a constant voltage with a small exponential ripple riding on it, at the frequency of the OUT switch-ing. If this varying voltage becomes too large, the ADC will not be linear enough for n-bit conversion. The larger is the RC time constant, the smaller the ripple. How large must RC be to ensure n bits of linearity? The ripple voltage,

Δv v v V VC H L LSBn

R= − ≤ = ⋅−2

and

Δvv

vv

eC

H

L

H

t R CINT= − = − − ⋅1 1

where vH and vL are the maximum and minimum of vC. At full scale, vH = VR and

2 1− − ⋅≥ −n t R Ce INT

or

R Ct

t nINT

n

nINT⋅ ≥

−( )≅ ⋅ >>

− −ln,

1 22 11


172 Chapter 2

For tINT = 1 ms, and n = 8 bits, then R ⋅ C ≥ 256 ms. For n = 10, R ⋅ C ≥ 1.024 s. The allowable measurement rate is comparable to that of DMMs.

S-D Algorithm

The ADC algorithm, coded as part of the interrupt routine, sets or clears OUT to keep vC = vX. In other words, charge balance is maintained on C so that Δq = 0. This can be expressed using Δq = i ⋅ Δt, where i = v/R:

V vR

NvR

N NR XX

XX

−⋅ = ⋅ −( )

or

NN

vV

X X

R

=

where N is the number of tINT cycles during the measurement. After N intervals, the measurement ends, and the NX accumulated during this measurement inter-val is related to vX by N and VR:

vVN

NXR

X= ⎛⎝

⎞⎠ ⋅

N is a software parameter and VR = VCC of the μC. For each interrupt, the fol-lowing routine is executed:

If IN = 1: OUT ← 1; increment NX

If IN = 0: OUT ← 0

At the end of the measurement, after N interrupts (or intervals of tINT), then execute:

measured NX ← NX

Reset NX ← 0



Unmatched RU and RL

A refi nement that can be brought to the minimalist ADC is to account for dif-ferent resistance values in series with the OUT switches. Let RU be the series resistance when OUT = 1 (high) and RL when it is 0 (low). Then

V vR

NvR

N NR X

UX

X

LX

−⋅ = ⋅ −( )

Given the two switch resistance values, the measured voltage, as a fraction of the reference voltage is

vV

RR

N

NRR

N

X

R

L

UX

L

UX

=

⎛⎝⎜

⎞⎠⎟ ⋅

− −⎛⎝⎜

⎞⎠⎟ ⋅1

This equation presents the onerous μC task of division, despite the pre-calculated constant, RL/RU. This refi nement is best left for DSPs, which usually facilitate division. As μCs become like DSPs, this improvement becomes feasible to implement.

Auto-Calibration

A more elegant method of producing an accurate measurement without external reference switching can be applied to systems in which multiple chan-nels are multiplexed into the ADC. If two additional MUX inputs are available and the ADC is linear, two-point calibration can be applied. Two reference volt-ages, which can be 0 V and VR, are applied to the ADC, resulting in NX(0 V) = N0 and NX(VR) = NR. A plot of vX versus NX will then have two known points on it, corresponding to the known input voltages. The equation for the calibration line is

vV VN N

N VXR os

RX os=

−−

⎛⎝⎜

⎞⎠⎟

⋅ +0


174 Chapter 2

where the expression in parentheses is the slope of the line. In general, the offset voltage, Vos, can be of either polarity, requiring negative NX. To get around this, two precision resistors forming a divider from VR can provide instead a known accurate voltage of a ⋅ VR, where a is the attenuation ratio of the divider. For this more general case, the equation of the line can be written by equating slope expressions

v VN N

V VN N

X R

X

R R

R

− ⋅−

=− ⋅

−α α

α α

Solving for vX,

vN NN N

V m VXX

RR R=

−−

⎛⎝⎜

⎞⎠⎟

⋅ −( ) +⎡⎣⎢

⎤⎦⎥⋅ = ⋅ −( ) +[ ]⋅α

αα α α α1 1

By making a = 1/2, then m must be divided by two, a right-shift instruction. To add ½ to it for rounding, increment m before right-shifting. The resulting number is the fraction of VR that is vX.

Inverting S-D ADC

An inverting Σ-Δ converter uses one additional resistor, as shown below.

+

–X

C

IN

OUT

V

RV

RR

XR



The RC time constants must still be much greater than tINT; a low OUT is 0 V, and a high level is VCC = a ⋅ VR. Charge balance on the capacitor is maintained by the ADC algorithm, keeping VC = VR. This results in ΔQ = 0 C:

v VR

NV V

RN

VR

N NX R

X

CC R

RX

R

RX

−⋅ +

−⋅ = ⋅ −( )

or

vV

RR

aNN

X

R

X

R

X= ⋅ − ⋅⎛⎝

⎞⎠ +1 1

For RX = RR, and a = 2, then

vV

NN

X

R

X= ⋅ −⎛⎝

⎞⎠2 1

The following chart summarizes the transfer function.

NX vX

0 2 ⋅ VR = VCC

N/2 VR

N 0 V

The interrupt routine for the ADC is given below:

If IN = 1: OUT ← 0; increment NX

If IN = 0: OUT ← 1

At the end of the measurement, after N interrupts (N intervals of tINT), then execute the following routine:

measured NX ← NX

Reset NX ← 0


176 Chapter 2

These minimal-component ADCs are often adequate for slow, low- to medium-precision, μC-based ADC requirements. Besides few components, other advantages of the Σ-Δ ADC are that it does not need an anti-aliasing fi lter or S/H circuit preceding its input. Its integrating function reduces noise band-width of the measurement. It is an optimal solution for many μC-based applications.

The inverting Σ-Δ ADC input circuit could be extended to have a second-order, cascaded RC fi lter using the same software routine, with a total of four external resistors and two capacitors. This adumbration is left to the imagi-nation of the reader. With suffi ciently low tINT, which is achievable on faster μCs and DSPs, high precision can be attained with a medium-performance comparator.

VOLTAGE-TO-FREQUENCY CONVERTERS

A special kind of integrating ADC converts input voltage or current to a pulse frequency. It is a kind of linear voltage-controlled oscillator (VCO) or FM modu-lator with digital output. The topology of the voltage-to-frequency (V/F) converter is similar to previous integrating ADCs.

VC

–

+–

+vfMMV

vO

–VR

R

vX

CR



As with parallel-feedback converters, the topological variations among inte-grating ADCs is in the logic block driven by the comparator. For the asynchronous VFC, a MMV replaces the fl op of the charge-balancing converter.

vO

VC

t

vf

t

ΔvOu d

Operation resembles the modifi ed dual-slope ADC. When the integrator output vO goes below VC, the comparator output goes high, triggering the MMV and turning on the reference switch. The MMV time-out is th, the time that the output pulse vf is high. During th, vO ramps up with a slope of u. When the MMV times out, the reference is switched out, and vX > 0 causes vO to ramp down with slope d. Slopes u and d are the same as those for the modifi ed dual-slope ADC. The change in vO over one cycle is

Δv u tV v

R CtO h

R Xh= ⋅ =

−⋅

⋅

From this,

tvd

Vv

tlO R

Xh= − = −⎛

⎝⎜⎞⎠⎟ ⋅Δ

1


178 Chapter 2

The output period is the sum of the half-cycles, or

T t tVv

t tVv

th lR

Xh h

R

xh= + = −⎛

⎝⎜⎞⎠⎟ ⋅ + = ⋅1

Finally, the output frequency is

fT

vV t

X

R h

= = ⎛⎝⎜

⎞⎠⎟ ⋅1 1

This formula is similar to that of previous integrating ADCs except that it depends on th, the MMV time-out duration, instead of a counter overfl ow period. Because th is typically set by an RC circuit, asynchronous VFC accuracy is limited by it. The accuracy also depends on the matching of the R , but the analysis could have been based on an input current iX and reference current IR instead. The resistors are implementation-dependent and not fundamental to the oper-ating principle.

The LM331 is an eight-pin VFC IC, shown below in (a). Instead of using an op-amp integrator, it avoids op-amp error by integrating with a shunt RC that is maintained at vX. The shunt RC voltage vO must be kept small to avoid nonlin-earity. If the exponential waveforms of vO (b) have a time constant RC that is much larger than th, they are approximately linear.

By keeping vO ≅ vX, the LM331 performs charge balancing at vO. The charge through R over T must be the reference charge during T, or

vR

TvR

T I t t RCO XR h h⋅ ≅ ⋅ = ⋅ <<,

Solving for f = 1/T,

fv

R I tt RCX

R hh=

⋅⎛⎝⎜

⎞⎠⎟

⋅ <<1,

Also, IR ≅ 1.9 V/RR.



This result is also valid for a charge-balancing VFC with a linear integrator but without the constraint. The typical fs frequency is 10 kHz at an output duty-ratio of 50%. Unlike the modifi ed dual-slope ADC, no convergence condition exists, but as tl approaches zero, the fs frequency asymptotically approaches 1/th

VCC

VCC

VCC23

Rh

Ch

5

MMV

Current mirror

VCC

VCC

IR

R C vO

6

7vX +

–

+

–

1.9 V

IR 2

RR

3 vf

+

–1.9 V

LM331

vO

vX

τΔ

= RCvO ≈ 0 V

t

t l

t

vf

f =vX

I R R ⋅ 1th

, th << RC

(a)

(b)

S Q

R Q

–

+


180 Chapter 2

of 20 kHz. When the MMV timing is based on a threshold voltage of (2/3) ⋅ VCC, then

t R C R Ch h h h h= ⋅ ⋅ ≅ ⋅ ⋅ln .3 1 1

A more precise analysis, calculated from the exponential vO, yields a period of

T R CI Rv

eR

X

t R Ch= ⋅ ⋅⋅⎛

⎝⎜⎞⎠⎟ ⋅ −( ) +⎡

⎣⎢⎤⎦⎥

− ⋅ln 1 1

For th << RC,

e t RCh− −( ) ≅1 0

Apply the approximations

ln , ; ,1 0 1 0+( ) ≅ ≅ ≅ + ≅x x x e x xx

to T:

T R CI Rv

tR C

I Rv

t t RR

X

h R

xh h≅ ⋅ ⋅

⋅⎛⎝⎜

⎞⎠⎟ ⋅

⋅⎛⎝⎜

⎞⎠⎟

⎡⎣⎢

⎤⎦⎥

=⋅⎛

⎝⎜⎞⎠⎟ ⋅ <<, CC

This period is consistent with the asynchronous-VFC f. For applications in which a compressed scale for vX is desired, the nonlinearity of this converter can be advantageous, thereby invoking the adage, “If you can’t fi x it, feature it.”

The VFC is most sensitive to noise at zero scale (zs), when the down-slope d is shallowest, causing comparator output jitter among crossings of its threshold and thereby jittering f. However, the VFC is an integrating type of ADC because a frequency measurement requires counting vf over a known period. This count-ing function is the digital equivalent of integration. The longer the count inter-val, the more the input is averaged, the greater the precision, and also the slower the conversion rate. For faster conversion at the same precision, the fs frequency



must be increased. By changing count intervals, we can make speed-precision trade-offs without a converter change.

The drift in MMV th can be averted by using a digital timer with an accurate clock. Then th would, on the average, be accurate. Because the clock is asyn-chronous with the comparator output, the timer has phase jitter and the time-out varies up to a complete clock cycle. Elaborate schemes have been devised to synchronize a digital counter with an asynchronous trigger to produce an accurate time-out. One simpler scheme combines an analog ramp generator with a counter. The ramp slope is set to VC/TCLK, where VC is a comparator threshold. The trigger starts the ramp. It runs up until the active clock edge occurs. The ramp output is held constant until the counter overfl ows. (More likely, it is a down counter that underfl ows.) The ramp is restarted. When it crosses VC, the comparator signals the time-out. The counter counts one less cycle than is required for the time-out because the ramp generator adds a cycle. Its slope error affects the time-out as an error in only one clock period.

CLK

Q

Q

D

C

VC

vOVR

Switch

Comparatoroutput

CLK

Q

(a)

(b)

–

+

Instead of substituting a clocked timer for the MMV, the synchronous (or clocked) VFC (fi gure a) operates similar to the charge-balancing ADC except that the reference is turned on for only one clock cycle at a time. The


182 Chapter 2

comparator output switches the reference only at the active clock edge (b). The D-fl op input is gated to enable its output to be high for the cycle, thus generat-ing the output pulse. In commercial synchronous VFCs, the fl op output triggers a MMV that sets the output pulse width.

Comparatoroutput

CLK

φ

vO φ delay = 0+

φ delay = (2 )–

π– 2

0

π

The dual-slope waveform of vO is synchronous with the clock only at discrete values of vX. For vX between these quantum levels, the average level of vO slowly drifts due to accumulating phase error. The comparator edge drifts relative to the clock, causing the reference on-time to change linearly. This causes the average level of vO to ramp up or down. When the phase between comparator and clock outputs drifts by a full clock cycle (or 2p radians of phase), the comparator and clock are again in sync; vO has drifted to a quantum level where the phase error is zero. Comparator and clock edges can coincide, and the output can be indeterminate for some time, causing frequency jitter. A trigger-generator circuit is required for synchronizing edges, for higher performance.

PARALLEL AND RECURSIVE CONVERSION TECHNIQUES

The fastest ADCs are parallel or fl ash converters. They have a resistive-divider string of 2n resistors for an n-bit converter. Each resistor drops VLSB and sets the reference input on one of 2n latching comparators that drive an encoder. A clock stores the data as 2n decisions are made simultaneously: 2n − 1 for n bits



of conversion plus one for overrange detection. No S/H function is required. Because the circuit complexity grows exponentially with the number of bits, these converters trade off cost, simplicity, and low power for speed. Also with complexity comes a loss of precision because many parts must meet design tol-erances. Integration on a single chip helps alleviate the burden of matching parts.

Parallel ADC power is reduced by CMOS implementation. Switched-capacitor comparators designed from CMOS logic inverters reduce power over BJT com-parators and can be easily auto-zeroed. But for many applications, the optimum criteria are less complexity and more precision at somewhat reduced speed. This has led to conversion topologies that use m-bit parallel ADCs to digitize n > m bits by iteration.

Σ

DAC

–

mvX

ADC2

m

n – m

MSBs

LSBs

ADC1

× 2m+

The multistage or subranging fl ash converter has two stages of fl ash ADCs. The fi rst ADC converts m bits. These MSBs drive a DAC. Its output is subtracted from the input. This remainder or residue is a fraction of one VLSB of the fi rst con-verter. It is the difference between vX and the m-bit quantized vX. The second ADC converts this remainder for the remaining n − m LSBs. If its input range is the same as ADC1, then each VLSB (each step) of ADC1 spans the input range of ADC2, and the remainder must be multiplied by 2m for correct scaling. Con-sequently, ADC1 must have n-bit accuracy in the placement of its voltage levels or steps. Also, to avoid misalignment in time, or phase error, subtraction from vX requires that vX be delayed by the same amount as the path delay of ADC1 and the DAC.


184 Chapter 2

This idea can be taken further. To save on ADCs and DACs, the recursive sub-ranging ADC has a feedback topology instead of the feedforward topology of the multistage fl ash ADC. In effect, it is a parallel-feedback converter with an m-bit comparator (the ADC) instead of the usual one-bit comparator. It requires n/m iterations or cycles for n-bit conversion. For each iteration, beginning with the m MSBs, the ADC output is stored in m bits of an n-bit output register. The multiplexer (MUX) directs the bits. The PGA gain is increased by 2m each itera-tion. This ADC technique requires a hold circuit for vX.

Σ ADC+

–

vXn

PGA MUX REGm

DACn

+

–

Σ +

–

× 2+

–

Σ × 2

0 V

VR2

bn–1(MSB)

vX

+–

bn–2

VR2

VR2

The multistage idea can be taken to its limits by converting one bit per stage. In this n-stage fl ash ADC, each ADC is a comparator designed to have accurate output levels of 0 V and VR/2. Instead of iterating in time, this design iterates



hardware stages. It needs no hold on vX since vX ripples through the stages, being processed as it goes, much like a distributed amplifi er. Because it is a bit-wise converter, it implements the SA algorithm in space (hardware) instead of in time as the SA ADC does:

v v bV

i i iR= ⋅ − ⋅⎛⎝

⎞⎠

⎛⎝

⎞⎠+ +2

21 1

where vn = vX.

Σvi + 1 v × 2

+

–b i + 1

vi

VR

+

–

This same idea has been used recursively in John Fluke Co. DVMs, called the recirculating-remainder or cyclic converter, shown above. It follows a similar recur-sive equation:

v v Vi i R= ⋅ −+2 1

where vn = vX. In the n-stage fl ash ADC, the remainder passed to the next stage is always positive. Here, the error is bipolar; its sign determines the bit. It is made positive by ⎪v⎪, amplifi ed by two and then subtracts VR. The block diagram above can be repeated, like the n-stage fl ash, or a S/H can hold the output for recirculation n times.

The serial bit output is ordered MSB fi rst, but the encoding is in Gray code. This code is commonly used in mechanical shaft position encoders because only one bit changes between adjacent states. If the bit outputs are misaligned, an error of only ±1 LSB occurs. Gray-code encoders are used in fast fl ash


186 Chapter 2

converters for the same reason: Any time-skew among output bits between two successive outputs results in at most 1 LSB of error. Gray code is converted to offset binary by the formula

b b gi i i= ⊕+1

where bi are output offset-binary bits, gi are input Gray-code bits, and ⊕ is the exclusive-OR logic operation.

TIME-DOMAIN SAMPLING THEORY

The explanation of A/D conversion assumes that a voltage at one point in time is converted. For a dynamic input, some means of sampling a voltage at an instant and holding this voltage constant is essential to the conversion process. Even fl ash converters require that all comparators sense vX at the same instant. Delays in the latching clock and the inputs among comparators causes this time instant to be instead a time interval ta, called the aperture uncertainty or aperture jitter. Besides this, there is delay from the clock edge to when the input is actu-ally sampled, or aperture delay.

Aperture jitter limits the maximum sine frequency of vX that can be digitized. For a frequency f, all comparators must settle within one VLSB or 2−n ⋅ Vfs for n bits. The sine slew-rate is 2p ⋅ f ⋅ Vfs for the worst case. Then ta must be less than the time taken to slew 1 LSB, or VLSB; that is,

tV

dV dtV

f V fa

nfs

fsn

< ( ) =⋅

⋅ ⋅=

⋅ ⋅

−

+LSB

max2

21

2 1π π

The maximum sine frequency for a given aperture jitter is thus

max sine ftna

=⋅ ⋅+

12 1 π

An eight-bit converter with 100 ps aperture jitter has a maximum digitizing bandwidth of about 6 MHz. By its nature, aperture jitter is a statistical quantity, leading to root mean square (rms) values of the quantities calculated with it.



ADCs that require their input to be held constant over their full conversion period must be preceded by a sampling circuit that then holds the sampled value constant. These are S/H circuits. DACs are inherently digital hold circuits. They hold the sampled output constant and effect a zero-order hold (ZOH). A S/H variation is the track-and-hold (T/H) circuit. Its output follows the input in the tracking mode. S/H theory also applies to T/H circuits.

S/H circuits are based on an underlying theory that has general application to discrete-waveform (or sampled-data) systems. Its development in the time domain begins with the step (a) and impulse (b) functions, shown below.

1

tΔ

Δ 0

u

1

t

( )t

(a)

1

tΔ

δ

1

t

( )t

(b)

ddt

Δ

The step function is derived by taking the limit of v(t) in (a) as Δ → 0. Then for t < 0, u(t) = 0, but at t = 0+, it is 1. Similarly, the impulse function (in a limit-ing sense) is derived in (b) as the derivative of v(t). As Δ → 0, the width of the rectangular pulse goes to zero, but the amplitude goes to infi nity. The area remains constant in the limiting process and is the value or “amplitude” of the impulse. In the limit,

limΔ

Δ

Δ→⋅ =∫

0 0

11dt


188 Chapter 2

The unit impulse has unit value at t = 0 and is zero elsewhere so that

δ t dt( )⋅ =−∞

+∞∫ 1

Now multiply d(t) by a continuous function, v(t), in the integral. Because d is nonzero only at zero, v(0) effectively weights d(t), and

v t t dt v( )⋅ ( )⋅ = ( )−∞

+∞∫ δ 0

More generally, if d is shifted in time by k ⋅ T, then

v t t kT dt v kT( )⋅ −( )⋅ = ( )−∞

+∞∫ δ

This can also be expressed as an integral with t as upper bound:

v kT d v kT t kTC

t τ δ τ τ( )⋅ −( )⋅ = ( ) >∫ ,

The impulse function is central to sampling theory. A periodic sequence (or “train”) of impulses conveniently characterizes the sampling process. A repeti-tive d(t) with period Ts is the sum of an infi nite number of time-shifted impulses spaced Ts apart, or

δ δP sk

t t kT( ) = −( )=−∞

∞

∑

When v(t) is multiplied by dP(t), a sampled form of v(t), or v*(t), results. (v(t) is real and thus v*(t) does not designate a complex conjugate.) For t ≥ 0,

v t v t t v t t kT v kT t kTP s s skk

*( ) = ( )⋅ ( ) = ( )⋅ −( ) = ( )⋅ −( )=

∞

=

∞

∑∑δ δ δ00

The resulting function is nonzero only where the impulses occur, with values determined by v(t).



The amplitudes of the impulses, though infi nite, graphically represent their area values, which are determined by v(t). This is the behavior of the ideal sampler, a switch that closes only for an instant.

v

t

( )t δ

1

t

( )tP

×

*

t

( )tv

( )tv

*( )tvkT

( )tv

s

*

Two graphic representations of the sampled v(t) are shown below.

*

t

( )tv

( )tv

3 5

(b)

t

( )kTv

( )tv

3 5

(a)

Ts Ts Ts Ts Ts Ts

From v(kT), the discrete v(t) for t = kTs in (a) are the integral of each weighted impulse of (b). v*(t) represents the sampled v(t) as a sum or series, whereas v(kTs), k = 0, 1, . . . represents the sampled v(t) as a sequence and dP(t) can also be interpreted as a series from a sequence of unit impulses.

FREQUENCY-DOMAIN SAMPLING THEORY

In the frequency domain, sampling is impulse modulation; v(t) amplitude-modulates the impulse train. The Laplace transform and Fourier series reveal another perspective on sampling and lead to important design criteria.


190 Chapter 2

To derive the Laplace transform of v*(t), begin with d(t) and apply

v t t dt v( )⋅ ( )⋅ = ( )−∞

+∞∫ δ 0

First,

L δ δt t e dt est( ){ } = ( )⋅ ⋅ = =−∞∫ 00

1

Second, the Laplace transform of dP is

L δPskT

Pk

t e ss( ){ } = = ( )−

=

∞

∑ Δ0

where Ts is the sampling period. One period of a function f1(t), such as a single cycle of a sinusoid, can be made repetitive as the series

f t f t f t T f t T f t kTs s sk

( ) = ( ) + −( ) + −( ) + = −( )=

∞

∑1 1 1 10

2 �

Given L{f1(t)} = F1(s), then

L f t F s F s e F s e F s esT s T skT

k

s s s( ){ } = ( ) + ( )⋅ + ( )⋅ + = ( )⋅− − −

=

∞

∑1 1 12

10

�

Applying the formula,

zz

zk

k=

−<

=

∞

∑ 11

10

,

results in

L f tF s

ee

sTsT

s

s( ){ } =( )

−<−

−1

11,



This is now applied to dP:

L δP P sTsTt s

ee

s

s( ){ } = ( ) =−

<−−Δ 1

11,

Finally, the Laplace transform of v*(t) is

L Lv t V s v kT t kT v kT es sk

sskT

k

s* *( ){ } = ( ) = ( )⋅ −( ){ } = ( )⋅=

∞−

=

∞

∑ ∑δ0 0

This infi nite series of exponentials in s makes V *(s) nonalgebraic and is unwieldy for linear systems analysis. It does, however, resemble the Laplace transform of v(t) for t = kTs. It is simplifi ed by a change of variable,

z e sTs≡

Solving for s,

sT

zs

= ⋅1ln

and substituting for s yields

V s v t v kT zs T z sk

ks

*( ) = ( ){ } = ( )⋅=( )−

=

∞

∑10

ln Z

The operator Z is the Z transform. The Z transform of v(t) is written as V(z), with the understanding that this is not V(s) with z substituted for s. Note that z is a shifting variable; z−k shifts v(kT) by k periods. The Z transform is used in sampled-system analysis the way that the Laplace transform is used with continu-ous functions. The s-domain offers a continuous view of discrete signals and the z-domain a discrete view of continuous signals.

Now v*(t) is expressed using the Fourier series. Repetitive v(t) with frequency ws can be expressed as the sum of sinusoids at integer multiple frequencies (or harmonics) of ws:


192 Chapter 2

v ta

a n t b n t c en sn

n sn

njn t

n

s( ) = + ⋅ + ⋅ = ⋅

↑ ↑=

∞

=

∞

=−∞

∞

∑ ∑ ∑0

1 12cos sinω ω ω

↑↑staticterm

evenharmonics

oddharmonics

where

aT

v t n t dt bT

v t nns

T

Ts n

sT

T

s

s

s

s= ⋅ ( )⋅ ( )⋅ = ⋅ ( )⋅− −∫ ∫2 2

2

2

2

2cos , sinω ωsst dt( )⋅

and for the complex Fourier series,

cT

v t e dtns

jn tT

T s

s

s= ⋅ ( )⋅ ⋅−−∫

12

2 ω

The two representations are equivalent and are related by

c a bba

n n n nn

n

= ⋅ + = { }−12

2 2 1, tanϑ

Even functions of time have no sine terms; odd functions have no cosine terms. Some v(t) can be made odd by subtracting an average offset. The odd function is then transformed and the offset is added as a constant term.

t

( )tv

A

–T Tτ2

– τ20 s

In actual samplers, the sampling waveform is an approximation to an impulse train. It has fi nite amplitude and time duration. The effect this has on sampling can be found by assuming the sampling waveform to be a pulse train with ampli-



tude A and pulse width t. Let wn = n ⋅ ws. As v(t) is centered around t = 0, it is an even function, and

aA

Tt dt

AT

ns

ns

n

n

= ⋅ ⋅ =⋅ ⋅

⋅ ( )−∫

2 2 222

2cos

sinω τ ω τω ττ

τ

where the discrete an have the continuous envelope of the form

sinc xx

x≡ sin

It is shown below for x = wnt/2 = n ⋅ p ⋅ (t/Ts). Instead of an impulse, sinc(x) is the result of fi nite-width sampling pulses.

fτ1– τ

1τ2

τ3

1

sinc

v(f)

f

As t → 0, the pulse train approaches an impulse train. The separation of an(w) decreases in frequency. If instead we let Ts increase, then the effect is the same; harmonic frequency separation decreases. As Ts → ∞, the an merge into a con-tinuous sinc function with a continuous frequency spectrum:

lim lim limT

nT s s T ss s s

nT

nT T→∞ →∞ →∞

=⋅ +( )

−⋅⎛

⎝⎜⎞⎠⎟ = =Δω π π π2 1 2 2

0

As Ts → ∞, the function becomes aperiodic, and the Fourier series becomes the Fourier transform:

F v t V j v t e dtj t( ){ } = ( ) ≡ ( )⋅ ⋅−−∞

+∞∫ω ω


194 Chapter 2

In the limit, the Fourier series of v(t) undergoes these changes:

→ → ( ) → →=−∞

∞

−∞

+∞∑ ∫n

n sc V j n t dt, , ,ω ω ω Δ

Except for the lower limit of integration, the Fourier transform is a special case of the Laplace transform when s = jw. The unit step and impulse functions have no Fourier series, but they have Fourier transforms.

As Ts increases (or t decreases), the sinc response broadens until, in the limit, it is constant over all frequencies. Thus, the frequency response of an impulse is independent of frequency, as in the Laplace transform of d(t).

The frequency spectrum for dP is

cT

t kT e dtT

ns

sk

jn tT

T

s

s

s

s= ⋅ −( )⎛⎝

⎞⎠ ⋅ ⋅ =

=−∞

∞−

− ∑∫1 1

2

2 δ ω

This spectrum is also fl at for all frequencies, with a constant amplitude of 1/Ts. It differs from the spectrum for d(t) in that it is discrete. The Fourier series of the impulse train is

δ δ ω πωP s

k s

jn t

ns

s

t t kTT

eT

s( ) = −( ) = ⋅ ==−∞

∞

=−∞

∞

∑ ∑1 2,

The waveforms of dP in both the time and frequency domains are shown below.

t

( )tP

T

1

δ

s–3 Ts– Ts Ts3

ω

( )ωPΔ⏐⏐ ⏐⏐

ωs2– ωs– 0 ωs ωs2

1Ts



This representation of dP leads to a different expression for L{v*(t)} from that derived previously:

L v t v tT

e e dts

jn t

n

sts*( ){ } = ( )⋅⎛⎝⎜⎞⎠⎟ ⋅ ⋅−∞

∞

=−∞

∞−∫ ∑1 ω

The index n is independent of t allowing the summation to be removed from the integral:

1 1T

v t e e dtT

v t es

jn t st

n s

s jn ts s⋅ ( )⋅ ⋅ ⋅ = ⋅ ( )⋅−∞

∞ −

=−∞

∞

−∞

∞ − −( )∫∑ ∫ω ω

nndt

=−∞

∞

∑ ⋅

The resulting integral is the Laplace transform, V(s − jnws). Thus,

V sT

V s jns

sn

*( ) = ⋅ −( )=−∞

∞

∑1 ω

This expression for V* has a geometric interpretation in the s-domain. The transform of V(s) is periodic in ws so that

V s V s j s* *( ) = −( )ω

V(s) repeats along the jw-axis at intervals of jws.Previously, dP(t) was expressed as a series of complex sinusoids with amplitude

1/Ts and frequencies of n ⋅ ws. The frequency spectrum of v(t) is convolved (or heterodyned) in the frequency domain with the spectrum of dP(t), as shown below.


196 Chapter 2

Multiplication in one domain corresponds to convolution in the other. The sine and cosine terms in v(t) multiply by the terms of dP to produce sum and difference frequencies according to the trigonometric formulas

cos cos cos cosα β α β α β⋅ = −( ) + +( )12

12

cos sin sin sinα β α β α β⋅ = +( ) − −( )12

12

The frequency-domain plots are the magnitude envelopes of the complex Fourier coeffi cients, the amplitudes of the harmonics. For V *( jw), the spectrum of v(t) is centered around harmonics of ws. Thus, the effect of sampling is to generate frequency-shifted copies (or bands) of V(jw) centered around harmon-ics of ws.

t

( )tv

tTs

Time domain( )vnc⏐⏐ ⏐⏐

ω

Frequency domain

Envelope ofFourier coefficients

= ( )ωV

ω

( )ωPΔ

ωs2– ωs– 0 ωs ωs2

( )tPδ

t

( )tPδ( )t* ( )tvv = ⋅

ωωs2– ωs– 0 ωs ωs2

( )tPΔ( )ω* ( )ωVV = *



THE SAMPLING THEOREM (NYQUIST CRITERION)

The sampling theorem gives a criterion for recovery of v(t) from v*(t). If ws is greater than twice the highest frequency in V( jw), then the frequency-shifted bands of V( jw) do not overlap and can be separated by fi ltering.

ωωs2– ωs– ωs ωs2

( )ω*V

ωa

ω1ωs2

( )ω–1V ( )ωV ( )ω1V ( )ω2V

ωa =Alias frequency = ω1 – ω s

–

The Nyquist criterion for recoverability of the original continuous signal is

ω ωs h> ⋅2

where wh is the highest frequency component of V(jw). The original signal is recoverable from its sampled form when the highest frequency component is less than the Nyquist frequency, ws/2. In the plot above, the band V1(jw) is a replica of V(jw) centered at ws. It has frequency components below ws that overlap with the positive frequency components of V(jw). These are negative frequencies in V(w) shifted up in frequency by ws.

The signifi cance of negative frequency components in V(jw) is that they are inverted (180° phase-shifted) from their corresponding positive counterparts. The magnitude of V(jw) is symmetric around w = 0; it is an even function and V(−jw) = V(jw). The phase, however, is an odd function and is negative for w < 0; for negative n, the angle of cn is J = −n ⋅ ws ⋅ t. Then J(−n) = −J(n).

In the plot, V(jw) and V1(jw) are symmetrical around the Nyquist frequency. In effect, V has been folded over at ws/2. The larger wh is, the further back toward lower frequencies the folding extends. These folded frequency


198 Chapter 2

components from V1 are alias frequencies in v*(t) and have a frequency of wa relative to ws.

t

ω– a

The signifi cance of an alias frequency in the time domain is that a sequence of samples has more than one frequency interpretation. In the fi gure above, V(jw) has one frequency component at w = (3/4) ⋅ ws. The samples also fi t a sinusoid of w = −(1/4) ⋅ ws, an alias frequency within the band of V(jw). The alias sinusoid is inverted relative to that of V1 because its frequency is negative.

More generally, if w1 of V(jw) is sampled at ws, then from the fi rst plot,

ω ω ω ω ω1 = − −( ) = +s a s a

and

alias frequency = = −ω ω ωa s1

In the plot above, sinusoids of both w1 of V and wa of V1 fi t the sample points. The discrete samples of v(t) are too few per cycle to eliminate wa and v(t) is undersampled. The sampling theorem requires more than two samples per cycle for recovery of v(t). Such a v(t) is oversampled.

Recovery of V(jw) from V*(jw) for oversampled signals is achieved by a low-pass fi lter (LPF) that passes only V(jw). The ideal fi lter magnitude, ⎪⎪H(jw)⎪⎪, is shown below.



It has an immediate cutoff just above wh. The ideal maximum-bandwidth fi lter has a cutoff at the Nyquist frequency.

t

( )th

t

v(k )

*sinc

t

( )tvTs

In the time domain, this fi lter function transforms into a sinc function. Nonzero sinc values extend to t = −∞, resulting in a noncausal function that can only be approximated by physical (thus causal) circuits. The pulse shape of the ideal LPF transforms into a sinc function in t just as a pulse in the time domain does in w. H( jw) is multiplied by V *( jw) in w to recover V( jw). In t, h(t) is convolved with v(kTs) to produce v(t). For bandlimited v(t),

v t v kT t kTss

ss

k

s( ) = ( )⋅ ⋅ −( )⎛⎝

⎞⎠ − < <

=−∞

∞

∑ sincω ω ω ω2 2 2

,

The sinc function operates as an interpolator, fi lling in the missing values of v(t).

t

( )tv

( )tv

sT

^

ωωs2

( )ωH

ωs


200 Chapter 2

The fi nal derivation of general usefulness is the spectrum of a zero-order hold. This is the frequency response of a S/H circuit. In the time domain, this is a voltage step turned off Ts later:

ZOH:v t u t v t T u t Ts s( )⋅ ( ) − −( )⋅ −( )

In the s-domain, a ZOH can be regarded as an integrator of weighted impulses, producing v(t), as shown above. This is the typical output waveform from a S/H or DAC.

The integrated waveform is periodic at the sampling rate. An integrator in s is 1/s. When it is normalized to be unitless, then it is 1/s ⋅ Ts. A periodic integra-tor is constructed by integrating for Ts. The Laplace transform of this expression is H0(s). The normalized ZOH transfer function is thus

ZOH: H ss T s T

ee

s Ts s

sTsT

s

ss

01 1 1( ) =⋅

−⋅

⋅ = −⋅

−−

The frequency response of H0(s) is found by letting s = jw. Then

H je

j TT

ej T

s

s j Ts

s0

212

ωω

ωωω( ) = −

⋅=

⋅⎛⎝

⎞⎠ ⋅

− ⋅− ⋅sinc

The magnitude and phase are

H jT

H jTs S

0 02 2

ω ω ω ω( ) =⋅⎛

⎝⎞⎠ ∠ ( ) =

− ⋅sinc ,

Once again, the sinc function appears. The magnitude plot of the frequency response is shown below.

ω

(jω)H0

ωs2

ωs ωs2

3

1

0.636

0.212



The phase response is linear and only time-shifts the output. The phase delay can be seen in the time plot by noting that a best-fi t of v(t) to v(t) requires v(t) to be shifted to the right (delayed in time) by half a step, or by −Ts/2, in agree-ment with ∠H0(jw). Ideal recovery of v(t) from v(t) requires an inverse sinc fi lter, or sinc compensator. This compensator can be implemented in either digital or analog form. It is digital if it precedes a DAC or follows an ADC and analog if it follows a DAC or precedes an ADC.

SAMPLING CIRCUITS

Sample-and-hold or track-and-hold circuits are switched between the sample or track state and hold state by a digital control line. Ideally, the input voltage at the instant of switching to HOLD is retained as a constant at the output of the S/H. T/Hs are similar to S/Hs; in the non-held state, the output follows the input. In a S/H this is not necessarily so, though most S/Hs are actually T/Hs. The sampling impulse of sampling theory corresponds to the active edge of the HOLD signal.

The speed of a S/H is determined by the acquisition time, the time from when sampling or tracking of the input begins to when a settled, held output is avail-able. This time has two terms. The fi rst is the time from when tracking begins to the time when the hold capacitor follows the input waveform. A large initial difference between vI and vC requires slewing time before tracking is accurate. The second term is the setting time at vC when the hold state begins. In addition to acquisition time, aperture delay and jitter also apply to S/H circuits.

Several errors are associated with S/H circuits, and their design consider-ations are closely related to those of peak detectors. Errors occur in the sampling process or in the hold state. The fi rst are dynamic sampling errors. Digital delay causes the effective sampling instant to be delayed. For a rising input, this trans-lates into a voltage error of

vdvdt

tIdε = ⎛

⎝⎞⎠ ⋅

where the digital delay time td is multiplied by the waveform slew-rate. The second cause of error is analog advance. If the input is delayed instead, an


202 Chapter 2

effective negative delay occurs in sampling since the waveform lags behind where it should be when sampling occurs. A rising input waveform is below where it should be and a negative error occurs. It is equivalent to sampling the waveform in advance of the actual sampling instant.

R

C

vO

+

–

vIK 1 ×

The dominant cause is a voltage lag on the hold capacitor. Its charging always lags somewhat behind the source. This is largely due to charging-source resis-tance R in the S/H circuit shown above. By closing the loop with an op-amp input, we reduce the charging time constant RC by K + 1. The diodes around the op-amp keep its output from saturating when in the hold state. Waveform advance is the major cause of delay error and is compensated by delaying the sampling command.

C

vO1×

Cs

1×vI

vC

A third dynamic error is due to stray capacitance Cs between the hold capaci-tor C and the sampling command line. When this line switches, it causes charge to fl ow through Cs into C. If the capacitor voltage vC is plotted against a range of constant-voltage inputs, the plot is linear. Its slope represents a hold gain. As



the input voltage vI increases, the step of extra voltage on C grows in size because the voltage between the hold line vH and vC varies linearly with vI. As the differ-ence between the sample level, Vs, of vH, and vC increases, Cs is charged more, and this charge is transferred to C when vC changes to the hold state. The hold step, or pedestal, thus increases with vI.

vO+

1×vI vC

C

–

Cs

A circuit that avoids this problem is shown above. The hold capacitor is the feedback C of the op-amp. The op-amp isolates vC from the switch node by holding it at virtual ground. Then the voltage across Cs is independent of vI and the same amount of charge is transferred to C on switching. The charge on Cs is Cs ⋅ Vs. The hold gain varies somewhat as Cs varies with voltage as do semiconductor junctions.

The hold capacitor dielectric absorption must be low to avoid recovery effects during the hold state. Its leakage causes static sampling error during the hold state. Any other leakage paths for capacitor charge contribute to leakage error. The buffer amplifi er and sample switch must be low in leakage. A leakage compensator is shown below.

vO+

1×vI

C

–

R


204 Chapter 2

The leakage decoupler R has the same function as in peak detectors. It keeps the voltage across the switch near zero, thus minimizing leakage through it.

vI

C Cs s C

vCQ1 Q2

Another hold-step compensator places another switch similar to Q1 in series with it. This additional switch is shorted, but its Cs (CGS for a MOSFET) connects to the same node. It is driven with an opposite polarity edge so that its stray charge cancels that of Q1.

1 +

–C

vI ×

C 2

Q1

1

Q2

RGS

D1

D2

RGS

vO

AB

In this S/H, a JFET switch Q1 passes the waveform through its channel, con-nected to the buffer A. When the control line goes low, Q1 cuts off. D1 conducts a small amount of current through RGS to keep the gate reverse-biased. At the same time, Q2 is also cut off by a similar circuit. The capacitor C2, equal to C1, is a bias-current compensator for the op-amp (as with a previous peak detector). As the hold capacitor C1 charges with IB, so does C2. The differential voltage is canceled at the output. Of course, offset current is not compensated.



Finally, very fast S/Hs have the additional error of signal leakage through shunt switch capacitance Cs during hold. This circuit uses a diode sampling bridge. The bridge has two Css in series for each leg of the bridge, or an equivalent of one Cs from input to output. It is current-switched for speed. To reduce addi-tional input-to-output bridge capacitance, the diodes are fed through a metal sheet which functions as a Faraday shield. Sampling bridges of this kind have commonly been used in sampling oscilloscope front ends. The practical limita-tion in their switching time is often the switching speed of their drivers.

SWITCHED-CAPACITOR CIRCUITS

Switched-capacitor circuits replace resistors with capacitors and switches. In ICs, diffusion resistors, made by connecting to the ends of a diffused area, are not optimal since their values are hard to control and they have large areas (their relative values are much better; they match well). Large-value resistors take up so much area that they are often impractical. When accuracy is not important, a kind of resistor made of a thin layer of, say, n material between two p layers – a pinch resistor – can be made large but with a ±20% accuracy. NiCr (nichrome) resistors are very good but costlier to make and trim.

i v

R+

–C

S

vi

C

1v

S i 2S

1vI ×

C

1×

I

I

vCC s

vO


206 Chapter 2

vO+

C

–

f

Ci

S1

S2

vI

This limitation makes switched-capacitor resistors an attractive alternative. The equivalent resistance is shown above. It is a single-pole, double-throw (SPDT) switch S and a capacitor. The SPDT switch is equivalent to two single-pole, single-throw (SPST) switches, synchronized as shown. When S is switched to the input, it charges to the input voltage v with a charge of C ⋅ v. When it switches to an output held at ground, it delivers this charge. The output is typically the virtual ground of an op-amp.

If the switching rate is fs, then the charge delivered per unit time, or current, is

i C f v rC f

TC

ss

s= ⋅ ⋅ ⇒ =⋅

=1

The equivalent resistance follows directly and is subject to the Nyquist crite-rion due to switching. The bandwidths of switched-capacitor circuits must be well within the Nyquist frequency for accurate equivalence.

vO+

C

–

f

v

Ci

I



vO+

C

–

f

Ci

S1 S2

vI

+

–

This switching scheme inverts vI. Ci charges with switches in the position shown. When switched, charge fl ows out of the op-amp input to ground. In effect, the two-switch circuit is a negative R.

With drive to the grounded side of S1 from the input instead, the two terminal voltages of vI subtract upon switching. The differential voltage vI determines the charges.

CLOSURE

The world of digital electronics merges with analog electronics in digitizing and sampling circuits, but the merged areas – mainly ADCs, DACs, and switched-capacitor and sampling circuits – do not involve logic design. Instead, the underlying theory is an extension of that for continuous functions. The mathe-matics is similar; difference equations replace differential equations. Sampled circuits also include commutating and switched-capacitor fi lters and digital signal processing, but the full story, including dithering, FFTs, DSP fi lters, and windowing, is left for other books.



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Index

555 timer, 71, 79absolute-value function, 121acquisition time, 132, 133, 201AD534, 104, 127ADC conversion rate, 154, 180aliasing, 176all-pass, 54, 116all-pass fi lter, 54, 116antilog-amp, 94aperture delay, 186, 201aperture jitter, 186armed, 82auto trigger, 85, 86

Baker clamp, 62, 63bandgap circuit, differential, 11bandgap energy, 5bandgap reference, 7, 9, 17bandgap-reference equation, 12band-pass fi lters, 41bandpass response, 43band-pass transfer function, 41bandwidth reduction factor, 45Barrie Gilbert, 133baseline restorer, 61biquad fi lter, 52, 53biquadratic form, 52BJT DACs, 144Bob Widlar, 9bootstrap ramp generator, 86Brad Howland, 29Bruce Hofer, 90

capacitance multiplier, 77, 78cermet, 15characteristic equation, 51charge-balancing ADC, 167, 168, 170, 177,

179, 181clamps, 60, 62, 65, 122, 125clipping circuit, 61clock generator, 67, 70, 71, 166CMOS DACs, 143, 152collector resistance, 70, 93complementary CC buffer, 23complex conjugate, 188complex-frequency domain, 40composite, 40composite amplifi ers, 40conductivity, 62coupling coeffi cient, 46crowding, 62current divider formula, 36current mirror, 17, 38, 39, 105, 129, 152current squarer, 99, 100current-source ramp generator, 90, 155current-switching R-2R network, 142, 144

Darlington, 17, 38, 66deadband, 54deadzone, 54, 56deglitcher, 140dielectric absorption, 130, 203differential linearity error, 140, 141, 147distributed amplifi er, 185dominant pole, 131

FPCIndex.indd 213FPCIndex.indd 213 7/29/2009 10:36:35 AM7/29/2009 10:36:35 AM

214 Index

double triggering, 83, 84dual-slope ADC, 161, 163, 166, 177duty-ratio, 67, 74, 85, 106, 118, 147, 148,

179

ECL, 82, 108envelope, 193event, 80, 81, 86, 136exp-amp, 94, 96

feedforward, 184foldback current limit, 66Fourier transform, 193frequency spectrum, 194, 195, 197full-wave rectifi er, 121function generation, 90, 98function generator, 106

Gilbert gain cell, 120Gray code, 185

high-level injection, 61hold step, 203Howland current source, 29, 36, 152hysteresis window, 56, 57, 85hysteretic comparator, 54, 55, 57, 58, 70

impulse function, 187, 188, 194impulse modulation, 189impulse train, 189, 192, 193incremental gain, 33instrumentation amplifi er, 128interpolator, 199

jitter, 76, 81, 83, 180, 182, 186, 201

Kirk effect, 62

Laplace transform, 189–191, 194, 195, 200

leakage decoupling, 132leakage path, 203least-integer function, 138

limiters, 60, 140LM331 VFC, 178LM334, 24logarithmic amplifi ers, 90logarithmic sweep, 117logic functions, 58log-ratio amplifi er, 91, 95log-rms, 105

maximum magnitude, 43medical laser, 101MFED response, 48mica, 130Miller effect, 78Miller ramp generator, 86, 88, 106MMVs, 66modifi ed dual-slope ADC, 164, 166, 167,

177monotonicity, 147multiple-feedback fi lter, 47, 49multipliers, 148Murphy clamp, 64

narrowband approximations, 42NE565 FG, 109NE566 PLL, 109nonlinear, 1, 115, 117nonminimum-phase, 116normal-mode rejection, 168n-stage fl ash ADC, 184, 185Nyquist criterion, 197, 206Nyquist frequency, 197, 199, 206

offset binary, 137, 186offset error, 106, 153one-shots, 66oscillation, 67oscilloscopes, 81, 82oversampled, 198overshoot, 131

Padé approximation, 116parallel or fl ash converters, 182


Index 215

parallel-feedback converters, 156, 157, 177Paul Brokaw, 11peak detectors, 86, 129, 158, 201, 204peaking, 41, 58peak-to-peak auto, 86PGA, 153, 184phase shifter, 54phase-lead compensator, 116phase-locked loop, 106piecewise-linear waveform, 118positive-feedback amplifi er, 58power-line, 170PSR, 18, 19, 21pulse-width modulation, 118, 136, 147

quantization noise, 139quasistable state, 66

R-2R network, 142–145, 147ramp converter, 154, 155, 157RC differentiator, 67recirculating-remainder ADC, 185recursive subranging ADC, 184resistance multiplier, 80retriggerable, 75, 85rms circuit, 104, 127rss circuit, 103, 104

Sallen-Key, 47Sallen-Key fi lter, 47sample-and-hold, 130, 136, 160, 168, 183,

185, 187, 200–202, 204sampled signals, 136sampled-data systems, 136sampler, ideal, 189sampling bridge, 205sampling oscilloscope, 205sampling pulses, fi nite-width, 193sampling theorem, 197, 198saturation current, 5, 132scaled-emitter technique, 145Schmitt trigger, 54–55, 66, 106, 108, 113Schottky clamp, 63

segmented DAC, 146, 147selectivity, 43, 45sensitivity, 90serial-input DAC, 148settling time, 140, 157shields, 108, 205shunt-feedback amplifi er, 21sigma-delta ADC, 167sign-magnitude, 137sinc(x), 193single-ended, 123, 152slew rate, 84SNR, 139source resistance, 15, 142, 202square-root circuit, 101state-variable fi lter, 50, 52step function, 187subranging fl ash converter, 183substrate, 2successive-approximation, 160switched-capacitor circuits, 205symmetric, 106, 108, 111, 112, 116, 128,

137, 150, 151, 197sync, 80sync tips, 61synchronous rectifi er, 122synchronous tuning, 45

tapped inductance, 46time advance, 116timer, 71, 72, 74, 76, 78, 170, 181timer-based MMV, 74track-and-hold, 158, 187, 201tracking converter, 156, 157translinear cell, 99, 103, 120triangle-wave generator, 106, 108–110, 112,

115, 116, 118trigger generator, 80–82, 84, 85trigger pulse, 74, 75TWG-loop compensation, 116two-BJT astable MV, 67, 70

undersampled, 198


216 Index

VBE multiplier, 21, 23VCF, VCG, 106VCOs, 106vector magnitude, 98virtual ground, 35, 125, 129, 143, 167, 203,

206voltage translator, 58voltage-controlled symmetry, 118voltage-switching R-2R network,

142

voltage-to-current converter, 38, 109, 112, 115, 163, 166

Widler, Bob, 9

XR2206 FG, 111

Z transform, 191Zener diodes, 1–3zero-order hold, 187, 200


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