Analog AND DIGITAL CIRCUIT DESIGN

8/13/2019 Analog AND DIGITAL CIRCUIT DESIGN

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MODULE IANALOG MOS CIRCUIT DESIGN

Dept. of AE&I, GEC Kozhikode


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Analog vs. DigitalAdvances in digital computing and IC technologies diven !ocus o!

design into digital domain

Digital domain" ease o! handling# elia$ilit% and implementation

possi$ilities pomoted eplacement o! taditional analog !unctions

Digital !unctions can&t still eplace analog countepat li'e pocessingo! natual signals# tansmission# sensos# (ieless communication etc)

Digital cicuits tade*o!! $+( speed and po(e ) Analog cicuit design

depends on multi*dimensional !actos speed# po(e# voltage#

!e,uenc%# gain# pecision etc)

Analog designes ae in demand - ,uic' undestanding o! cicuit# good

mathematical s'ills# ceative !o cicuit topologies i)e) good anal%tical

and design s'ills e,uied



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CMOS vs. Bipolar

CMOS technolog% is dominant ove $ipola technolog%due" lo( po(e dissipation# $ette integation densit% and

less !a$ication cost

Intinsic speed o! MOS devices has $een impoved ove

past decades and pime candidate !o analog designscompaed to $ipola devices

CMOS has $een the choice to meet the scaling as pe

Mooe&s la( o! integation i)e) num$e o! tansistos

integated dou$les eve% .)/ %eas 0/1m in .234

4).51m in 0444)



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MOSFET structure

n*t%pe MOS device stuctue !a$icated on p*su$state

Dain and souce" heav% di!!usion egions

Gate" =ol%silicon o metal (ith SiO0 isolation

Channel Length Le!! > Lda(n - 0Ld 6side di!!usion7

O?ide thic'ness To? and Le!! ae impotant design paametes



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MOS sy!"ols

;ou Teminal Analog model

Digital modelDept. of AE&I, GEC Kozhikode


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MOS #$% CharacteristicsGeneation and tanspot o! chage caies as a !unction o! MOS;ET

intenal voltages at device level



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Threshold %oltage (%thMinimum gate*to*souce voltage to tun on the MOS

device !o conduction

Co? > @o?+to?



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Derivation o& #$% characteristicsDain cuent Id as !unction o! MOS teminal voltages 9gs# 9ds

Cuent !lo( though uni!om coss section o! semiconducto

Uni!om chage densit% pe unit channel length o! MOS;ET 6condition

9g9th and 9ds>Beo7

8hen 9ds4 channel chage densit% vaies as !unction o! length 4:?:L

Integating ove ange



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Setting the $ounda% conditions and evaluate and Id is constant along

the channel

L is the e!!ective channel length) Cuent as a paa$olic !unction o!

voltage and pea' value at called as ove*dive voltage

and 8+L is called as aspect atio



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MOSFET operation !odesLinea esisto model" Deep tiode egion appo?imation



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Saturation !ode8hen MOS;ET opeates in satuation

egion) Cuent cuve doesn&t !ollo( paa$olic !unction

i)e) cuent elativel% constant



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Channel pinch'o&&As d is popotional to 9gs*96?7*9th hence 9ds>9gs*9th i)e)

d>Beo 8hen 9ds is slightl% geate than 9gs*9th invesion la%estops at ?L temed as channel pinch*o!!



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;o =MOS;ET" Dain cuent e,uation (hen device opeating in

linea and satuation egions

Tansconductance paamete" ho( (ell device convets voltage into

cuent i)e) !igue meit) gm in satuation egion is ecipocal o! Ron

in tiode egion


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Channel length !odulationChannel length is educed as 9ds inceases i)e) L&>L*L

$% linea app?) L+L H 9ds) Device cuent in satuation

Tansconductance o! device $ecome



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Su" threshold conduction

Ideal $ehavio" (hen 9gs : 9th device tuns o!!Su$*theshold cuent !lo(s even (hen 9gs:9th (ith

e?ponential dependence on 9gs simila to diode e,n)

8hee



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MOS device capacitance

Device capacitance must $e consideed !o JacK modelingo! Analog MOS cicuits

Eve% t(o teminals o! MOS device has capacitance

depends on $ias conditions



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Device capacitances divided into

C." O?ide capacitance $+( gate and channel 8LCo?

C0" Depletion capacitance $+( channel and su$state

C#C" Ovelap capacitance $+( S*D and gate i)e) Cov

C/#C3" unction capacitance $+( S*D and su$state can $e

decomposed into C 6$ottom*plate7 and Cs( 6side*(all7

components



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MOS s!all signal !odelLage signal model" ,uadatic $ehavio o! cuent (ith device voltage (ith

capacitance model i)e) help!ul in anal%Bing cicuits (ith non*linea$ehavio

Small signal model" Appo?imation o! lage signal model to simpli!% the

anal%sis i)e) linea $ehavio )

MOS device opeating in satuation egion in most analog cicuits)

Modeling components"

Cuent souce gmVgs" device cuent dependenc% on 9gs

Linea esisto r0" Channel length modulation paamete i)e) device cuent

dependenc% on 9ds

Cuent souce gmbVbs" od% e!!ect paamete i)e device cuent dependenc%

on $ul' potential

Device capacitances



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MOS AMPLIFIERS



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Single'stage A!pli&iersImpotant analog !unction to stengthen signals !o

diving the loads

Appo?imate and simple cicuit models 6small signal# lo(

!e,uenc%7 used !o ampli!ie cicuit anal%sisAmpli!ie design is a multi dimensional optimiBation

po$lem li'e speed# suppl% voltage# po(e# lineait%# gain#

input*output impedance# voltage s(ing etc)

Input*output chaacteistics o! ampli!ie is non*linea

!unction epesented as pol%nomial ove ange



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Co!!on Source (CS A!pli&ierGate teminal 69gs7 sensitive to input changes and convets in to

dain cuent in load esisto i)e tansconductance $ehavio o!

MOS;ET

8hen 9in aises esults in dain cuent !lo( in load esisto Rd

causes 9out dop

8hen 4:9in:9outP9th 69in.7 opeates in satuation

Small signal gain o! the CS ampli!ie



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Lage signal model !o CS stage i)e) conside channel

length modulation 6non*linea model7Qence simpl% $% inspection o! lage signal CS stage

cicuit model (e get"



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Source Folloer (Co!!on Drain

Used as a voltage $u!!e placed in $et(een CS ampli!ie (ithlage gain 6Rd7 diving a lo( impedance load i)e) to avoid

loading e!!ect



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Opeation" 8hen 9in : 9th * 9out>4) 8hen 9in 9th#

Output !ollo(s input voltage change shi!ted $% 9gs and

assume device opeating in satuation) Input*output

chaacteistics epesented $%

Di!!eentiating $oth sides $% 9in to o$tain Av

As



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Also note that"

Qence 9oltage gain e?pession $ecomes"

Small signal e,uivalent cicuit (ith gain chaacteistic



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Co!!on )ate (C) A!pli&ier

Unli'e CS and CD stages# cicuit senses input at souceand poduce output at dain teminal) Gate connected to

DC $ias !o pope opeation) T(o con!iguations

possi$le" diect coupling 6dc7 and capacitive coupling 6ac7



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Opeation" As 9in deceases !om lage positive value !o

9in9$*9th M. is o!! hence 9out>9dd) Once 9in:9$*9th

device tuns on in satuation

Small signal gain"

E,uivalent cicuit"



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Cascode A!pli&ier

Cascode 6Jcascaded tiodesK7 com$ination o! CS and CGstages !o inceased intinsic gain and output impedance

values in compaison (ith othe con!iguation



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Output voltage s(ing limited to sum o! ove dive voltages

o! M. and M0 i)e) 9dd * 69gs.*9th.7P69gs0*9th07

compaed to CS stage 69dd * 9gs*9th7

Opeation" 8hen 9in:9th. device M.#M0 cuto!! no cuent

9out>9dd As 9in9th. M. stats conducting and 9out dops)



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Using small signal model $elo( assuming Beo channel length

modulation voltage gain o! cascode stage is that o! CS stage as cuent is

independent o! M0 paametes 6gm and $od% e!!ects7

Consideing lage signal model (ith const cuent souce Av>gm.Rout

(hee Rout is the e!!ective output esistance 6gm$0Pgm07o0o. i)e)

intinsic gain inceased $% M0 tem



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Frequency Response



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Co!!on Source (CS stage

Qigh !e,uenc% model o! CS ampli!ie" Gain is a !unctiono! !e,uenc% G6s7 * G6(7

Conside !inite impedance due to device and node

capacitance and esistance * identi!% poles in tans!e!unction G6s7

High frequency model and equivalent ckt of CS stage


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Neglect channel length modulation and device opeating

in satuation) Total capacitance at input node is"

Input pole !e,uenc% at is"

Total capacitance at output"

Output pole !e,uenc% is"

Qence tans!e !unction is"



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Source &olloer (CD stageUsed e?tensivel% as level shi!tes and $u!!es impotant to

'no( the impact on !e,uenc% esponse

Not possi$le to associate poles (ith nodes and due to

stong inteaction though Cgs) Intuitive method cant $eapplied hee li'e CS stage) CL is the total output load

capacitance including Cs$



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% CL at output node in e,uivalent c't"

% 9L# summing all voltages !om 9in"

Su$stitute value o! 9. in 9in e,uation"



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Consideing patial !action o! second ode denominato

(ith distinct poles (p. :: (p0

Signi!icant pole !e,uenc% is given $%



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Co!!on )ate (C) stageTo simpli!% the anal%sis channel length modulation is

neglected)

=e!ect isolation $et(een input and output nodes i)e) no

mille coe!!icient to multiplied in tans!e !unction esults

in (ide $and esponse



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Cascode stageChaacteiBed $% high input impedance o! CS stage and high

speed and $and(idth chaacteistic o! CG stage% intuitive appoach# simpli!ied tans!e !unction can $e

deived $% associating node $ased poles $elo("



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Differential Amplifier



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Di&&erential A!pli&iers

Choice o! ampli!ie in high pe!omance analog and mi?ed signaldesign due to $ette noise immunit%

Di!!eential vs) single ended opeation

Di!!eential opeation can inheentl% eliminate suppl% voltage#

coss tal' noise vaiations intoduced in ampli!ie stages



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asic di!!eential ampli!ie composed o! t(o identical CS

stages opeate on t(o phases o! signal aound a common

mode level 6dc o!!set at input to ensue devices do not tuno!! and al(a%s in satuation7



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To ma'e device least dependent on input common mode

level connect souce teminals though a cuent souce !o

ma?imum voltage s(ing

Qence (hen 9in.>9in0 output common mode level



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Input*output chaacteistic o! di!!eential ampli!ie

Ma?imum and minimum output voltage levels"

As input voltage s(ing inceases $oth sides gain 6slope o!

cuve7 deceases and ma?imum at 9in.>9in0

Small signal gain o! di!!eential ampli!ie" gmRd



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Di&&erential A!pli&ier $ MOS load

Linea esisto load can $e $ette eplaced $% MOSdevices !o optimum aea and po(e dissipation



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Current Mirror



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Cuent mio is also called as Jcuent cop%ing cicuitK

i)e) povide a sta$le cuent against pocess# suppl% and

tempeatue vaiationsE?tensivel% used as $iasing and signal pocessing

applications



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Cascode current !irrorModi!ied cuent mio to compensate the cuent vaiations

due to channel length modulation dependencies) Ratio o!cuents $ecome"

8hee 9ds.69?7>9gs. 6diode connected7>9gs0 i)e) does not

impl% 9ds069%7>9gs0 $ecause 9ds0 depends on $ias cicuit o!

M0 69p7



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Modi!% the $asic cuent mio cicuit to povide a

cascode $ias voltage !o M 69$7 to ma'e 9ds069%7

independent on 9p esults in a cascode cuent miocicuit $elo("

Select device dimensions to satis!% the condition

Analog AND DIGITAL CIRCUIT DESIGN

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