s. ~M:/~a3J/C~! JECCOE~S I 5 AMI/HDB3/CMI DECODERS 1= 5.1 OBJECTIVES • Describe and examine the functional aspects of the decoders A.'iI /UDB3 / C!iI . • carry out the error rate measurement on the connections consisting of: coders ~~I/HDB3/C!iI; transmitter; line+noise; line receiver; decoders .-\"'iI/HDB3 /C!iI. 5.2 DESCRIPTION 5.2.1 ~'iI/HDB3 Decoder The circuit receives the binary unipolar signals "+" and "-" and the negated RCK clock ·(with frequency equal to the data speed), supplied by the Data Recovery and Clock Recovery circuits (fig.S.l). A decoder operates on a 4-bit string, which are read in correspondence of the rising edge of the clock. The NRZ decoded binary data are supplied across the output in correspondence to the rising edge of the clock and a delay of 4 clock periods (see example of fig.5.2). The decoder carries out also a control on the binary signals .~'iI/HDB3 "+" and "_" , and in presence of violation of the code it supplies an error signal (high level for the duration of a clock period) across the Error detector output. The error is signalled in the following cases: • HDB3 mode: when two consecutive violations are detected having the same polarity • AMI mode: when a violation is detected • AMI/HDB3 mode: when the binary signals AMI/HDB3 "+" and "_" applied to . the input of the decoder are simultaneously at high level. C.LOCK RECOVERY 2' 'N' m oc. AWI/HD83 DECODER LINE 2< 'e •• our IN- EOUAlIZER 21 & ALBO Ifl IN A•• [CJ "DU 33 3C 22 IICi <J I\, OUT. ["01 D[I[CrDR 30 OUl· l! DATA RECOVERY fig.5.1 - 36 -
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s. ~M:/~a3J/C~! JECCOE~S
I
5
AMI/HDB3/CMI DECODERS1=
5. 1 OBJECTIVES• Describe and examine the functional aspects of the decoders
A.'iI /UDB3 / C!iI .• carry out the error rate measurement on the connections consisting of:
coders ~~I/HDB3/C!iI; transmitter; line+noise; line receiver; decoders.-\"'iI/HDB3 /C!iI.
5.2 DESCRIPTION5.2.1 ~'iI/HDB3 Decoder
The circuit receives the binary unipolar signals "+" and "-" and thenegated RCK clock ·(with frequency equal to the data speed), supplied bythe Data Recovery and Clock Recovery circuits (fig.S.l).
A decoder operates on a 4-bit string, which are read in correspondenceof the rising edge of the clock. The NRZ decoded binary data aresupplied across the output in correspondence to the rising edge of theclock and a delay of 4 clock periods (see example of fig.5.2). Thedecoder carries out also a control on the binary signals .~'iI/HDB3 "+"and "_" , and in presence of violation of the code it supplies an errorsignal (high level for the duration of a clock period) across the Errordetector output. The error is signalled in the following cases:• HDB3 mode: when two consecutive violations are detected having the
same polarity• AMI mode: when a violation is detected• AMI/HDB3 mode: when the binary signals AMI/HDB3 "+" and "_" applied to .
the input of the decoder are simultaneously at high level.
C.LOCKRECOVERY
2''N' moc. AWI/HD83 DECODER LINE2<
'e •• our IN- EOUAlIZER21 & ALBO Ifl IN
A•• [CJ "DU33 3C
22 IICi <J I\,OUT.["01D[I[CrDR 30
OUl·l! DATARECOVERY
fig.5.1
- 36 -
s. AMI/~OB3/C~I ~£COOERS
~ECEIVED SIGNAL HOBJ
3~Ot<EN U?51eNAL •.•.• e '-'
CLOCK
RECEIVED DATA
-- -....1 11DELAY I I~ ~r!~ ~
fig.5.2
5.2.2 CMI DecoderThe circuit receives the CMI amplified signal and the RCK clock (withfrequency double the data speed), supplied by the Data Recovery andClock Recovery circuits (fig.5.3). Across the output of the decoder, youobtain the data signal with the related clock.
CMI~CK CLOCKPCM OUT 28CIoII RECOVERY
DC. DECODER RCK C1l CMI LINEEOUALlZER
At ALBO RI IN3) ,.
<J T\'ell DATA12 RECOVERY
fig.5.3
- 37 -
...
5.3 EXERCISESRequired material• modules T20E/T20F• power supply +/-12 Vdc• osci lloscope.5.3.1 Exercise 1: Decoding of AMI/HDB3 signals1. At the beginning set up the system in fu~Imode (fig.5.4):
flat cable between T20E and T20FTP5 of T20E with TP16 of T20FTP27 of T20F with TP10 of T20Eground of TX OUT with ground of LINE INTP11 of T20E with TP34 of T20Fground of LINE OUT with ground of TX INTP 23 of T20F with TP8 of T20ETP 24 of T20F with TP9 of T20E
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2. examine the data signal across the input of the coder (TP16) andacross the output of the decoder (TP24). The same data should beobtained (i.e. the same wave-form) delayed of about 9 clock periods
3. examine the data signal and the corresponding clock signal together(TP 23 and TP 24)
4. set up the system in HDB3 mode and carry out the last measurements.again.
5.3.2 Exercise 2: Measurement of the error rate
PC.r--c0cU"~~ =-~~ I~ ~ I
I,---,.",..---, I
ICltllrulr\aI~'1 :
-- IIIII
..If( Kf'tJi"C( o o
TH"
no!
5. Select the Sequence data signal (pseudocasualsequence of 64 bit)on T20E. and press the RESET pushbutton
6. the value read on the "BIT COUNTER" display, multiplied by 103,corresponds to the number of received bit. The "ERROR COUNTER"display shows the number of the bit received wrong
7. if the noise is not introduced into the line there should not bewrong bit. In case there should be, this could'be caused by a badclock extraction; regulate the variable capacity (on the back of themodule) until the error bit counting stops