Decoders and Encoders Discussion D4.2
Dec 22, 2015
3-to-8 Decoder
Behavior
A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1
A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1
input [2:0] A ;wire [2:0] A ;
output [0:7] Y ;reg [0:7] Y ;
for(i = 0; i <= 7; i = i+1)if(A == i)
Y[i] = 1;else
Y[i] = 0;
3-to-8 Decodermodule decode38 ( A, Y );
input [2:0] A ;wire [2:0] A ;
output [0:7] Y ;reg [0:7] Y ;
integer i;
always @(A)for(i = 0; i <= 7; i = i+1)
if(A == i)Y[i] = 1;
elseY[i] = 0;
endmodule
decode38.v
TTL Decoders1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
GND
Vcc 1G
1A
1B
1Y0
1Y1
1Y2
1Y3
2G2A
2B
2Y0
2Y1
2Y2
2Y3
74LS139
Y0 Y1 Y2 Y3 B A G
1 X X 1 1 1 10 0 0 0 1 1 10 0 1 1 0 1 10 1 0 1 1 0 10 1 1 1 1 1 0
Dual 2-4 Decoder
TTL Decoders
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
GND
Vcc A
B
C
G1
Y7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
!G2A
!G2B
74LS138
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7G1 G2
G2 = G2A # G2B X = don't care
X 1 X X X 1 1 1 1 1 1 1 10 X X X X 1 1 1 1 1 1 1 11 0 0 0 0 0 1 1 1 1 1 1 11 0 0 0 1 1 0 1 1 1 1 1 11 0 0 1 0 1 1 0 1 1 1 1 11 0 0 1 1 1 1 1 0 1 1 1 11 0 1 0 0 1 1 1 1 0 1 1 11 0 1 0 1 1 1 1 1 1 0 1 11 0 1 1 0 1 1 1 1 1 1 0 11 0 1 1 1 1 1 1 1 1 1 1 0
3-to-8 Decoder
Encoders
A
B
I0
I1
I2
I3
4-to-2 Encoder 1 0 0 0 0 0
0 1 0 0 0 10 0 1 0 1 00 0 0 1 1 1
I0 I1 I2 I3 B A
Encoders
1 0 0 0 0 00 1 0 0 0 10 0 1 0 1 00 0 0 1 1 1
I0 I1 I2 I3 B AAssume only 1 inputcan be high at any time.
A = I1 + I3B = I2 + I3
I1
I2I3
I0
B = I2 + I3
A = I1 + I3
8-to-3 Encoder
1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
Y2 = I7 + I6 + I5 + I4Y1 = I7 + I6 + I3 + I2Y0 = I7 + I5 + I3 + I1
Priority Encoder
1 0 0 0 0 0 0 0 0 0 0X 1 0 0 0 0 0 0 0 0 1X X 1 0 0 0 0 0 0 1 0X X X 1 0 0 0 0 0 1 1X X X X 1 0 0 0 1 0 0X X X X X 1 0 0 1 0 1X X X X X X 1 0 1 1 0X X X X X X X 1 1 1 1
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
Priority Encoder
1 0 0 0 0 0 0 0 0 0 0X 1 0 0 0 0 0 0 0 0 1X X 1 0 0 0 0 0 0 1 0X X X 1 0 0 0 0 0 1 1X X X X 1 0 0 0 1 0 0X X X X X 1 0 0 1 0 1X X X X X X 1 0 1 1 0X X X X X X X 1 1 1 1
Y2 = L7
+ L6
+ L5
+ L4
L7 = I7
L6 = I7'I6
L5 = I7'I6'I5
L4 = I7'I6'I5'I4
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
Priority Encoder
1 0 0 0 0 0 0 0 0 0 0X 1 0 0 0 0 0 0 0 0 1X X 1 0 0 0 0 0 0 1 0X X X 1 0 0 0 0 0 1 1X X X X 1 0 0 0 1 0 0X X X X X 1 0 0 1 0 1X X X X X X 1 0 1 1 0X X X X X X X 1 1 1 1
Y1 = L7
+ L6
+ L3
+ L2
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
L7 = I7
L6 = I7'I6
L3 = I7'I6'I5'I4'I3
L2 = I7'I6'I5'I4'I3'I2
Priority Encoder
1 0 0 0 0 0 0 0 0 0 0X 1 0 0 0 0 0 0 0 0 1X X 1 0 0 0 0 0 0 1 0X X X 1 0 0 0 0 0 1 1X X X X 1 0 0 0 1 0 0X X X X X 1 0 0 1 0 1X X X X X X 1 0 1 1 0X X X X X X X 1 1 1 1
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
Y0 = L7
+ L5
+ L3
+ L1
L7 = I7
L5 = I7'I6'I5
L3 = I7'I6'I5'I4'I3
L1 = I7'I6'I5'I4'I3'I2'I1
TTL Priority Encoder
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
GND
Vcc
1
2
3
4 5
6
7
A2
A1
E1
E0
GS
0 A0
74LS148
1 X X X X X X X X 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 00 X X X X X X X 0 0 0 0 0 10 X X X X X X 0 1 0 0 1 0 10 X X X X X 0 1 1 0 1 0 0 10 X X X X 0 1 1 1 0 1 1 0 10 X X X 0 1 1 1 1 1 0 0 0 10 X X 0 1 1 1 1 1 1 0 1 0 1 0 X 0 1 1 1 1 1 1 1 1 0 0 10 0 1 1 1 1 1 1 1 1 1 1 0 1
EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO
Priority Encoder
entity pencoder is
port (
x: in STD_LOGIC_VECTOR (7 downto 0);
E: in STD_LOGIC;
y: out STD_LOGIC_VECTOR (2 downto 0);
A: out STD_LOGIC
);
end pencoder;
8-to-3 Priority Encoder
architecture pencoder_arch of pencoder isbegin pe: process(x,E) variable k: integer; begin y <= "000"; A <= '0'; if E = '1' then for j in 0 to 7 loop if x(j) = '1' then
y <= conv_std_logic_vector(j,3); A <= '1'; end if; end loop; end if; end process pe;end pencoder_arch;