Ultra-Threaded Dispatch Processor SIMD Array Setup Engine AMD Barts(Radeon HD 68xx) Overview (一部推定) Copyright (c) 2010 Hiroshige Goto All rights reserved. Geometry Assembler Ultra-Threaded Dispatch Processor Tessellator (Gen7) Command Processor RISC based Micro-Coded engine Hierarchical Z Data Share Data Share Data Share Data Share Data Share Data Share Data Share L1 Texture Cache 8KB (read only) Global Data Share 64KB (read&write) Instruction Cache Constant Cache L2 Texture Cache 128KB (read only) Z/Stencil Cache Color Cache Hub UVD3 (Universal Video Decoder) CrossFireX Compositor Vertices Geometry Command Queue L1 TC 8KB L1 TC 8KB L1 TC 8KB L1 TC 8KB L1 TC 8KB L1 TC 8KB 256-bit GDDR5 Interface Render Back--End Z/Stencil Cache Color Cache Render Back--End GDDR5 Memory Controller DRAM Controller DRAM Controller GDDR5 32-bit 32-bit L2 Texture Cache 128KB (read only) Z/Stencil Cache Color Cache Render Back--End Z/Stencil Cache Color Cache Render Back--End GDDR5 Memory Controller DRAM Controller DRAM Controller GDDR5 32-bit 32-bit L2 Texture Cache 128KB (read only) Z/Stencil Cache Color Cache Render Back--End Z/Stencil Cache Color Cache Render Back--End GDDR5 Memory Controller DRAM Controller DRAM Controller GDDR5 32-bit 32-bit SIMD Array Data Share Data Share Data Share Data Share Data Share Data Share Data Share L1 Texture Cache 8KB (read only) L1 TC 8KB L1 TC 8KB L1 TC 8KB L1 TC 8KB L1 TC 8KB L1 TC 8KB Crossbar (up) L2 Texture Cache 128KB (read only) Z/Stencil Cache Color Cache Render Back--End Z/Stencil Cache Color Cache Render Back--End GDDR5 Memory Controller DRAM Controller DRAM Controller GDDR5 32-bit 32-bit Crossbar (Down) = Shader Export Scan Converter /Rasterizer Vertex Assembler Pixels Hierarchical Z Scan Converter /Rasterizer Pixels PCI Express Gen2.1 Crossbar (Down) = Shader Export Eyefinity Display Controllers Instruction Cache Constant Cache Geometry Vertices Command Queue Command Queue Command Queue Command Queue Command Queue