ADC-VPX3-XMC-RTM User Manual V1 - Alpha Data user...ADC-VPX3-XMC-RTM User Manual V1.0 - 2nd October 2015 1 About the Hardware The ADC-VPX3-XMC-RTM is an Open VPX compliant XMC RTM

ADC-VPX3-XMC-RTMUser ManualDocument Revision: 1.0

2nd October 2015

ADC-VPX3-XMC-RTM User ManualV1.0 - 2nd October 2015

© 2015 Copyright Alpha Data Parallel Systems Ltd.All rights reserved.

This publication is protected by Copyright Law, with all rights reserved. No part of thispublication may be reproduced, in any shape or form, without prior written consent from Alpha

Data Parallel Systems Ltd.

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Address: 4 West Silvermills Lane,Edinburgh, EH3 5BD, UK

Telephone: +44 131 558 2600Fax: +44 131 558 2700email: [email protected]: http://www.alpha-data.com

US Office

3507 Ringsby Court Suite 105,Denver, CO 80216(303) 954 8768(866) 820 9956 toll [email protected]://www.alpha-data.com

All trademarks are the property of their respective owners.


Table Of Contents

1 About the Hardware ......................................................................................................................... 12 Board Features ................................................................................................................................ 2 2.1 ATX Power ..................................................................................................................................... 2 2.2 Current Monitoring ......................................................................................................................... 2 2.3 REFCLK/REFCLK ......................................................................................................................... 2 2.4 JTAG .............................................................................................................................................. 2 2.5 Switch ............................................................................................................................................ 2 2.6 PCIe Re-Driver .............................................................................................................................. 2 2.7 High Speed Signaling .................................................................................................................... 3 2.8 Header Pins ................................................................................................................................... 3

Appendix A Carrier Connector Pin Assignments and Locations .................................................................... 5

List of Tables

Table 1 SW1 Definitions ................................................................................................................................. 2Table 2 Pin Assignments ................................................................................................................................ 6

List of Figures

Figure 1 ADC-VPX3-XMC-RTM Block Diagram .............................................................................................. 1Figure 2 ADC-VPX3-XMC-RTM ....................................................................................................................... 1Figure 3 Top Side Assembly Drawing .............................................................................................................. 5


Page Intentionally left blank


1 About the HardwareThe ADC-VPX3-XMC-RTM is an Open VPX compliant XMC RTM designed to interface with Alpha Data 3U VPXcards. All signals from the VPX backplane are available on the RTM by header pins or high-speed cagestandards (iPASS, QSFP, and SFP).

RP0

RP1

RP2

PCIeRe-Driver

iPass

2x SFP

2x zQSFP

GPIO Headers

ATX PowerCurrentMonitoring

x4

x8

x2

GPIO:36 Diff Pairs16 Single Ended

Util

ityD

ata

Da

taE

xpa

nsi

on

Co

ntr

ol

Use

r D

efin

ed

Figure 1 : ADC-VPX3-XMC-RTM Block Diagram

Figure 2 : ADC-VPX3-XMC-RTM

Page 1About the Hardwaread-ug-1254_v1_0.pdf


2 Board Features2.1 ATX Power

The ADC-VPX3-XMC-RTM provides an ATX power connector allowing the RTM and VPX backplane to bepowered from a standard ATX power supply. The supply is configured to be always on with the expectation thatthe switch on the power supply itself will act as the power switch for the system.

2.2 Current MonitoringThe power from the ATX power supply is sent through current sensing resistors. The amplified voltage differentialover the current sense resistors is available at J1 (near RP0).

3.3V current is measured differentially across pins 1 and 2



The voltage to current ratio is such that 100mV = 1A on any of the three power feeds.

2.3 REFCLK/REFCLKThe auxclk and refclk connections use an industry standard SMB receptacle. The clock signals are directlyconnected to the backplane.

For pin assignments, please see the appendix.

2.4 JTAGA Xilinx standard 14-way parallel JTAG cable receptacle also connects to the backplane.

2.5 SwitchSW1 provides user control over the geographic address pins, NVMRO, and the PCIe re-driver loopback

SwitchRef. Function ON State Off State

SW1-1 NVMRO 0 1

SW1-2 LPBK Normal operation PCIe looped back

SW1-3 GA0 0 1

SW1-4 GA1 0 1

SW1-5 GA2 0 1

SW1-6 GA3 0 1

SW1-7 GA4 0 1

SW1-8 GAP 0 1

Table 1 : SW1 Definitions

2.6 PCIe Re-DriverThe ADC-VPX3-XMC-RTM employs a DS80PCI402 to boost the strength of the PCIe signal from the iPASScable cage to the VPX card on the other side of the backplane. This re-Driver does not guarantee PCIe link

Page 2 Board Featuresad-ug-1254_v1_0.pdf


reliability though the re-driver characteristics can be modified with resister strapping as needed to improve linkreliability. Contact [email protected] for questions regarding resisotr strapping.

The PCIe clock from the iPASS cage is not used.

2.7 High Speed SignalingThe iPass cage provides a x4 PCIe interface that is theoretically capable of Gen3 speeds. The PCIe referenceclock from the cable is not passed to the backplane.

The double height zQSFP cage provides access to the openVPX data and expansion interfaces.

The double height SFP cage provides access to the openVPX control planes.


2.8 Header PinsAll other IO on the board is broken out using 0.1" header pins. The board uses Wurth 613 series header pins.(i.e. 61304021121)


Page 3Board Featuresad-ug-1254_v1_0.pdf



Page 4 Board Featuresad-ug-1254_v1_0.pdf


Appendix A: Carrier Connector Pin Assignments andLocations

Figure 3 : Top Side Assembly Drawing

Page 5Carrier Connector Pin Assignments and Locationsad-ug-1254_v1_0.pdf


Part Reference Pin Number Signal Name Pin Number Part Reference

RP0 C8 AUXCLK_N 1 J5

RP0 B8 AUXCLK_P 1 J3

RP0 B13 DATA_RX0_N L18 J10

RP0 A13 DATA_RX0_P L17 J10

RP0 C14 DATA_RX1_N L21 J10

RP0 B14 DATA_RX1_P L22 J10

RP0 B15 DATA_RX2_N L15 J10

RP0 A15 DATA_RX2_P L14 J10

RP0 C16 DATA_RX3_N L24 J10

RP0 B16 DATA_RX3_P L25 J10

RP0 E13 DATA_TX0_N L37 J10

RP0 D13 DATA_TX0_P L36 J10

RP0 F14 DATA_TX1_N L2 J10

RP0 E14 DATA_TX1_P L3 J10

RP0 E15 DATA_TX2_N L34 J10

RP0 D15 DATA_TX2_P L33 J10

RP0 F16 DATA_TX3_N L5 J10

RP0 E16 DATA_TX3_P L6 J10

RP0 A6 GA0 3 SW1

RP0 B6 GA1 4 SW1

RP0 F6 GA2 5 SW1

RP0 G6 GA3 6 SW1

RP0 F5 GA4 7 SW1

RP0 G5 GAP 8 SW1

RP0 G9 GP0 1 J12

RP0 G11 GP1 2 J12

RP0 G13 GP2 3 J12

RP0 G15 GP3 4 J12

RP0 A4 NVMRO 1 SW1

RP0 B9 PCIE_RX0_N B3 J7

RP0 A9 PCIE_RX0_P B2 J7

RP0 C10 PCIE_RX1_N B6 J7

RP0 B10 PCIE_RX1_P B5 J7

RP0 B11 PCIE_RX2_N B9 J7

RP0 A11 PCIE_RX2_P B8 J7

RP0 C12 PCIE_RX3_N B12 J7

Table 2 : Pin Assignments (continued on next page)

Page 6 Carrier Connector Pin Assignments and Locationsad-ug-1254_v1_0.pdf



RP0 B12 PCIE_RX3_P B11 J7

RP0 E9 PCIE_TX0_N A3 J7

RP0 D9 PCIE_TX0_P A2 J7

RP0 F10 PCIE_TX1_N A6 J7

RP0 E10 PCIE_TX1_P A5 J7

RP0 E11 PCIE_TX2_N A9 J7

RP0 D11 PCIE_TX2_P A8 J7

RP0 F12 PCIE_TX3_N A12 J7

RP0 E12 PCIE_TX3_P A11 J7

RP0 F8 REFCLK_N 1 J9

RP0 E8 REFCLK_P 1 J8

RP0 B5 SM0 1 J4

RP0 A5 SM1 3 J4

RP0 G4 SM2 2 J4

RP0 F4 SM3 4 J4

RP0 B4 SYSRESET 20K PU 20K PU

RP0 G7 TCK 6 J6

RP0 D7 TDI 10 J6

RP0 E7 TDO 8 J6

RP0 B7 TMS 4 J6

RP0 A7 TRST_L 20K PU 20K PU

RP1 C8 ETH1_RX_N L12 J11

RP1 B8 ETH1_RX_P L13 J11

RP1 F8 ETH1_TX_N L19 J11

RP1 E8 ETH1_TX_P L18 J11

RP1 B7 ETH2_RX_N U12 J11

RP1 A7 ETH2_RX_P U13 J11

RP1 E7 ETH2_TX_N U19 J11

RP1 D7 ETH2_TX_P U18 J11

RP1 B1 EXP_RX0_N U18 J10

RP1 A1 EXP_RX0_P U17 J10

RP1 C2 EXP_RX1_N U21 J10

RP1 B2 EXP_RX1_P U22 J10

RP1 B3 EXP_RX2_N U15 J10

RP1 A3 EXP_RX2_P U14 J10

RP1 C4 EXP_RX3_N U24 J10





RP1 B4 EXP_RX3_P U25 J10

RP1 E1 EXP_TX0_N U37 J10

RP1 D1 EXP_TX0_P U36 J10

RP1 F2 EXP_TX1_N U2 J10

RP1 E2 EXP_TX1_P U3 J10

RP1 E3 EXP_TX2_N U34 J10

RP1 D3 EXP_TX2_P U33 J10

RP1 F4 EXP_TX3_N U5 J10

RP1 E4 EXP_TX3_P U6 J10

RP1 G13 GP10 11 J12

RP1 G15 GP11 12 J12

RP1 G1 GP4 5 J12

RP1 G3 GP5 6 J12

RP1 G5 GP6 7 J12

RP1 G7 GP7 8 J12

RP1 G9 GP8 9 J12

RP1 G11 GP9 10 J12

RP1 D5 P1_N1 4 J13

RP1 A5 P1_N2 6 J13

RP1 E6 P1_N3 8 J13

RP1 B6 P1_N4 10 J13

RP1 E5 P1_P1 3 J13

RP1 B5 P1_P2 5 J13

RP1 F6 P1_P3 7 J13

RP1 C6 P1_P4 9 J13

RP1 D9 P2_N1 12 J13

RP1 A13 P2_N10 30 J13

RP1 E14 P2_N11 32 J13

RP1 B14 P2_N12 34 J13

RP1 D15 P2_N13 36 J13

RP1 A15 P2_N14 38 J13

RP1 E16 P2_N15 4 J14

RP1 B16 P2_N16 6 J14

RP1 A9 P2_N2 14 J13

RP1 E10 P2_N3 16 J13

RP1 B10 P2_N4 18 J13





RP1 D11 P2_N5 20 J13

RP1 A11 P2_N6 22 J13

RP1 E12 P2_N7 24 J13

RP1 B12 P2_N8 26 J13

RP1 D13 P2_N9 28 J13

RP1 E9 P2_P1 11 J13

RP1 B13 P2_P10 29 J13

RP1 F14 P2_P11 31 J13

RP1 C14 P2_P12 33 J13

RP1 E15 P2_P13 35 J13

RP1 B15 P2_P14 37 J13

RP1 F16 P2_P15 3 J14

RP1 C16 P2_P16 5 J14

RP1 B9 P2_P2 13 J13

RP1 F10 P2_P3 15 J13

RP1 C10 P2_P4 17 J13

RP1 E11 P2_P5 19 J13

RP1 B11 P2_P6 21 J13

RP1 F12 P2_P7 23 J13

RP1 C12 P2_P8 25 J13

RP1 E13 P2_P9 27 J13

RP2 G1 GP12 13 J12

RP2 G3 GP13 14 J12

RP2 G5 GP14 15 J12

RP2 G7 GP15 16 J12

RP2 D1 P2_N17 8 J14

RP2 A1 P2_N18 10 J14

RP2 E2 P2_N19 12 J14

RP2 B2 P2_N20 14 J14

RP2 D3 P2_N21 16 J14

RP2 A3 P2_N22 18 J14

RP2 E4 P2_N23 20 J14

RP2 B4 P2_N24 22 J14

RP2 D5 P2_N25 24 J14

RP2 A5 P2_N26 26 J14

RP2 E6 P2_N27 28 J14





RP2 B6 P2_N28 30 J14

RP2 D7 P2_N29 32 J14

RP2 A7 P2_N30 34 J14

RP2 E8 P2_N31 36 J14

RP2 B8 P2_N32 38 J14

RP2 E1 P2_P17 7 J14

RP2 B1 P2_P18 9 J14

RP2 F2 P2_P19 11 J14

RP2 C2 P2_P20 13 J14

RP2 E3 P2_P21 15 J14

RP2 B3 P2_P22 17 J14

RP2 F4 P2_P23 19 J14

RP2 C4 P2_P24 21 J14

RP2 E5 P2_P25 23 J14

RP2 B5 P2_P26 25 J14

RP2 F6 P2_P27 27 J14

RP2 C6 P2_P28 29 J14

RP2 E7 P2_P29 31 J14

RP2 B7 P2_P30 33 J14

RP2 F8 P2_P31 35 J14

RP2 C8 P2_P32 37 J14

J13 1 GND 1 J14

J13 2 GND 2 J14

J13 39 GND 39 J14

J13 40 GND 40 J14

J4 5 GND 17 J12

J4 6 GND 18 J12

Table 2 : Pin Assignments



Revision HistoryDate Revision Changed By Nature of Change

1 Oct 2015 1.0 K. Roth Initial Release




Address: 4 West Silvermills Lane,Edinburgh, EH3 5BD, UK

Telephone: +44 131 558 2600Fax: +44 131 558 2700email: [email protected]: http://www.alpha-data.com

Address: 3507 Ringsby Court Suite 105,Denver, CO 80216

Telephone: (303) 954 8768Fax: (866) 820 9956 toll freeemail: [email protected]: http://www.alpha-data.com

4.5

ADC-VPX3-XMC-RTM User Manual V1 - Alpha Data user...ADC-VPX3-XMC-RTM User Manual V1.0 - 2nd October 2015 1 About the Hardware The ADC-VPX3-XMC-RTM is an Open VPX compliant XMC RTM

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