Adam Marmbrant Samuel Silverstein Stockholm University Link Test Status 2 Goals of study Explore several ideas: Low-cost hardware? 10 Gbit ethernet vs. high speed FPGA I/O Cheap FPGAs (Spartan 3) Running links synchronously? Use LHC bunch structure to schedule link retiming (comma chars) in empty BCs Run from TTC clock Commercial jitter cleaners sufficient? 3 Ribbon Fiber Simple transmitter (Zarlink ZL60113) up to 12 channels 3.2 Gb/s Low latency 4 Link board prototype (Stockholm) Readily available components TI TLK3114SCZPV 10 Gb ENET transceivers Xilinx XC3S1400AN-4 FPGA National Semiconductor LMK03033CISQ clock conditioner Zarlink Tx 10 Gbit FPGA 10 Gbit 30 Gb/s 12-fiber bundle 96 x 320 Mb/s Zarlink Rx and/or or 5 Link prototype Tx Rx SNAP12 FPGA 10 GB TX/RX Jitter cleaner 6 Link prototype 7 Link test motherboard data out data in TTC fiber FPGA serial terminal TTCdec daughter card 8 Test setup 9 Current test setup Repeating sequence of parity-encoded data Destination performs parity check One of three transceiver chips used so far (4 of 12 lanes) Simulated TTC optical signal from Spartan-5 developer board Will also test with TTCvi crate Using Deskew-1 output with PLL from TTCdec Link resynchronization during the large gap in LHC bunch structure 10 Current test setup 32-bit test sequence (24b + 8b checksum) Checksum tested at destination Data source Data sink 4 of 12 lanes currently populated 11 Test setup 12 Phase sweep of data clock ~800 ps 13 Timing-in "by design" CK0 CK90 CK180 CK270 Spartan3 DCM To pattern generator To I/O buffer multiplexers CKIN 160 MHz Works well in overnight runs 14 Results Long, stable runs with no parity errors! 17 hours 4 lanes 2.56 Gbit/s gives upper BER limit of 1.6e-15 Link very stable, very low realignment needed Last week: 1500 seconds between realignment words without errors Realignment takes fraction of a tick two consecutive data words (rising, falling edges of 160 MHz clock) 15 Outlook Near-term plans Run with all three transceivers (12 lanes) Precise jitter measurements of conditoned TTC clock Latency measurements between transmitting and receiving FPGAs Run from "real" LHC clock hardware (TTCvi) 16 Conclusions Low cost hardware 10 Gbit ENET transceivers are relatively inexpensive and definitely usable in LHC environment. Spartan 3 being used at its speed limit; we probably want a more modern device... Synchronous running possible Resynching during one of the LHC bunch gaps is more than sufficient to maintain link Commercial clock conditioner can clean TTC clock well enough to run multi-GB links Will do more careful measurements in near future
