Samuel Silverstein Stockholm University L1Calo upgrade hardware planning + Overview of current concept + Recent work, results.

Samuel Silverstein Stockholm University

L1Calo upgrade hardware planning

+ Overview of current concept+ Recent work, results

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Upgrade phases

Phase I (2012 - 2019?): upgrade current L1Calo FPGA-based MCM replacement for PreProcessor (?) Augment EM/Had and Jet/Energy processors with

CMM++ to add topological algorithm capabilities, Phase II (2020 - ) Replace L1Calo with 2-level system

Full digital readout of LAr, Tile data to RODs in USA15 "Level 0": Synchronous, fixed latency,

Topological algorithms with calorimeters + muon ROIs "Level 1": Asynchronous, longer latency, access to full

resolution calorimeter data, Topological algorithms with calo, muon and ID ROIs

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Phase-I summary

Goals: Extend useful life of existing HW Minimize impact on external systems Provide technical "bridge" to phase-II

High-speed optical links allow parasitic testing of new hardware

Use some prototype phase-II hardware for phase-I (e.g. topo processor)?

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Phase I status

Good progress on developing formats and firmware for 160 MHz backplane transmission Upcoming tests with real modules + BLT

Promising results from early CMM++ firmware studies Existing code easily ported to Virtex-6

(Sam + Ian) Reasonable design concept using target FPGA

Reasonable prospects for improving L1Calo performance, extending useful lifetime

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Merger replacement: CMM++

Legacy DAQ, ROI readout

(Glink)

SNAP12

SNAP12

SNAP12

Topologicalprocessor links:12-fiber bundles,6.4/10 Gbit/s/fiber

LegacyLVDS outputs to CTP

Virtex 6HX565T

Backplanedata fromJEM/CPMmodules(160 MHz)

LVDS merger links

SNAP12

SNAP12

SNAP12

VMECPLD

VME --

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Topoproc.

Jet / ET

(JEP)0.2 x 0.2

E/ /hadclusters

(CP)

0.1 x 0.1

Pre-Processor(PPr)

Analogtower sums(0.1 x 0.1)

Topo processor can be a separate subsystem...

use phase-II prototypehardware (L0Topo)?

Jets

ClustersTo CTP

Energy results to CTP?

Muons

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...or only using CMM++ modules

JEP0

JEP1

CP0

CP2

CP1

CP3

EM EMEM/ EM/JetEnergy

LVDS

CLU

ST

ER

EN

ER

GY

JET

N.B. Maximum 8 e/tau thresholds

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Phase I topological algos:

Begin with simple, "generic" algorithms, including: Overlaps between jets and other objects Improved missing ET ?

Add more complex algorithms for specific physics processes: Rapidity gaps, non-back-to-back jets for

diffractive processes Transverse or invariant mass for W, Z, Higgs Sphericity / aplanarity (?)

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These appear to help!

Sphericity

Overlap Removal

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Phase II concept

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L0 overview Synchronous:

Input rate 40 MHz Fixed latency: <3.2 s?

L0Calo: sliding window algorithms Include HLT-inspired cluster algorithms

Input from calorimeter RODs (proposed): Trigger towers (0.1 0.1) with finer etaphi, depth

segmentation. Three output data streams: One 10 Gbit fiber per TT in etaphi from LAR RODs one fiber per 2 4 TTs from Tile RODs Lower-resolution EM data (0.1 0.1 TT sums) to jet algorithm

L0Topo: topological algorithms combining calo & muon ROIs Possible dual use as Phase-1 topological processor

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L1 overview Does not need to be synchronous:

Input rate : L0A (limited by slowest subsystem) Variable latency (packet-based data transfers) Some combination of processors and FPGAs?

Input from RODs: Full-resolution calorimeter data around L0 ROIs

L1Calo Improved ID of isolated electrons, hadrons identified by L0 Aim for similar performance to present L2

L0Topo Topological algorithms on L1Calo ROIs, plus ROIs from

muon and L1Track triggers

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Phase II status

GOLD progress in Mainz Real experience with many Phase-II challenges

Complex boards with multiple Virtex 6 FPGAs High speed optical links Clock distribution and conditioning High-power modules in ATCA

Very productive brainstorm on Wednesday Concentrated on L0Calo and inputs from RODs Some interesting ideas came out, including

Optimal balance between optical fiber duplication and electrical fanout on custom 8U backplane

Jet and cluster processing on same module (but different FPGAs?)

Cluster algorithm windows similar size to today's Will write up soon and distribute

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"Staged" deployment Phase-I deployment as soon as feasible

Start with CMM++ Begin with near-"Day-1" functionality Parasitic testing of new algorithms before going live Topological processor subsystem can come later

Phase II deployment L0Calo/L0Topo commissioned with upgraded

calorimeter electronics upgrades L1Topo ready for L1Track

Use L0Calo ROIs until L1Calo commissioned? General strategy: run new components parasitically in

system as early as possible

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Phase-II "staging"With calorimeter upgrades

With ID upgrade

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Overall summary

Phase-I beginning to converge on a stable design concept (at least for CMM++). Need to write up soon Start CMM++ soon, consensus that it is

feasible, will help Phase-II our ultimate target, but actual

hardware ideas more nebulous Hope we have started to change this...

Need to move ahead to have a reasonable design concept in time for T

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Discussion