ACCELERATING DETAILED SIMULATIONS OF AN HVDC SYSTEM BASED ON MODULAR MULTILEVEL CONVERTERS IN A MULTI-CORE ENVIRONMENT by XIAODAN WANG B.S., Beijing Technology and Business University, 2010 A thesis submitted to the Faculty of the Graduate School of the University of Colorado in partial fulfillment of the requirements for the degree of Master of Science Electrical Engineering 2015
81
Embed
ACCELERATING DETAILED SIMULATIONS OF AN HVDC …digital.auraria.edu/content/AA/00/00/32/86/00001/AA00003286_00001.pdfA new High Voltage Direct Current (HVDC) transmission technology
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
ACCELERATING DETAILED SIMULATIONS OF AN HVDC SYSTEM
BASED ON MODULAR MULTILEVEL CONVERTERS IN A MULTI-CORE
ENVIRONMENT
by
XIAODAN WANG
B.S., Beijing Technology and Business University, 2010
A thesis submitted to the
Faculty of the Graduate School of the
University of Colorado in partial fulfillment
of the requirements for the degree of
Master of Science
Electrical Engineering
2015
This thesis for the Master of Science degree by
Xiaodan Wang
has been approved for the
Electrical Engineering Program
by
Fernando Mancilla-David, Chair
Titsa Papantoni
Dan Connors
June 18, 2015
ii
Wang, Xiaodan (Electrical Engineering)
Accelerating Detailed Simulations of an HVDC System Based on Modular Mul-tilevel Converters in a Multi-core Environment
Thesis directed by Professor Fernando Mancilla-David
ABSTRACT
The topology of the Modular Multilevel Converter (MMC) was introduced
in 2001. The MMC topology is well suited for the High Voltage Direct Current
(HVDC) system. The MMC-HVDC topology has several advantages over other
topologies: (i) it is based on simple converter cells, (ii) it has easy voltage
and current scaling, (iii) it features distributed capacitive energy storage, (iv) it
offers straightforward protection schemes, (v) it has low switching frequency and
losses. However, the simulation speed of a detailed MMC model in an HVDC
system is slow due to the computational burden.
In this thesis, with the help of PSCAD/EMTDC, a new approach in a
multi-core CPU environment has been implemented to speed up the simulations
of the HVDC system based on the MMC topology. This approach is evaluated
by comparing results with a single-core average model, a single-core detailed
model and a eight-core detailed model. This thesis also includes an analysis
selecting the best sorting algorithm.
iii
The form and content of this abstract are approved. I recommend its publication.
Approved: Fernando Mancilla-David
iv
DEDICATION
This thesis is dedicated to my family and my girlfriend who have supported me
all the way since the beginning of my studies. They provide me with a great
source of motivation and inspiration. Finally, this thesis is dedicated to all those
who believe that knowledge is power.
v
ACKNOWLEDGMENT
I would like to express my deepest gratitude to my advisor, Professor Fer-
nando Mancilla-David, for his excellent guidance, care, patience, and for pro-
viding me with an excellent environment for doing research.
I greatly appreciate Professors Titsa Papantoni, and Professor Dan Con-
nors for forming part of my dissertation defense committee. Finally, I would
like to thank my family; they were always there cheering me up and stood by
me through the good and bad times.
I also want to thank Phd student Miguel Carrasco for his tips on my simu-
6.1 Simulation time versus Submodule number on each arm. . . . . . . 54
xii
1. Introduction
A new High Voltage Direct Current (HVDC) transmission technology based
on the Modular Multilevel Converter (MMC) topology has been introduced in
recent years. In this topology, the converter arm behaves as a controllable
voltage source with a high number of possible discrete voltage steps, which
together can produce close to a true sinusoidal voltage in the AC terminal [1].
MMC topology enables using a smaller switching frequency to reduce converter
losses and eliminates the filter requirements by using a significant number of
levels per arm [2]. Nowadays, there are five MMC-HVDC projects in progress
in Europe [3][4].
In the following thesis, the basics of the MMC-HVDC technology is ex-
plained in Section 1; the power stage design is shown in Section 2; the control
strategies are shown in Section 3; the sorting algorithm is shown in Section 4;
the multi-core simulation approach is shown in Section 5; the simulation results
are shown in Section 6; the conclusions are shown in Section 7; the future work
is shown in Section 8.
The advantages of the MMC-HVDC technology are summarized in [5, 6, 7]:
• AC voltages can be adjusted in very fine increments and a DC voltage with
very little ripple can be achieved, this minimizes the level of generated
harmonics and in most cases completely eliminates the need for AC filters.
• The low switching frequency of the individual semiconductors results in
very low switching losses. Total system losses are therefore relatively low,
1
and the efficiency is consequently higher than existing two– and three–level
solutions.
• Due to the elimination of additional components such as AC filters and
their switchgear, high reliability and availability can be achieved.
• Through a highly modular construction both in the power section and
in control and protection, the system is very scalable, (i.e. conveniently
adaptable to any required power and voltage ratings.)
• With respect to later provision of spare-parts, it is easy to replace existing
components by state-of-the-art ones, since the switching characteristics
of each power module are determined independently of the behavior of
the other power modules. This is an important difference to the direct
series-connection of semiconductors as in the two-level technology where
nearly identical switching characteristics of the individual semiconductors
are mandatory.
• Independent control of active and reactive power. As a consequence, no
reactive power compensation equipment is needed at the station.
• Possibility to connect the system to a “weak” ac network or even to one
where no generation source is available and the short-circuit level is very
low.
• It can provide a variety of ancillary services to the interconnected ac sys-
tems, such as harmonic and unbalanced voltage compensation, flicker elim-
ination, etc.
2
2. Power stage
In a back-to-back configuration, two converters are connected by a DC link
capacitor, as shown in Figure 2.1. Each converter can independently synthe-
size a sinusoidal voltage at its terminals. These voltages can be defined by
their amplitudes (V1, V2) and phase angles (θ1, θ2). Active power injections
depend mainly on phase angles, while reactive power injections depend on the
amplitudes of the synthesized voltages. The MMC topology allows independent
control of the voltage amplitudes V1 and V2. Therefore, reactive power injections
on both sides can be controlled independently. However, phase angles (θ1, θ2)
need to be controlled in such a way that the active power being transmitted
by one converter equals the active power transmitted by the other converter in
steady state to keep the energy of the DC link constant.
AC System 1 AC System 2
V1 V2
V1
θ1V2
θ2
MMC1
MMC2
Figure 2.1: Schematic of the HVDC back–to–back system.
The basic component of the MMC converter is a simple half bridge with a
capacitor called power submodule (SM), as shown in Figure 2.2(a). With the
two power electronic switches, an SM can generate two output voltages, zero, or
3
the voltage of the capacitor. An SM has bidirectional current capability. The
capacitor can be charged or discharged depending on the direction of the arm
current [8][9]. The series connection of a number of SMs constitutes an arm, as
shown in Figure 2.2(b). In the converter there are three legs, one for each phase.
A converter leg is composed of an upper and a lower arm. Figure 2.2(c) shows
the structure of the converter. The number of the output steps depends on the
number of SMs available in each arm. By connecting enough SMs in series, no
AC filters will be necessary. In the TransBay Cable Project, Siemens used more
than 200 SMs per converter arm. As a result, the synthesized voltage profile is
very close to sinusoidal [1].
SM SM
SM
ArmArm
Arm
Arm
Arm
Arm
Arm
phase a phase b phase c
(a) (b) (c)
Leg
Figure 2.2: (a) Structure of a SM; (b) series connection of a number of SMsconstituting an arm; (c) converter composed of three legs – one for each phase.
2.1 Design parameters
Figure 2.3 shows the overview of the HVDC system implemented in PSCAD.
Each converter consists of three legs. In turn, each leg is composed by two arms,
and each arm is electrically connected with a certain number of SMs in series.
Since the MMC topology belongs to the VSC family, a DC link capacitor is
4
needed. Both converters are connected to the grid through a circuit breaker.
The initial state of both breakers are open, and they will close after all SMs are
fully charged. The nominal power is 110 MW. The selected DC voltage is ±200
kV. The number of SMs per arm was chosen to be 36 by heuristics because there
is a trade of between the computational complexity and the harmonics content
on the synthesized voltage.
5
Ibus
VA
VF
Ph
0.1
13
2 [H
]
Vo
ltag
e w
es
t
60.0
0.0
Mai
n : C
...
1.5
0.1
Vol
tage
wes
t
1
* 230.0
#2
um
ec
#1
#2
um
ec
#1bu
s2
VA
VF
Ph0.2
59
8 [H
]
Vo
ltag
e e
as
t
60.0
0.0
Mai
n : C
...
1.5
0.1
Vol
tage
eas
t
1
* 230.0
R=0V
20
0.0
20
0.0
R=0V
10 [uF] 10 [uF]
BR
K
Tim
ed
Bre
ake
rL
og
icC
los
ed
@t0
BR
K
BR
K
DC
_1
DC
_2
AC
P_
ref
Q_
ref
Wes
t M
MC
Pre
f_W
es
tP
ref_
Ea
st
Qre
f_E
as
tQ
ref_
We
st
DC
_1
DC
_2
AC
P_
ref
Q_
ref
Eas
t M
MC
Wes
t Tra
nsfo
rmer
Wes
t AC
Sys
tem
Eas
t Tra
nsfo
rmer
Eas
t AC
Sys
tem
DC
Lin
k
Vd
c
Figure 2.3: Overview of the HVDC system in PSCAD.
6
The primary side of the transformer is rated at 230 kV with a grounded Wye
connection and the secondary side is rated at 180 kV with a delta connection,
considering the DC link voltage ±200 kV. A leakage reactance of 10% is selected
as a typical value of this rated power.
The insulated-gate bipolar transistors (IGBTs) in each SM are selected ac-
cording to their voltage blocking and maximal current conduction capabilities.
The voltage blocking capability needs to reach Vb=400/36=11.1 kV and a max-
imum forward current of 1.2 kA. The resistance of the selected IGBT is 1 mΩ,
therefore, the total resistance of each arm is 36 mΩ. The capacitance of each
SM may be obtained by the following equation [10]:
C =2SEMMC
6NarmV 2C
where S is the nominal power of the converter, EMMC is the capacitor’s storage
energy in [KJ/MVA], Narm is the number of the SMs in each arm, and VC is the
SM nominal voltage.
With a storage energy of 331 kJMVA
[5], combining all the known parameters
in the equation, the capacitance is found to be 16.4 mF. The arm inductance,
LS, has been selected as 15% of the system’s base impedance, as shown in the
following equation [10].
Zs =V 2
ac
S
Ls = 0.15Zs = 0.1172H
All system parameters are summarized in the Table 2.1.
7
Table 2.1: Design parameters.
West AC SystemBus Voltage East (kV) 230Thevenin Equivalent Impedance (H) 0.1132West TransformerPrimary Voltage (kV) 230 (Y)Secondary Voltage (kV) 180 (∆)Power Rating (MVA) 133Leakage Reactance (pu) 0.1West MMCNumber of SMs per arm 36Number of IGBTs per SM 2IGBT blocking capability (kV) 15IGBT maximal forward current (kA) 3IGBT resistance (mΩ) 1SM Capacitor (mF) 14.6Arm inductance (H) 0.1172DC Link CapacitorCapacitance (µF) 0.5Rated voltage (kV) 400East MMCNumber of SMs per arm 36Number of IGBTs per SM 2IGBT blocking capability (kV) 15IGBT maximal forward current (kA) 3IGBT resistance (mΩ) 1SM Capacitor (mF) 14.6Arm inductance (H) 0.1172East TransformerPrimary Voltage (kV) 230 (Y)Secondary Voltage (kV) 180 (∆)Power Rating (MVA) 133Leakage Reactance (pu) 0.1East AC SystemBus Voltage West (kV) 230Thevenin Equivalent Impedance (H) 0.2598
2.2 Average model
To validate the detailed model simulations, the average model is imple-
mented first. In the average model, each arm is presented by an equivalent
8
voltage source, and the calculation is shown in Section 3. The series resistance
and inductance in each average arm is 36 mΩ and 0.117 H, respectively. One
arm in the average model is shown in Figure 2.4.
Arm
Average Vout
Nin
L
R
V-calculated
I
Figure 2.4: Average model arm.
2.3 Detailed model
In the detailed model, each arm has a series connection of a certain number
of SMs. The control on the SMs will be explained in Section 3. One arm in the
detailed model is shown in Figure 2.5.
9
Arm
Detailed Vout
Nin
L
I
SM
SM Controls
Figure 2.5: Detailed model arm.
It is worth noting that the arm inductance and resistance of both models
are same. In the detailed model, the diodes and the IGBTs have the same
resistance. As shown in Figure 2.6, in both on and off states of the SMs, the
arm resistance remains constant, (i.e. the total resistance is a constant 36 mΩ).
10
C C
CC
Capacitor off-state Capacitor on-state
Figure 2.6: Submodule at on-state or off-state.
Finally, the WEST and EAST MMC are modified with either average or
detailed arm, as shown in Figure 2.7.
11
DC_2
DC_1
MMC
average
arm
Vout
Ninor
detailed
MMC
average
arm
Vout
Ninor
detailed
MMC
average
arm
Vout
Ninor
detailed
MMC
average
arm
Vout
Ninor
detailed
MMC
average
arm
Vout
Ninor
detailed
MMC
average
arm
Vout
Ninor
detailed
P = 0.0001059Q = -0.001344
VA
BRK
AC
Vcn_eqVbn_eqVan_eq
Nn_a Nn_b Nn_c
Vcp_eqVbp_eqVap_eq
Np_a Np_cNp_b
Figure 2.7: The MMC with average or detailed arm.
12
3. Control scheme
The overall operation of the converters is directed by the control panel as in
Figure 3.1. The references can be set in this control panel, including the active
and reactive power of the rectifier side, the reactive power of the inverter side
and the active power flow direction.
Figure 3.1: PSCAD control panel.
Depending on the active power flow direction, one of the converter stations
will act as a rectifier and the other one will act as an inverter. For instance, if
power is flowing from the WEST MMC to the EAST MMC, the east converter
will act as the inverter and the west converter will act as the rectifier [11].
13
Reactive powerreference generator
Reactive powerreference generator
Active powerreference generator
Active powerreference generator
Power–to–currenttransformation
Power–to–currenttransformation
Current controller
Current controller
Leg energy controller
Leg energy controller
Modulation
Modulation
Inverter control
Rectifier control
P
Vdc ref
Pref P
Pref V
Qref rect
Qref inv
Qrect
Qinv
Id ref
Iq ref
udiff i 1
i = a, b, c
Ei
i = a, b, c
Id ref
Iq ref
udiff i 1
i = a, b, c
Ei
i = a, b, c
Np i
Nn i
i = a, b, c
400 kV
Controlpanel
Np i
Nn i
i = a, b, c
Wi
i = a, b, c
Wi
i = a, b, c
Figure 3.2: Overview of the control strategy.
Figure 3.2 shows the overall control strategy. Through the ABC-to-DQ
transformation, the active and reactive power references are transformed to DQ
current references an fed to the current controller. The current and energy
controllers then work together to generate the modulation index, N , for each
arm in both converters [12] [13].
3.1 Rectifier and inverter control
The difference between the rectifier and the inverter is the active power
reference generator. In the rectifier, the active power reference and the reactive
power reference are coming directly from the control panel. In the inverter, the
reactive power reference is coming from the control panel, however, the active
power reference is generated by the DC link voltage control.
Following the active and reactive power generators, the power references are
transferred to current references with the ABC-to-DQ transfer. The ABC-to-DQ
14
transformation is based on the following equations:
P =3
2(vdid + vqiq),
Q =3
2(−vdiq + vqid).
The Phase Lock Loop(PLL) forces vq = 0, which will simplify the above
equation set to be:
Pref =3
2vdId ref ,
Qref = −3
2vdIq ref .
Following the power-to-current transformation, reference current and actual
current are compared to generate an error, and the error is driven to zero with
the help of two decoupled compensators. Aiagram of this process is shown in
Figure 3.3. The output signals of the current controller, Ea, Eb and Ec, will be
used as input signal in the modulation in Section 3.3.
Pref
1.5 Vd Id
IdrefP
I
*Iq
wL
Pref
-1.5 Vd Iq
IqrefP
I
Vd
Vq
*Id
wL
Ed
Eq
DQ
to
ABC
Ea
Eb
Ec
Figure 3.3: Current controller.
15
3.2 Leg energy control
The leg energy control is built to balance the three phase voltages and reduce
the circulating current. The energy on each leg is a function of the upper and
lower arm voltages. In other words, the leg energy will be stable if the leg voltage
is fixed, and the three phases will be balanced.
Diffi = (Wi ref −Wi)(Ki +Kp1
s) i = a, b, c,
where Wi = V 2ip eq + V 2
in eqi = a, b, c.
The leg energy controller is shown in Figure 3.4.
X2
X2
W
320000
P
I
Diff
Vup
Vlow
Figure 3.4: Leg energy controller for each phase.
3.3 Modulation
The instantaneous voltage of each arm is determined by the modulation
index N. In the average model, N is in the range of 0 to 1. When N equals 0,
16
all SMs are disconnected, and when N equals 1, all SMs are connected. For the
upper and lower arm in each leg, the modulation indexes are computed as:
Niup =
(Vdc
2− Ei − Udiff i
)1
Viu eq
i = a, b, c
Nilow =
(Vdc
2+ Ei − Udiff i
)1
Vil eq
i = a, b, c
where Vdc is the DC link voltage, Ei is AC terminal voltage to be synthesized
which is determined by the current controller, and Udiff i is the output of the
leg energy controller. At any point in time the sum of the upper and lower
modulation indexes in an arm is one:
Nup +Nlow = 1
A diagram of the modulation index computation for one leg is shown in
Figure 3.5.
2
Vdc
Diff-a
Ea N N
Na-up*
Va-up
2
Vdc
Diff-a
Ea N N
Na-low*
Va-low
Quantizer
Figure 3.5: Per-phase modulation index computation.
17
3.3.1 Control of the average model
The arm equivalent capacitance is:
Ceq =CSM
n
and the arm voltages are:
Viup = Varm iupNup i i = a, b, c
Vilow = Varm ilowNlow i i = a, b, c
where Varm iup and Varm ilow are the equivalent voltages of the upper arm and the
lower arm. Combining the three equations above, the Varm iup and Varm ilow are:
Varm iup =
∫Iiup
Ceq
Nupi
dt i = a, b, c
Varm ilow =
∫Iilow
Ceq
Nlowi
dt i = a, b, c
Based on these equations, the average arm can be modeled as shown in Figure
3.6.
18
Arm
Average Vout
Nin
L
R
V-equiv
I
Nin
I
I-equiv
I-equiv
C
1/sTVout
Vout
Nin
Varm
*
*
Figure 3.6: Arm in the average model.
3.3.2 Control of the detailed model
The detailed model arm is shown in Figure 3.7.
19
Arm
Detailed Vout
Nin
L
I
Nin
Vout
SM
VarraySorting
Algorithm
andSwitching
Delay
Tarry
SM
SM
T(1)
T(2)
T(3)
SMT(N)
V(1)
V(2)
V(3)
V(N)
Figure 3.7: Arm in the detailed model.
In the detailed model, the modulation index needs to be multiplied by the
number of the SMs in each arm. As a result, the modulation index of the detailed
model is an integer in the range of 0 to 36. In general, the number of the levels
is equal to one plus the number of the SMs. It is also worth noting that the
number of SMs has to be even, otherwise the 0 kV level cannot be achieved.
20
Figure 3.8: Different stairs-V comparison with sinusoidal-V.
Three voltage curves with different number of SMs (N) per arm (N=4, N=8,
N=12) are generated as shown in Figure 3.8. It is apparent that as the number
increases, the voltage profile becomes closer to sinusoidal. In the detailed model
simulations, the magnitude of the stepwise curve equals the number of the SMs
in each arm [14].
Assuming there are N SMs in each arm, to satisfy Kirchhoff’s Voltage Law
(KVL), the synthesized voltage on phase A needs to fit both upper arm’s and
lower arm’s voltage drop, as in the following equations:
Va = Vdc/2−NupperarmVsm
Va = −Vdc/2 +NlowerarmVsm
N = Nupperarm +Nlowerarm
Solving the above equations set, Vsm equals Vdc/N. Assuming four SMs, Va
would take values as shown in Table 3.1.
21
Table 3.1: Phase voltage in terms of N.
N(upper) N(lower) Va(upper KVL) Va(lower KVL)
4 0 Vdc/2− 4Vsm = −Vdc/2 −Vdc/2 + 0Vsm = −Vdc/2
3 1 Vdc/2− 3Vsm = −Vdc/4 −Vdc/2 + 1Vsm = −Vdc/4
2 2 Vdc/2− 2Vsm = 0 −Vdc/2 + 2Vsm = 0
1 3 Vdc/2− 1Vsm = Vdc/4 −Vdc/2 + 3Vsm = Vdc/4
0 4 Vdc/2− 0Vsm = Vdc/2 −Vdc/2 + 4Vsm = Vdc/2
Va is in the range of -Vdc/2 to +Vdc/2 by steps of Vdc/4. However, the
size of every step may be different without control. To equalize all the steps,
the SMs voltage balancing algorithm is introduced.
In the following discussion, the term ”ON” signifies that one SM gives the
Capacitor voltage (Vc) as the output voltage, and ”OFF” signifies that a sub-
module gives 0 kV as the output voltage. The number of SMs on and off is in
the range of 0 to 36. Also, N(t) refers to the number of the submodules in the
”ON” state in the upper arm of one phase leg at time ”t”.
The SMs voltages are balanced by turning ON or OFF SMs depending on the
current flow directions. N(t) SMs with lower capacitor voltages will be turned
ON when the arm current flow is charging the capacitors, and OFF when the
arm current flow is discharging them. A flowchart of SMs voltage balancing is
shown in Figure 3.9 [15] [16].
22
Voltage Array
Voltages and Indices Matrix
Indices Array
Sorting with aselected algorithm
Sorted Matrix, ascending order
Current .GE. 0 ?
Yes No
Select N count SMswith low voltage
Select N count SMswith low voltage
Switching Array
Sorting process
Switching process
Figure 3.9: Flowchart of the voltage balancing algorithm.
There are three inputs: (i) N(t), (ii) Id(current direction) and (iii) V(array,
for all SMs). The voltage balancing controller will receive data from all the
inputs during the simulations, then, the data of V(array) will be listed in a table
along with their labels VLB(array). Next, the table of V(array) and VLB(array)
will be sorted into ascending sequence, and finally, the switching signals T(array)
will be generated based on N(t), I, and the sorted table generated in step three
of Figure 3.9. Combined with the voltage balancing control, the detailed arm is
built as shown in Figure 3.7.
23
Also, to accelerate the simulation, the sorting process will only be triggered
when N(t) changes [15]. This will reduce the sorting process’ frequency and the
results will be acceptable if the SMs number is high enough to avoid using filters.
The process of checking whether N(t) changes in the processing time interval
will be notified as ”N-check” in this thesis.
24
4. Sorting algorithm
The sorting algorithm has been selected from three candidates in order to
improve the simulation speed. Three sorting algorithms are evaluated both in
MATLAB and PSCAD. The computing time is matching the computational
complexity (big O notation) in terms of the size of the list(N). The candidate
sorting algorithms are:
• Insertion Sort
• Quick Sort
• Merge Sort.
4.1 Insertion sort
Insertion sort is an iterative algorithm which removes one element from the
input data each iteration and adds it to the correct lovation in a sorted output
list. This process repeats until no input elements remain [17].
The best case input is an array that is already sorted. In this case insertion
sort has a linear running time O(n). During each iteration, the first remaining
element of the input is only compared with the right-most element of the sorted
subsection of the array.
The simplest worst case input is an array sorted in reverse order. The set of
all worst case inputs consists of all arrays where each element is the smallest or
second-smallest of the elements before it. In these cases every iteration of the
25
inner loop will scan and shift the entire sorted subsection of the array before
inserting the next element. This gives insertion sort a quadratic running time
O(n2).
The average case is also quadratic, which makes insertion sort impractical
for sorting large arrays. However, insertion sort is one of the fastest algorithms
for sorting very small arrays, even faster than quick sort. In fact, good quick
sort implementations use insertion sort for arrays smaller than a certain thresh-
old, also when arising as subproblems; the exact threshold must be determined
experimentally and depends on the machine, but is commonly around ten [18].
4.2 Quick sort
Quick sort is a divide and conquer algorithm. Quick sort first divides a
large array into two smaller sub-arrays: the low elements and the high elements.
Quick sort then recursively sorts the sub-arrays [19] [20].
The steps of quick sort are:
1. Pick an element as a pivot from the array. 2. Reorder the array so that
all elements with values less than the pivot are placed before the pivot, while all
elements with values greater than the pivot are placed after it (equal values can
go either way). After this partitioning, the pivot is in its final position, which
is called the partition operation. 3. Recursively apply the above steps to the
sub-array of elements until the sub-array contains one element.
Quick sort’s divide-and-conquer formulation makes it amenable to paral-
lelization using task parallelism. The partitioning step is accomplished through
the use of a parallel prefix sum algorithm to compute an index for each array
element in its section of the partitioned array. Given an array of size n, the
26
partitioning step performs O(n) work in O(logn) time and requires O(n) addi-
tional scratch space. After the array has been partitioned, the two partitions
can be sorted recursively in parallel. Assuming an ideal choice of pivots, parallel
quick sort sorts an array of size n in O(nlogn) work in O(log2n) time using O(n)
additional space.
4.3 Merge sort
Merge sort is an O(nlogn) comparison-based sorting algorithm. Merge sort
is also a divide and conquer algorithm used in computer science [19] [20].
The steps of merge sort are:
1. Divide the unsorted list into n sublists halfway, until each list containing
1 element (a list of 1 element is considered sorted). 2. Repeatedly merge sublists
to produce new sorted sublists until there is only 1 sublist remaining. This will
be the sorted list.
4.4 Performance test
The sorting algorithms are tested both in MATLAB and PSCAD/EMTDC.
Since the tic-toc function is available in MATLAB, a small arbitrarily time
scale is enough for the MATLAB based tests. However, the tic-toc function is
not available in PSCAD, so a longer period of time is necessary to make the
stopwatch reliable for the PSCAD based tests.
4.4.1 MATLAB based tests
Using tic-toc function in MATLAB, these three algorithms computing time
are compared with same input array as shown in Table 4.1.
27
Table 4.1: MATLAB based algorithms speed test results.
Three sorting algorithms are tested with three different input arrays as in
Table 4.3. Array1 requires least effort to sort (because most of the array is
already in ascending order), and Array3 requires most effort to sort (because it
is in opposite order). Setting the time step to 50 µs, and plot step to 250 µs, the
time to complete a 100 s simulation for three sorting algorithms is summarized
in Table 4.4.
32
Table 4.4: PSCAD based algorithms speed test results.
Algorithms Simulation
time(s) for
Array1
Simulation
time(s) for
Array2
Simulation
time(s) for
Array3
Insertion Sort 53.94 54.17 66.66
Merge Sort 55.69 52.40 54.14
Quick Sort 64.41 54.38 64.41
Regarding 36 elements, Table 4.4 shows that: (i) the insertion sort is the
best for a less-effort sorting situation, (ii) the quick sort speed is not stable,
because it is influenced by the pivot selection too much. In this test, the first
element is selected as the pivot, (iii) the merge sort has good speed in all three
situations.
Therefore, the merge sort is the optimal selection when the communication
time is considered.
33
5. Implementation of the detailed model in a multi-core
environment
Other than the selection of the sorting algorithm, a new approach is imple-
mented to accelerate the simulation on the software side. The new approach is
called Electrical-Network-Interface(ENI) and it’s from PSCAD/EMTDC.
The concept of the ENI approach splits the project into pieces, and the
computational burden from every piece is assigned to each CPU core of the
computer. As a result, the overall CPU usage can reach 100%, as shown in
Figure 5.1. For a typical simulation, only two cores will do the processing,
so the CPU usage normally acts as shown in Figure 5.2 on a eight-core CPU
computer. There are two requirements for ENI: 64-bit operation system and a
multi-core CPU.
Figure 5.1: CPU monitor in task manager for ENI.
34
Figure 5.2: CPU monitor in task manager for single core.
In order to fully use the CPU, the number of the splitting pieces has to be
one less than the number of the CPU cores, since one core has to be left for
the PSCAD software and windows operations. For example, in a computer with
eight cores, the original project is better to be split into seven pieces. These
seven pieces will be computed in parallel. Therefore, giving each piece an equal
portion of the total work is preferred, so that the cores who finish their tasks
will not have to wait for other cores who have not finished.
The bridge between different pieces for the ENI approach is the transmission
line as shown in Figure 5.3. The original project is split into a simulation set of
seven project pieces, since the computer running the simulation has eight cores.
35
PHAwest
PHBwest
PHCwest
PHAeast
PHBeast
PHCeast
Arm
Arm
Arm
Arm
Arm
Arm
Arm
Arm
Arm
Arm
Arm
Arm
Main Piece
Arm
Arm
Piece No.2
Arm
Arm
Arm
Arm
Piece No.3 Piece No. 4 Piece No. 7
Transmission Line
Figure 5.3: ENI detailed model.
After splitting, the main project piece consists of the whole system control,
the grid and the DC link. The other six project pieces comprise two arms,
36
the sorting process, the switching process and all the SMs. In Figure 5.3 all
transmission lines are represented by black solid squares.
The main project piece (Part1) is built as shown in Figure 5.4, and other
pieces (Part2-Part7) are shown as in Figure 5.5. The transmission lines are also
useful for sending and receiving data in between different project pieces. As
seen in Figure 5.4 and 5.5, Part1 sends modulation indices to Part2, and Part2
sends arm voltages back to Part1 for both upper and lower arms.
Edc
12
Ncnw Ncpw
12
Nbnw Nbpw
12
Nanw Napw
Tline0
Tline2
Tline1
Vc1w
Vc2w
Vb1w
Vb2wVa2w
Va1w
P
a
r
t
4
:
T
l
i
n
e
8
P
a
r
t
4
:
T
l
i
n
e
7
P
a
r
t
2
:
T
l
i
n
e
4
P
a
r
t
2
:
T
l
i
n
e
3
P
a
r
t
3
:
T
l
i
n
e
6
Timed
Breaker
Logic
Closed@t0
BRKdc
P
a
r
t
3
:
T
l
i
n
e
5
Figure 5.4: ENI circuit in Part1.
37
Part1:Tline0
Tline3
Tline4
12
detailed
arm
36 sms
etop
NV
ebot
detailed
arm
36 sms
etop
NV
ebot
Figure 5.5: ENI circuit in Part2.
The ENI approach also raises a new restriction for the simulation step-time.
Since the transmission line is the bridge to connect different pieces, the ”signal
traveling time” needs to be taken into account. PSCAD/EMTDC requires the
simulation step to be equal or smaller than 10% of the ”signal traveling time”.
The capacitive reactance XC of the transmission line can be calculated to avoid
the ”signal traveling time” issue using the following equation:
TS =√CL
where C and L are the capacitance and the inductance of the transmission line,
TS is the maximum simulation time step.
In PSCAD/EMTDC, the transmission line can be set in the ”Bergeron
Mode” to avoid the soil and the transmission tower configuration. Afterward,
using ”Manual Entry of X, Y”, the R(Ω/m), XL(Ω/m), XC(MΩ ∗m) param-
eters are set. To make the transmission line equal to an inductor, it requires
R=0 and XC→ ∞. However, according to the equation of the time step, the
38
XC is dependent on the XL. This will influence the simulation results, it will be
shown in Section 6.
39
6. Simulation results
Three test cases are built to evaluate the ENI multi-core approach. The
first two test cases include simulations for the single-core average model, the
single-core detailed model and the eight-core detailed model. The third test
case includes simulations for the eight-core detailed model for different number
of SMs per arm.
The simulation results will include the active and reactive power for both
MMC converters, the DC link voltage and the synthesized voltage. Some SM
voltages will also be shown in the detailed model simulation.
6.1 Test case 1
The first test case uses the references as:
• DC link voltage reference, Vdcref=400 kV,
• WEST MMC active and reactive power reference, PWref=60 MW, QWref=0
MVar,
• EAST MMC reactive power reference, QEref=10 MVar.
6.1.1 Average model test in the one-core CPU environment
Figure 6.1 shows the active and the reactive power of the WEST MMC.
Figure 6.2 shows the active and reactive power of the EAST MMC. Figure 6.3
shows the DC link voltage. Figure 6.4 shows the synthesized voltage.
40
Figure 6.1: WEST MMC active power and reactive power.
Figure 6.2: EAST MMC active power and reactive power.
Figure 6.3: DC link Voltage.
41
Figure 6.4: Synthesized voltage Va Vb Vc.
6.1.2 Detailed model test in the one-core CPU environment
Figure 6.5 shows the active and reactive power of the WEST MMC. Figure
6.6 shows the active and reactive power of the EAST MMC. Figure 6.7 shows
the DC link voltage. Figure 6.8 shows the synthesized voltage.
Figure 6.5: WEST MMC active power and reactive power.
42
Figure 6.6: EAST MMC active power and reactive power.
Figure 6.7: DC link Voltage.
Figure 6.8: Synthesized voltage Va Vb Vc.
43
6.1.3 Detailed model test in the eight-core CPU environment
Figure 6.9 shows the active and reactive power of the WEST MMC. Figure
6.10 shows the active and reactive power of the EAST MMC. Figure 6.11 shows
the DC link voltage. Figure 6.12 shows the synthesized voltage.
Figure 6.9: WEST MMC active power and reactive power.
Figure 6.10: EAST MMC active power and reactive power.
44
Figure 6.11: DC link Voltage.
Figure 6.12: Synthesized voltages Va Vb Vc.
In an arm of the multi-core detailed model, 12 SMs voltage are randomly
selected as shown in Figure 6.13. They are almost overlapping, which shows the
sorting process is working well.
45
Figure 6.13: Voltage of 12 SMs.
6.2 Test case 2
The second test case uses the references as:
• DC link voltage reference, Vdcref=400 kV,
• WEST MMC active and reactive power reference, PWref=40 MW, QWref=-
10 MVar,
• EAST MMC reactive power reference, QEref=20 MVar.
6.2.1 Average model test in the one-core CPU environment
Figure 6.14 shows the active and the reactive power of the WEST MMC.
Figure 6.15 shows the active and reactive power of the EAST MMC. Figure 6.16
shows the DC link voltage. Figure 6.17 shows the synthesized voltage.
46
Figure 6.14: WEST MMC active power and reactive power.
Figure 6.15: EAST MMC active power and reactive power.
Figure 6.16: DC link Voltage.
47
Figure 6.17: Synthesized voltage Va Vb Vc.
6.2.2 Detailed model test in the one-core CPU environment
Figure 6.18 shows the active and reactive power of the WEST MMC. Figure
6.19 shows the active and reactive power of the EAST MMC. Figure 6.20 shows
the DC link voltage. Figure 6.21 shows the synthesized voltage.
Figure 6.18: WEST MMC active power and reactive power.
48
Figure 6.19: EAST MMC active power and reactive power.
Figure 6.20: DC link Voltage.
Figure 6.21: Synthesized voltage Va Vb Vc.
49
6.2.3 Detailed model test in the eight-core CPU environment
Figure 6.22 shows the active and reactive power of the WEST MMC. Figure
6.23 shows the active and reactive power of the EAST MMC. Figure 6.24 shows
the DC link voltage. Figure 6.25 shows the synthesized voltage.
Figure 6.22: WEST MMC active power and reactive power.
Figure 6.23: EAST MMC active power and reactive power.
50
Figure 6.24: DC link Voltage.
Figure 6.25: Synthesized voltages Va Vb Vc.
6.3 Test case 3
In test case 3, only the multi-core models are tested. The simulation result
of the synthesized voltage with different number of SMs, (Nsm=36, Nsm=108)
are as shown in Figure 6.26 and Figure 6.27.
51
Figure 6.26: Synthesized voltages Va Vb Vc(Nsm=36).
Figure 6.27: Synthesized voltages Va Vb Vc(Nsm=108).
It is worth noting that as the number of the SMs per arm increases, the bad
effect from the ENI approach decreases.
6.4 Comparative evaluation
From the simulations, the results show that:
• The active and reactive power of both WEST and EAST MMC in all tests
meet the references at steady state.
52
• The synthesized voltage of the multi-core model contains some noise not
seen in the one-core models.
• The DC voltage in the multi-core model contains noise as well.
• The noise in the multi-core model decreases when the number of SMs per
arm gains.
The source of this noise is the ENI bridge, transmission line. Since trans-
mission line and cable are the only available bridge for the ENI approach, the
best way to split system is replacing inductors by transmission lines. Since the
transmission line can be treated as a series connection of π-structures, as shown
in Figure 6.28, the shorter the length is, the less π-structures will exist. Even
though the length of every transmission line is set as 1 m, the noise still exists.
This is the downside of the ENI approach. This drawback of the ENI approach
is decreased as the number of levels increases.
RL
C C C C
L R
Figure 6.28: Transmission line and π-structure.
6.5 Simulation speed versus SMs number
The main contribution of this thesis is speeding up the simulations. Accord-
ing to [10] [16] [21], the typical detailed MMC model simulation with a large
number of SMs is slow. A table of simulation time versus SMs number per arm
53
is summarized in the Table 6.1 in the single-core CPU environment. It shows
how much time it will take to finish 1 s simulation.
Table 6.1: Simulation time versus Submodule number on each arm.
Arm SMs number 14 16 18 20 22 24
Simulation time(s) 232 392 541 710 902 1044
Arm SMs number 26 28 30 32 34 36
Simulation time(s) 1424 1693 2520 2848 3086 4084
A quadratic curve fit for the data in Figure 6.29 is obtained using the ”basic
fitting” tool by MATLAB. The equation of simulation time versus SMs number
per arm is:
T = 6.9N2 − 180N + 1500
Note that if the number of the SMs per arm is 200, it will take 86400s to
finish 1s duration of run. For the test cases (with 36 SMs per arm), it only takes
94.4 s to simulate one second with the multi-core approach vs. 4048 s reported
in the literature for a single-core architecture. This is a simulation speed gain
of 43 times.
54
10 15 20 25 30 35 400
1000
2000
3000
4000
5000
6000
SMs number per arm
Sim
ulat
ion
time
for
1 se
c du
ratio
n
Simulation time respect to SMs number per arm
y = 6.9*x2 - 1.8e+02*x + 1.5e+03
data 1
quadratic
Figure 6.29: Simulation time curve.
55
7. Conclusions
An HVDC system based on MMC topology has been modeled to one average
and two detailed models and simulated in a single-core and a multi-core environ-
ment. The performance of three sorting algorithms are evaluated by MATLAB
and PSCAD/EMTDC.
The simulation speed has been greatly improved with the help of selected
sorting algorithm and the ENI approach. Compared to the average model,
the detailed model can show more information such as the submodule voltage
profiles. The approach in a multi-core environment makes it possible to simulate
a large system in the detailed model within a reasonable time frame.
In the ENI approach, inductors are replaced by the transmission line models.
This approximation introduces noise on the DC link and synthesized voltage.
This seems to be a huge problem to the detailed model with 36 submodules in
each arm. However, in the real MMC-HVDC technology projects, it usually has
more than 200 submodules in each arm, and the introduced noise will decrease
as the submodules number increases.
Therefore, the ENI approach in a multi-core environment can accelerate the
simulation significantly, and it will be effective for MMC simulations with a high
number of submodules.
56
8. Future work
In the future, the following work may be done:
• More comparisons: The circulating current effects can be analyzed.
• ENI bridge: In the future, it can be improved if the inductor substitution
is better.
• Optimal way of splitting: The original project has been split by assumed
model branch computational equality, there could be better ways to split
the system to maximize the CPU usage. One possible approach to do this
could be to use the software VTune to analyze CPU usage.
57
REFERENCES
[1] M. Davies, M. Dommaschk, J. Dorn, J. Lang, D. Retzmann, and D. So-erangr. HVDC PLUS–Basics and principle of operation. Siemens EnergySector, ET PS SL/DSoe/Re-2008-08-10-HVDC PLUS V, 3, 2008.
[2] B. Gemmell, J. Dorn, D. Retzmann, and D. Soerangr. Prospects of multi-level VSC technologies for power transmission. In T&D Conf. and Expo.,2008. T. D. IEEE/PES, pages 1–16, Apr. 2008.
[3] T. Westerweller, K. Friedrich, U. Armonies, A. Orini, D. Parquet, andS. Wehn. Transbay cable–Worlds first HVDC system using multilevelvoltage–sourced converter.
[4] Siemens. HVDC Plus References. [Online] Available:http://www.energy.siemens.com/us, 2013.
[5] B. Jacobson, P. Karlsson, G. Asplund, L. Harnefors, and T. Jonsson. VSC–HVDC transmission with cascaded two–level converters. In CIGRE session,pages B4–B110, 2010.
[6] J. Arrillaga, Y. H. Liu, and N. R. Watson. Flexible Power Transmission:The HVDC Options. John Wiley & Sons, Inc., 2007.
[7] N. Flourentzou, V. G. Agelidis, and G. D. Demetriades. VSC–Based HVDCPower Transmission Systems: An Overview. IEEE Trans. Power Electron.,24(3):592–602, Mar. 2009.
[8] A. Antonopoulos, L. Angquist, and H-P. Nee. On dynamics and voltagecontrol of the modular multilevel converter. In 13th European Conf. onPower Electron. and Applicat., pages 1–10, 2009.
[9] S. Rohner, S. Bernet, M. Hiller, and R. Sommer. Modulation, losses, andsemiconductor requirements of modular multilevel converters. IEEE Trans.Ind. Electron., 57(8):2633–2642, Aug. 2010.
[10] X. Jianzhong, Z. Chengyong, L. Wenjing, and G. Chunyi. Acceleratedmodel of modular multilevel converters in PSCAD/EMTDC. IEEE Trans.Power Del., 28(1):129–136, 2013.
58
[11] G. Bergna, E. Berne, P. Egrot, P. Lefranc, A. Arzande, J. C. Vannier,and M. Molinas. An energy–based controller for HVDC modular multi-level converter in decoupled double synchronous reference frame for voltageoscillation reduction. IEEE Trans. Ind. Electron., 60(6):2360–2371, Jun.2013.
[12] J. Peralta, H. Saad, S. Dennetiere, J. Mahseredjian, and S. Nguefeu. De-tailed and averaged models for a 401–level MMC–HVDC system. IEEETrans. Power Del., 27(3):1501–1508, 2012.
[13] G. Minyuan, X. Zheng, and C. Hairong. Control and modulation strate-gies for modular multilevel converter based HVDC system. In IEEE Ind.Electron. Soc. Annu. Conf., pages 849–854, 2011.
[14] P. Sotoodeh and R. D. Miller. A new multi–level inverter with FACTScapabilities for wind applications. In IEEE Green Technologies Conf., pages271–276, Apr. 2013.
[15] M. Saeedifard and R. Iravani. Dynamic performance of a modular multilevelback–to–back HVDC system. IEEE Trans. Power Del., 25(4):2903–2912,Oct. 2010.
[16] U. N. Gnanarathna, A. M. Gole, and R. P. Jayasinghe. Efficient modeling ofmodular multilevel HVDC converters (MMC) on electromagnetic transientsimulation programs. IEEE Trans. Power Del., 26(1):316–324, 2011.
[17] Algorithms and Data Structures Slection Sort. [Online] Available:http://www.algolist.net/Algorithms.
[18] D. Knuth. The Art of Computer Programming 3 (2nd ed.). Addison–Wesley, 1998.
[19] B. Jon. Programming Pearls. Addison–Wesley Professional, 1999.
[20] R. Miller and L. Boxer. Algorithms sequential & parallel: a unified ap-proach.
[21] F. Yu, W. Lin, X. Wang, and D. Xie. Fast voltage–balancing control andfast numerical simulation model for the modular multilevel converter. IEEETrans. Power Del., 30(1):220–228, Feb. 2015.
[22] P. Le–Huy, P. Giroux, and J. C. Soumagne. Real–time simulation of mod-ular multilevel converters for network integration studies. In Proc. IPST,2011.
59
APPENDIX A. FORTRAN codes for the detailed model
In this chapter, the algorithm of sorting is shown. The codes are pro-
grammed in the FORTRAN language, which can be directly compiled by the
PSCAD. Instead of injecting C file or Matlab file, the FORTRAN approach ap-
pears to be the best choice, as for saving the simulation time. Here is the code
using InsertionSort in PSCAD.
#LOCAL real A
#LOCAL real B
#LOCAL real clmfst(36)
#LOCAL real clmscd(36)
#LOCAL integer tri
!CHECK IF N CHANGE
!---STORAGE MATRIX-----!
!---INITIAL ORIGINAL MATRIX 2ND CLO WITH LABELS---!
DO I=1,36
clmscd(I)=I
END DO
!---INITIAL ORIGINAL MATRIX 1ST CLO WITH VOLTAGES---!
DO J=1,36
clmfst(J)=$IN(J)
60
END DO
!---SORT MATRIX ROWS BASED ON 1ST CLO VALUES IN ASENDING SEQUENCE---!
DO I=1,36
DO J=(I+1),36
IF (clmfst(J).LT.clmfst(I)) THEN
A=clmfst(J)
clmfst(J)=clmfst(I)
clmfst(I)=A
B=clmscd(J)
clmscd(J)=clmscd(I)
clmscd(I)=B
END IF
END DO
END DO
!---GIVE OUT WITH SORTED LABELS---!
DO I=1,36
$OUT(I)=clmscd(I)
END DO
tri=0
!---GIVE T WITH 1/0 BASED ON NUMBER OF ON/OFF CAPS-N AND CURRENT DIRECTION-ID---!