-1- A Switch-Utilization-Improved Switched-Inductor Switched- Capacitor Converter with Adapting Stage Number (Short title: A Switch-Utilization-Improved SISCC with Adapting Stage Number ) Yuen-Haw Chang [email protected](corresponding author), Yu-Jhang Chen [email protected]Department of Computer Science and Information Engineering, Chaoyang University of Technology, 168, Jifong E. Rd., Wufong, Taichung, Taiwan, R.O.C. (Post Code: 413), Tel: 886-4-2332-3000 ext.4411 Fax: 886-4-23742375
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A Switch-Utilization-Improved Switched-Inductor Switched-Capacitor Converter with Adapting Stage Number
(Short title: A Switch-Utilization-Improved SISCC with Adapting Stage Number)
Next, via replacing the Thevenin’s equivalence of (1) into the SISCC, the overall topologies for the PWM-ON and
PWM-OFF periods can be obtained as in Fig. 4(a) and 4(b), respectively. Based on the topologies, the relevant
dynamic equations are derived as follows.
(i) PWM-ON period: within STD (Fig. 4(a))
openA 1)()]([ V
Lti
LR
dttid
LL , (2a)
dBBB
1)(1)()]([
VRC
tvRC
tvRC
mdt
tvd
oC
oC
o
cCLo
o , (2b)
dBBB
1111)()]([
VRC
vRRC
tvRC
mdt
tvd
LC
LLCo
L
cCL
L
, (2c)
)()(o tvtv LC , )()(S titi L , (2d,e)
(ii) PWM-OFF period: within STD )1( (Fig. 4(b))
dopenC 11)(1)()]([ V
LV
Ltv
Lti
LR
dttid
oCLL , (3a)
)(1)]([ti
Cmdttvd
Loc
Co , (3b)
LL
CLL
C vRCdt
tvd
1)]([, (3c)
)()(o tvtv LC , )()(S titi L , (3d,e)
where TL rrrR openA , CcTc rmrmR )1(B , cCL mrrrR openC are the parasitic resistances,
)(o tv is the output voltage, and )(S ti is the current passing through openV . Again by using SSA technique, the state
equation of ASN-based SISCC can be derived as: ( )'( means dtd )( )
)()()( tuBtxAtx nn , (4a) )()( txCty n , (4b)
where TCCL tvtvtitx L )()()()( o , TVVtu dopen)( , Ttitvty )()()( So , (5a,b,c)
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LLL
c
oo
c
ocn
RRD
CRCDm
RCD
RCDm
CmD
LD
LR
A
110
1
01
BB
BB
D
,
B
B
0
0
11
RCDm
RCDLD
LB
L
co
n,
001100
nC , (5d,e,f)
cCTL mrDrDrrR )1(openD . (5g)
4. Analysis and Design of ASN-Based SISCC
4.1 Conversion Ratio and Power Efficiency:
By substituting 0)( tx of (4), the steady-state output voltage oV , output current oI , and supply-terminal
current SI can be obtained as:
L
cccnnn RR
VmmDxDVxDnnD
muBACVo
dS1o 1
])1()1([])1[(1
1
, LR
VI oo , (6a,b)
L
cc
L
cnnn RR
VmmDxDVxDnn
RDmuBACI
o
dS2
21
S 1])1()1([])1[(
)1(
2
, (6c)
where
2D
2B
)1( DRm
DR
R co
, (7a)
1001 nC , 0012 nC . (7b,c)
From (6a), it is obvious that oV can be regulated by duty cycle D , and then the step-up voltage conversion ratio is
suggested as
L
cccn R
Rn
kmmDxDxDnD
mnVVM o
S
o 11
)1()1(11
)1( , (8)
where SVVk d is the ratio of dV to SV . When V5S V and V2.0d V , the ratio is 04.0d SVVk . For
example, 04.0k , 2.0x , and CTL rrR , ( LR is in -level, and CT rr , is in m -level, i.e. oL RR ),
nM is really close to the theoretical value of )1()1( Dmn c , cnn 2,...,,1,0 . Thus, the ideal maximum gain is
)1()1( Dmn cc . For nominal conditions, the maximum attainable value of oV is S)1()1( VDmn c
minus voltage drops in the charging or discharging circuits. Next, according to Fig. 4, the input and output power can
be computed as
SopeniP IV , LRV 2ooP . (9a,b)
According to (9) plus (6) and (1a), the power efficiency of ASN-based SISCC is derived as in (10). Clearly, n is
rising when oV (i.e. refV ) is closer to S)1()1( VDmn c .
S
oSo
i
o)1()1(
1)(1
1
1)1(P
PVDmn
V
nxDkn
Dmn
VV
ccn
. (10)
Here, let's discuss the benefit to switch utilization and supply range by using ASN. For example, SV = 5V ,
refV = 50V , and the total step-up gain is 10550Sref VV . If 0n , D ∵will be 0.8 for this gain ( step-up
gain 10)8.01(2)10( ). If 1n , D ∵will be 0.6 ( step-up gain 10)6.01(2)11( ). If 2n is
adapted, then D needs just ∵0.4. ( step-up gain 10)4.01(2)12( ). Obviously, based on ASN, n
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( cnn 2,...,,1,0 ) can be adapted according to SV and refV to use a smaller duty cycle D for the higher switch
utilization. Besides, the range of the total gain can be extended with ASN. It is helpful that the SISCC has the wider
range of supply SV when refV is given. For example, assume that SV is V5 normally and decreasing along with
time, oV (i.e. refV ) is desired at 50V , 2cm , 04.0k , 2.0x , and 82.0~10.0D ( 1.0min D ). If 0n ,
SV needs V5.4 at least or above. If 1n , SV needs V25.2 or above. If 2n is adapted, the SISCC will still
work as SV needs just V5.1 or above. The range of supply voltage becomes wider by using ASN. Certainly, ones
might pay a price of power consumption due to using the bigger stage number of the front-stage SC.
4.2 Inductance/Capacitance Selection:
(i) Selection of inductor L :
Based on the theoretical waveform of inductor current of Fig.2, plus the topologies of Fig. 3(a)-(c), the
relationship of Phase I, II, III referring to the inductance can be simplified and presented as:
SDTxV
IILt
S
121 , SDTx
VnIILt
)1(
)1( S
232 , STD
VnVIILt )1(
)1( So
133
. (11a,b,c)
By adding (11a), (11b), and (11c), the sum of the three phase cycles is obtained as
SS f
TnxnDV
ILttt 1)1(
1
S321
, (12)
where 13 III is denoted by the current swing of inductor L . According to (12), the minimum inductance for a
current swing I can be estimated as in (13). Certainly, if ones desire a smaller I , the inductor L will be larger,
but it is improved by increasing Sf .
IfnxnDVLL
S
)1(S
min . (13)
(ii) Selection of pumping capacitor C :
Based on the topology of Phase I as in Fig. 3(a), 1 must be smaller than SDTx for the fast response, where
1 is the time constant of charging these pumping capacitors from supply SV , and the inequality is presented as in
(14). Obviously, C should be selected as smaller for the fast boosting response of the front-stage SC.
Sc
T DTxnrrCn )(1 . (14)
(iii) Selection of filter capacitor LC :
As in Fig. 2, ov decays from o,1V to o,2V exponentially in Phase II, and then decays from o,2V to o,3V
exponentially in Phase III. Thus, ov can be modeled as
III] [Phase )1(0 , II] [Phase )1(0 ,
)(3
2
o,2
o,1o
St
St
TDteVDTxteV
tv
, (15)
where 2)1(o,1o,2
SDTxeVV , 3)1(o,2o,3
STDeVV , and the discharging time constants of Phase II and III are
)(2 coLL mCCR , LL CR 3 , respectively. So, the voltage ripples can be defined as
]1[ 2)1(o,1o,2o,1IIo,
SDTxeVVVV , (16a)
]1[ 3)1(o,2o,3o,2IIIo,
STDeVVVV . (16b) By using (15)-(16), plus assuming oL CC , the averaged output voltage can be derived as
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oS
LL
c
oL
S
LTxD
SV
TxDCRV
mCVVC
TxDRdttv
TxDV S
)1()1( )(
)1(1
IIIIIo,IIo,)1(
0 oo , (17)
where IIIo,IIo, VVVo is the total swing of output voltage. Then, the ripple percentage can be presented as
LLSLL
SCRf
xDCR
TxDVVrp
1)1(
o
o . (18)
Clearly, rp is worse while the loading is heavier, but it is improved by increasing Sf or LC . When the converter
is unloaded, rp is almost zero. For a desired ripple pr~ , the filter capacitor is estimated as
prRfxDCCLS
LL ~1
min,
. (19)
4.3 Stability and PWM Control:
As in (5d), the system matrix nA is divided into four sub-matrices 11nA , 12
nA , 21nA , 22
nA , and then can be
decomposed as in (20a), where diagonal matrix n is computed as in (20b). Obviously, n represents one of the
characteristic roots of SISCC.
IAAIA
IAAI
AAAAA nn
n
n
nnnn
nnn
0000 1211111
111212221
1211, (20a)
oLLnnnnn RRC
AAAA 111 121112122 . (20b)
Based on this n , plus taking the resonant capacitor )()1( 2D
2 RmDLC co , the characteristic equation of the
open-loop SISCC can be decomposed approximately as in (21), and then the characteristic roots 1p , 2p , 3p can be
obtained as in (22).
0)1( )1(
1)||(
1321
B
2
B2
D2
B
D2
pspsps
RLCmRDDs
RDDRm
RCRCDm
LRs
RRCsAsI(s)
oc
oc
oLo
c
oLLn , (21)
where
)||(1
1oLL RRC
p , (22a)
)1()1(
141
)1(1
21,
B
22
B2
D2
B
D
B2
D2
B
D32 RLCm
RDDRD
DRmRCRC
DmL
RRD
DRmRCRC
DmL
Rppoc
oc
oLo
cc
oLo
c
, when 2
D
2)1(Rm
DLCc
o
. (22b)
Obviously, the three different real roots: 1p , 2p , 3p are all located in the left half of s-plane. Hence, the open-loop
SISCC has an inherent good stability. Further, based on (8), LR is much larger than oR for the better voltage
conversion ratio, i.e. BRRR oL (10 times larger or above). Based on (19), LC is taken as larger for the
smaller output ripple. In general, LC is times larger than oC , i.e. oL CC . Because BoL RRR and
oL CC , it concludes that 321 , ppp , i.e. 1p is at least 10 times smaller than 32 , pp . Thus, 1p as in
(22a) is the dominant pole of SISCC, and its first-order approximation will be applied for the PWM control design.
As controller in Fig. 1, oV is fed back into LPF for noise rejection, where L is a cut-off frequency chosen
based on what range the noises occur at. To avoid affecting system response, L is taken as bigger than the inverse
value of dominant pole 1p ( 11 pL ). Fig. 5 shows the closed-loop control diagram of ASN-based SISCC. If SV
or LR is decreasing (source/loading variation), based on (6a), then oV will be going down. The error e between
refV and oV is rising quickly. The bigger e makes a larger duty cycle D via PK (proportional gain of PWM
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control), and then this D will drive oV to keep following refV . The capability of output regulation (line/load
regularity) is enhanced. Next, the design of PK is discussed. Assume that the SISCC is running around a duty cycle
oDD for refo VV . With the help of taking these small k and x , oV of (6a) can be simplified as
Loo
cRRD
VmnV
1
11
)1( So , for oDD . (23)
If a small duty-cycle variation d occurs, the output voltage for dDD o has a small change ov as
Loo
ScRRdD
VmnvV
11
)(1)1(oo , for dDD o . (24)
By subtracting (23) from (24), and then combining the dominant pole 1p , the small-signal output voltage can be
expressed with the s-domain first-order approximated model as:
)(1
11
1)1(
)1()(1
2S
o sdsRRD
VmnsvLoo
c
, (25)
where )||(1 11 oLL RRCp is the small-signal time constant of SISCC. When we consider the response just at the
frequency lower than L of LPF, based on Fig. 5 plus (25), the closed-loop characteristic equation is derived as
01
11
1)1(
)1(1)(1)(
12
sRRDVmn
KsHsLoo
ScPc
. (26)
The closed-loop settling time St within a settling error of %5 is obtained as
Loo
ScPS RRD
VmnKt1
1)1(
)1(13 21 . (27)
For keeping St shorter than a desired settling time St~ , the minimum gain of PK can be designed as
1~3
)1()()1( 1
2
SLSc
oLoP tRVmn
RRDK , cnn 2,...,,1,0 . (28)
Next, let the phase margin be higher than some desired d as dgjHPM )(180 , where g is the gain-
crossover frequency of )(sH (i.e. 1)( gjH ). So, g is obtained as
11
1)1(
)1(12
21
Loo
ScPg RRD
VmnK
. (29)
By substituting (29) into the PM inequality, the maximum gain of PK for d can be derived as
)sec()1(
)()1( 2
dLSc
oLoP RVmn
RRDK
, cnn 2,...,,1,0 . (30)
5. Examples of ASN-Based SISCC
A closed-loop ASN-based SISCC ( 2,2 cc mn ) is simulated by OrCAD, and then its hardware circuit is
implemented and tested. Basically, the step-up conversion is to realize the gain of 2.16)63.01(2)12(
( 63.0D , 2.0x , 04.0k ), and then to boost the output voltage oV into V81 at most ( V5S V , 500LR ,
kHz100Sf ). By using (14), C is selected at F25 ( mrC 20 , mrT 30 ). According to (19), LC is
selected at F300 for the desired ripple %08.0~ pr . According to (13), L is designed as H47 for the current
swing A0.2I , and then following to take oC of F80 based on (22b). For noise rejection, L is taken by
about 1000Hz here. Based on (28),(30), plus the larger duty cycle running in the transient response, PK is basically
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designed at 0.003 for mstS 20~ , 20d . The simulation cases include: (i) steady-state response, and (ii)
source/loading variation. Besides, the hardware circuit of SISCC is realized as photo shown in Fig. 6. There are two
parts including: (i) power part of SISCC (right: cmcm 1014 ), (ii) ASN and PWM controller (left: cmcm 1014 ),
mainly implemented in the circle-marked chip (I.C. number: D35-101B-37e, TSMC 0.35μm 2P4M, size:
500μm×300μm, 12.2mW, max. frequency: 200kHz) via full-custom fabrication of National Chip Design and
Implementation Center (CIC), Taiwan. Fig. 7 shows the physical layout and wire-bonding diagrams of D35-101B-37e.
Finally, this hardware circuit is tested practically for the same cases.
Firstly, the simulation is discussed here. (i) Steady-state response: The SISCC is simulated for V80ref V , V75
respectively, and the waveforms of oV and the relevant ripples are shown as in Fig. 8(a)-(d). In Fig. 8(a) and 8(c), it
is found that the converter is stable to keep oV on following refV , and the settling time is shorter than ms20 . In Fig.
8(b) and 8(d), the output ripple percentage can be obtained as: %05.0rp . Also, the efficiencies are obtained as:
%4.89 %,9.88 , and the results can be verified by (10). Additionally, Fig. 8(e) deals with the steady-state
waveforms of duty cycle, capacitor voltage, and inductor current for V80ref V . (ii) Source/loading variation: [Case
I]: Assume supply source SV is V5 normally, and it suddenly has a voltage drop from V5 to V5.4 at ms60 .
After a short period, SV recovers from V5.4 to V5 at ms90 . Fig. 8(f) shows the waveform of oV while
5V4.5VV5S V , and it is found that oV has a very small drop of V05.0 at msms 90~60 . Obviously, the
closed-loop SISCC still can hold oV on following V80ref V in spite of the source variation. [Case II]: Assume
LR is 500 normally, and it suddenly changes from 500 to 250 (double loading) at ms60 . After a short
period, LR changes from 250 back to 500 at ms95 . Fig. 8(g) shows the waveform of oV while
LR = 500250500 , and it is found that oV has a very small drop of V02.0 at msms 95~60 . Clearly,
oV is still following V60ref V in spite of the loading variation. The results show that the converter has good
robustness to source/loading variation. Here, a remark is given about the switch utilization by using ASN. Fig. 9(a)
shows conversion ratio nM versus duty cycle D , and Fig. 9(b) shows switch utilization To PP versus duty cycle
D . When oV (i.e. refV ) is desired at 50V , the step-up gain is 10550Sref VV . As the bold line: 0n
shown in Fig. 9(a) (i.e. with no front-stage SC and ASN), D needs a high duty of 0.8 for this gain of 10, and the
switch utilization is %20To PP as in Fig. 9(b). As the dotted line: 1n , D needs 0.6 for this gain and
%40To PP . As the star line: 2n , D needs just a smaller duty of 0.4 for this same gain, and the switch
utilization can be improved to %60To PP . Thus, based on ASN control, n ( cnn 2,...,,1,0 ) can be adapted
according to SV and refV to obtain a properly small D for the higher switch utilization, i.e. reduce the voltage/
current stress on power switch.
Secondly, the experiment is discussed as follows. ( SV 5V , k5LR , kHz15Sf , tool: Agilent 54830B/
MS0-X 3052A oscilloscope, probe attenuation: 10x). (i) Steady-state response: The hardware of SISCC is tested for
V80ref V , V75 respectively, and the waveforms of oV and the relevant duty cycle are shown as in Fig. 10(a)-(d).
In Fig. 10(a) and 10(c), the output signal is measured at 8.019V , 7.505V respectively, i.e. oV has the steady-state
practical value of about 75.05V ,V19.80 , and is following 75V V,80ref V via the controller. In Fig. 10(b) and
10(d), the duty cycle is measured at 0.633 , 0.604 respectively for two different V80ref V , V75 . Also, the ripples
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and efficiencies are measured as %96.0%,25.1rp , %2.87%,3.84 . (ii) Source/loading variation: [Case I]:
Assume SV suddenly changes from normal V5 down to V5.4 , and after a short period SV recovers from V5.4
to V5 . Fig. 10(e) shows the waveform of oV while 5V4.5VV5S V . It is found that oV has a very small
drop, but the closed-loop SISCC still can hold oV on following V80ref V . [Case II]: The SISCC hardware is
tested for loading variation. Fig. 10(f) shows the total waveform of oV when the same load is added in parallel and
then the added load is removed after about sec5.3 ( V60ref V ). Obviously, oV has an abrupt drop while the same
load is added in, and has an abrupt jump while the added load is removed, but oV is still following V60ref V for
achieving the output regulation.
6. Conclusions
This paper presents the analysis, design and implementation of a closed-loop ASN-based SISCC for the step-up
DC-DC conversion & regulation. The power part of SISCC consists of two cascaded sub-circuits: a serial-parallel SC
circuit with cn pumping capacitors and a SI booster with cm resonant capacitors, so as to obtain a high step-up
gain of )1()1( Dmn cc at most, where D is the duty cycle of PWM. Further, the ASN control is presented
with adapting the stage number n ( cnn 2,...,,1,0 ) of the front-stage capacitors to realize a flexible gain of
)1()1( Dmn c , and then according to SV and refV so as to obtain a properly small duty cycle D for
improving switch utilization and/or supply voltage range. The control part consists of ASN decision, ASN phase
generator and PWM compensator, mainly implemented in the chip via full-custom fabrication (TSMC 0.35μm 2P4M).
The advantages of the proposed scheme are listed as follows. (i) As the example said, the step-up gain of 16.2 or
higher can be achieved just with one inductor, four switches and five capacitors. Thus, this scheme can provide the
high step-up gain under the fewer component count, or under a compromise among volume size, component count,
and voltage gain. (ii) For the higher step-up gain required, it can be realized easily by extending the stage number of
pumping capacitors. (iii) Since the dominant pole of SISCC is in the left half of s-plane, this scheme has an inherent
good local stability. (iv) The ASN control is presented here with adapting the stage number n ( cnn 2,...,,1,0 ) to
realize a flexible step-up gain according to SV and refV so as to obtain a properly small duty cycle D for
improving switch utilization and/or supply voltage range. (v) The PWM technique is adopted here not only to enhance
output regulation capability for the different desired outputs, but also to reinforce the output robustness against
source/loading variation.
Acknowledgment This research of converter circuit theory and application is financially supported by Ministry of Science and
Technology of Taiwan, R.O.C., under Grant MOST 103-2221-E-324-039.
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Fig. 1. Configuration of ASN-based SISCC.
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Fig. 2 Theoretical waveforms of SISCC.
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(a)
(b)
(c)
Fig. 3. Topologies of SISCC in (a) Phase I, (b) Phase II, (c) Phase III.
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(a)
(b)
Fig. 4 Equivalent circuits in the period of (a) PWM-ON (b) PWM-OFF.