A SINGLE STAGE FULL BRIDGE POWER FACTOR CORRECTED AC/DC CONVERTER Nasser Ismail A Thesis in The Department of Electrical and Computer Engineering Presented in Partial Fulfillment of the Requirements for the Degree of Master of Applied Science at Concordia University Montreal, Quebec, Canada November, 1996 @Nasser IsmaiI, 1996
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A SINGLE STAGE FULL BRIDGE POWER FACTOR
CORRECTED AC/DC CONVERTER
Nasser Ismail
A Thesis
in
The Department
of
Electrical and Computer Engineering
Presented in Partial Fulfillment of the Requirements for the Degree of Master of Applied Science at
Concordia University Montreal, Quebec, Canada
November, 1996
@Nasser IsmaiI, 1996
7 of Canada du Canada
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ABSTRACT
A Single Stage Full Bridge Power Factor Corrected
AC/DC Converter
Nasser Isrnail
Conventional single phase AC/DC converters use a two stage power configuration
to provide a regulated DC power supply at high input power factor. Elhination of one of
these stages cm reduce the cost, weight, size, complexity and increase the overall
reliability of this converter. This thesis proposes a single stage power factor correction
converter circuit. This proposed converter circuit uses the traditional non-power-factor
corrected circuit configuration with only few additional components. These are: an
additional winding on the high fiequency transformer, a small high fiequency inductor
and three diodes. The topology allows the output voltage regdation and input curent
shaping with a single power processing stage and one control chip. In addition, it is
shown that this converter can be designed to offer soft switching of the full bridge
switches. The operating principles of the proposed converter are discussed and its
performance characteristics under steady state conditions are examined. A design
procedure is illustrated to select the components of the converter for a 500 W power
supply operating at 50 kHz. Theoretical results are verified with simulation and
experimental tests on a 500 W laboratory prototype.
The author would iike to express his deep gratitude to Professor Praveen Jain for
his invaluable guidance, advice and financial support throughout al1 stages of this thesis.
The Experimental work reported in this thesis was performed at Nortel
Technologies in Ottawa. The author would like to thank Mr. H. Soin and D. Barmard of
Nortel for their invaluable help in conducting the experirnentai work.
The author also wishes to thank ail his colleagues in the Power Electronics
Laboratory at Concordia University, particularly Jose Espinoza, Manu Sain and Randy
Lee for their help.
The hancial support of the National Science and Engineering Research Council
(NSERC) and Nortel Technologies is greatfuly acknowledged.
Finally, the author wouid Iike to thank ail his fiends and family members for their
support and help.
TABLE OF CONTENTS
Page
List of Figures ......................................................... ... ... .......... List of Acronyms ...................................... ..................................................... xm
List of Principal Symbols ................................................................................................. xiv
CHAPTER 1 . INTRODUCTION
..... ............................-...........*................. f .f . General Introduction ...,............... 2
............................................................ ............. 1.2. Literature Review ..................... 3
1.3. Thesis Objectives and Scope ...................... ... .............................................. 6
CKAPTER 2 . CIRCUIT DESCRIPTION AND MODES OF OPERATION
Mode 4: Zero Prirnary Cwrent ................................................................. 21
Mode 6 : Linear Current Ramping ........................................................... 23
.................................................. ........... Mode 7 : Lefi Leg Transition .. -24
Mode 8 : t'[ta, t& QI tum on ....................... .......... ................................ 25
.................................................... Current Through the Auxiliary hductor 26
CHAPTER 3
Fig . 3.1
Fig . 3.2
Fig . 3.3
Fig . 3.4
Fig . 3.5
Fig . 3.6
Fig . 3.7
Fig . 3.8
Fig . 3.9
. . A d a r y Current Wavefom ..................................................................... 32
State One Equivalent Circuit- On Time .................................................... 33
.......................................... State one: a) Linear Rise of Auxiliary Current 34
............................................ Power T rade r to the Load ............... ,.., 35
.......................................... Output Filter hductor and Capacitor Currents 36
................................................... State Two Equivalent Simplifïed Circuit 38
State Three: Zero Adiary Current .......................................... ... ......... 39
.................. ................. Dc Link Capacitor Current ............. 4 1
The Value of the Auxiliary Inductor for DEerent Switching Frequencies
.... .... ................ and input Voltage Levels .... .... .. .......... ................ Fig . 3.10 Bo~ndary of CCM and DCM for Fn=85-135 volts ... 44
............................ Fig . 3.1 1 Boundary of CCM and DCM for hn=176-266 volts 44
.... ..........*.... ..................... Fig . 3.12 Current through the Auxiliary Inductor ... .. -45
........... ........... Fig . 3.13 Input Curreat and A d i a r y Voltage Waveforms .... 3 0
......................................... Fig . 3.14 Curent through the Output Filter Components 54
CHAPTER 4
Fig . 4.1 Output Filter Current and Voltage Waveforms for Operation at the Edge of
................... COCM and DOCM ............... -2
..................................................... DC Link Capacitor Current for DOCM 67
Curent through the Output Filter Capacitor for DOCM ........................... 70
Fig . 4.2
Fig . 4.3
Fig . 4.4 Per Unit DC Link Voltage ......................................................................... 73
Fig . 4.5 Per Unit DC Link Capacitor RMS Current ................................................ 74
Fig . 4.6 Per Unit RMS Filter Capacitor Curent ..................................................... 74
.................................. Fig . 4.7 Per Unit Switch RMS Current ............................. .... 75
The circuit representing this topological mode of operation is shown in Fig 2.3.
During this mode: At tirne t = tl, Q3 is turned on and power is transferred to the secondary
winding as the diagonal pair of switches Q, and Qj are both conducting. The dc link
capacitor discharges during this mode as the current flows in the negative direction, and
the output inductor current reaches peak value at t = t2.
V aux
Fig. 2.2 Operathg Waveforms of the converter
Fig. 23 Mode 1, Power Transfer Cycle: Q, and Q are conducthg
Conducting Elements: QI, Q3, Del, Dauxl
Final Conditions:
The primary current is the sum of the reflected load current and the auxiliary
current Auxiliary current is Iinearly rising until it reaches its peak value. At the end of
this interval switch QI is tumed off at zero voltage.
2.4.2 MODE 2, Interval t = It,, t-1: Left l e Transition - - Mode 2 is s h o w in Fig. 2.4. When QI is turned off, the prirnary current, i,, starts
discharging C4 and charging CI in a linear fashion. At tirne t3, the voltage across Q4
reaches zero while the voltage across QI reaches Vdc. I f Q4 is tumed on &er t,, then it
will tum on at zero voltage, thus reducing the switching losses. The rate of discharge is
defined by the MOSFET capacitance and the primary current in the circuit. Thus, at
higher load currents it is easy to achieve ZVS. The magnetizing current is assumed to be
constant and very small and could be neglected duruig this interval as any change would
be a oegligible second-order effect. This mode ends when D4 startS conducting d e r vw
had reduced to zero voltage.
Conducting elements: Q3, CL, C4, Do,, Do2, Dauxl
Initial conditions: vdsl = vds3 = O
V & = v & = vdc
Final Conditions :
Fig. 2.4 Mode 2: lefi leg Transition
State Equations:
2.4.3 MODE 3. Interval t = Itx. t& Primarv and Secondaw Free-wheeling - -
This mode starts with v,, going to zero and D4 hinllng on. During this mode, the
primary current fiee-wheels through Q3 and D4. AU variables remain unchanged during
this interval. Switch Q, can be turned on at zero voltage at any tirne during this interval.
Turning Q4 on will divert the current fiom D4 to Q4. The voltage across the primary is
zero. The load current dso fiee-wheels through the shorted secondary winding. Fig. 2.5
demonstrates the events during this mode.
Conducting elements: Q , , D, / Q,, Do,, Do,, D,,
Initial conditions:
v,, = v,= V,and v,, = vM = O
Fig. 2.5 Mode 3: Primary fieewheeling
2.4.4 MODE 4. Interval t = 1 t t P r i m a r v X - - - is cI.,,aehPi.mng Cd, -
This mode starts when no switch is conductiag and primary voltage and current
are zero. The auxiliary current will charge the dc link capacitor. Secondary is
fieewheeling. Mode 4 is shown in Fig 2.6
2.4.5 Mode 5. Interval t = IL td: Turuine on O, at zero current - - -
At instant t = k, Q2 is tumed on at zero cunent as the curent ramps slowly due to
leakage and auxiliary inductance and the voltage across the drain to source of Q2 becomes
zero.
Fig. 2.6 Mode 4: Zero primary current
2.4.6 Mode 6. Interval t = WC. t,l: Power Cvcle, Linear Current Ram~ing - - During this mode, the primary current (i, ) fds down Linearly and goes negative.
Once the current reverses direction, (assuming Q4 has been tumed on by then) the circuit
remallis in this mode until the prUnary current can support the load current through Do,.
At this poinf DO2 tunis off, Qg and Qz conduct and the dc Link voltage appears across the
primary winding of the transformer. The circuit representing this mode is s h o w in Fig.
2.7
Final equations:
Fig. 2.7 Mode 6: Linear Current Ramping
2.4.7 Mode 7, Interval t = It,, kl: Transition of the left le. OA - - - tum off.
At instant t = t,, Qq is turned off at zero voltage, CI is discharged to zero volts and
C, is charged to Vdc. mer this instant Q, can be tumed on at zero voltage. Fig. 2.8 shows
the circuit during this mode of operation
Fig. 2.8 Mode 7, left leg transition
2.4.8 Mode 8. Interval t = [te. 61: QI turn on - - -
At instant t = te, QI is tumed on at ZV as Cl was M y discharged. Dl and Q2 are
conducting during this interval which is simiiar to mode 3. This mode is show in
Fig. 2.9.
Fig. 2.9 Mode 8 - t = [tg, b]
2.4.9 Mode 9. Interval t = lh,t& - - -0, tum o f f
At instant t = tio, switch Qz is tumed off at zero current (ZC). This mode is similar
to mode 4 with zero prhary current and auxiliary current charging the dc bus capacitor.
This mode ends when Q2 is tumed off and a complete cycle of operation ends at this
point.
2.5 Losses Durinp Switchina Operation
As was seen fiom the analysis of various modes of operation presented in section
2.3, the left leg switches are switched with zero voltage and those of the right leg with
zero current.
The peak auxiliary current plays an important role in zero voltage switching as
when one of the left leg switches tums off, its capacitor starts charging and the capacitor
of the other switch in the same leg starfs discharging. If the voltage becomes zero before
the switch is tumed on, then we achieve zero voltage switching, if not switching will be
with some losses.
The energy stored in the auxiliary and leakage inductors at the time when QI is
tumed off should be equd to or greater than the energy stored in the output capacitance of
the switch.
As the leakage inductance is very small compared to the auxiliary inductance, it is
ignored in later discussions. Also, as we consider the most severe conditions for
switchùig ( with maximum losses), which occur close to no load condition, the primary
current wiii be e q d to the aiollliary current.
The awiliary current is ac modulated, as show in Fig. 2.10, so at the beginning
of h e frequency it has smaller values.
Fig. 2.10 Curent through the auxiliary inductor
The instantaneous value of the auxiliary current in each n-th auxiliary current
period
where V k is the dc l h k voltage which appears across the primary and any switch of the
full bridge when it is off.
TL is the line frequency penod.
Ts is the a period of switching frequency, and - = is a period of the awciliary 2
current and equd to haif a switching penod.
The peak auxiliary current I,, is m e n as:
Replacing (c, + c') by CI and i, by i, in (2.7) yields
For known values of inductance, capacitance and dc luik voltage, the minimum
required current for M y discharging the capacitance is calculated as:
When the instantaneous value of the auxiliary current (i,J is less than iawmin for
the whole line period, then switching losses exist and are expressed as:
This is valid in case the auxiliary current is less than the minimum during the
whole line fiequency period, othenvise only a portion of these losses exist whenever
The value of the losses could be approximated by the following expression:
2.6 Conclusions
This chapter presented the topological modes of operation of the proposed
converter circuit. In each switching fiequency perïod, nine distinctive modes were
explained. It is noted that the lefi leg switches have ZV turn on and t u m off, a smail
snubber capacitor is added to achieve ZVS at tum off if the parasitic capacitance value is
not enough. Due to the presence of the auxiliary inductor, the right leg switches have a
natural ZCS at both turn on and turn off,
The following conclusions about the switcbg losses are made: when operating at
full load, the 11 2cv2 losses negligible, but at light loads these losses tend to increase
depending on the amount of peak energy stored in both the leakage and auxiliary
inductors, whether it is enough to discharge the switch output capacitance before it tums
on. This is the case for the left leg switches, but the nght leg switches always have
11 2cv2 losses.
CHAPTER 3
S T E M STATE ANALYSIS OF THE CIRCUIT
FOR CONTINüOUS OUTPUT CURRENT
3.1 Introduction
In this chapter steady state analysis of the single stage power factor corrected
converter described in chapter two is presented in detail. This analysis is important to
predict steady state performance and to develop necessary equations for the proper choice
of converter components.
The steady state analysis is carried out for continuous conduction mode of the
output filter inductor (COCM) and the discontinuous conduction mode of the awciliary
inductor (DACM).
The steady state analysis of this converter is more complicated than that of the
conventional converters due to the nature of current and voltage wavefoms. Some of
these waveforms have a switching frequency period (Ts = l/f,), while others have half
switching fiequency period (TJ2). This fact complicates the steady state analysis. For
example, to obtain the value of the RMS current through the auxiliary inductor, the area
under the I, curve in each cycle is found ( these wavefoms repeat in shape, but differ in
value or amplitude). Then al1 these areas are summed and averaged over the line
frequency and the square root is taken for this sum.
In this chapter the circuit equations are derived and used to describe the proposed
circuit. The schematic shown in Fig 2.1 represents the main power circuit. Simplified
equivalent circuits are used in the analysis as well. Section 3.2 presents the states
(intervals) o f operation. Section 3.3 shows how to find the tums ratio of the high
frequency transformer. In Section 3.4 modes of conduction of the auxiiiary current are
discussed and its value is found. In Section 3.5 DC Link voltage value is found as a
hct ion of duty ratio, output load and auxiliary inductance.
Performance characteristics of the converter such as RMS current through the
switches, RMS input current, dc link capacitor current, output filter capacitor RMS
current, input power factor, total hannonic distortion and the output current ripple are
developed in Section 3.6.
3.2 States of O~eration
The steady state anaiysis of the circuit is conducted using equivalent simplifïed
circuits and using the following simplifjhg assumptions:
(1) Magnetizing current is neglected due to the high value of rnagnetizing
inductance.
(2) The rectified line voltage 1 V, 1 is constant during the switching period.
(3) DC link voltage Vds is constant during a switching period.
Circuit operation is better descnbed in terms of the auxiiiary current waveform
during one cycle of operation, which is equal to half the switching period. The waveform
is shown in Fig. 3.1.
Fig. 3.1 Auxiliary Current wavefom
This waveform clearly shows three states or intervals of operation:
(1) State One: The on-tirne interval: Linear Rise of the Awiliary Current- bn
(2) State Two: The off-time interval: Linear fd of the Auxiiiary Current- bR
(3) State Three: The dead-band interval: Auxiliary current is zero- T,/2-(kn+brr)
3.2.1 State One: Auxüiarv Current iinearlv Rising
In this state current is rising as the net voltage across the inductor is positive. n ie
circuit representing this state is shown in Fig. 3.2. During this interval the operation of
the circuit is explained by the following events:
Fig. 3.2 State One Equivaient circuit- on t h e
a) Awciliary current increases linearly with the net positive voltage applied across Lw
equal to Iv,~ as shown in Fig. 3 -3.
Fig. 3 3 State one a) Linear Rise of Auxiliary Current
Applying KVL to Fig. 3.3 yields
V' =l&l+vaLOt-v* (3.2)
Assuming N,, = N,
In a power tramfer cycle, during tirst staie V, equals V,, and they cancel each
other as they have different signs, this yields
v ~ n a = lys1 (3 -3)
and the auxiliary current is:
b) Primary cunent is the sum of auxiliary current and load current reflected to the
Also the prirnary current is the sum of the auxiliary inductor current and the dc
link capacitor current:
. . zp =lot +ipir (3-6)
By equating the two expression for the primary current (3.5) and (3 -6)
r & f iM =IO +im
By eliminating i, fiom both sides, (3 -7) becomes
iCdc = Iot (3 -8)
This means that in this state the load draws the current fkom the dc link capacitor
C, and discharges it.
c) Power is transferred to the load as a voltage is applied across the primary. This voltage
is transferred to the secondary and then rectifïed. This mode is explained in Fig. 3.4 & 3.5
Fig. 3.4 State one c) Power transfer to the load
Fig. 3.5 Output filter inductor and capacitor currents
The duration of this penod is the duty cycle
3.2.2 State Two: Auxiliarv Current Linearlv decreasing
in this state auxiliary current is decreasing (fdling) as the net voltage across the
auxiliary inductor is negative. The auxiliary voltage is zero and the following events take
place:
a) The voltage across L, is negative dc voltage according to the following
considerations
The value of the dc link voltage which ensures the discontinuous operation for the
auxiliary inductor could be found as follows.
The peak value of the auxiiiary current is
AIso it codd be written as
The auxiliary current has to be discontinuous for proper operation of the circuit,
so the following relationship has to be satisfied:
and
The tirne scale is normaliled to simplifi the presentation
Substituting (3.14) and (3.15) in (3.13) yields:
D+D% 1 (3.16)
By equalizhg (3.1 1) and (3.12) and substituthg Dr 5 I - D in these equations, we
have
Laux
And substituthg (3.16) for D' in (3.1 7) yields
V,D = (V, - V,)DtS (V, - V,)(l- D )
Equation (3.18) might be simplined and give the following expression
V, 2- V" * V d c > & (3.19) 1-D
Substihrting (3.1 9) in (3.1 0) shows that the voltage across L, during this state is
negative and current i, is decreasing.
2) The dc link capacitor is charged as the awciliary current flows through it. Current in the
secondary is fieewheeling through the output diodes and load. At the end of this state
auxiliary current becomes zero.
Fig. 3.6 shows the equivalent simplified circuit representing this state.
L a.. L 0
Fig. 3.6 State Two Equivalent Simplified Circuit
3.23 State Three: A d a m Current is zero ITn-(t +t - L-2
in this state the auxiliary current is zero as ail the energy stored in the auxiliary
inductor has been used to charge the dc link capacitor and the net dc voltage across the
a d i a r y inductor is ais0 zero. The equivalent simplifïed circuit could be represented as
shown in Fig. 3.7.
Fig. 3.7 State Three: Zero awciliary current
During this state the output current is fkeewheeling through the output diodes and
the load, auxiliary current is zero. This state continues until another power cycle starts.
3.3 Tums Ratio of the Hieh Freauencv Transformer
The tums ratio of the high fkequency transformer is found using the value of
minimum input voltage, maximum duty cycle and the rated output voltage.
For proper operation of the circuit the maximum pulse width (bn ) should not
exceed 90' which results in a maximum duty cycle of 50% @ = 2t,.,J
v,% v, D=---.-- v, N, - v, ns
Also, the value of dc link voltage is found &om (3.19) as
Using these equations the value of the turns ratio of the transformer is found
E x m l e :
D, = 0.45
V,, = 248.902 V
v,=so v
The value of the dc link voltage is found fkom (3.23)
we chose n, = 4 and the maximum duty cycle becomes:
3.4 Modes of Conduction and the Value of the Auxiliarv Inductor
3.4.1 Value of the Auxiliary Inductor
The dc link capacitor current waveform is shown in Fig. 3.8. This waveform is
used to h d the value of the auxiliary inductor.
Fig. 3.8 Dc link capacitor current
It is well known that in steady state the average current through the dc lin
capacitor is equal to zero. This fact is used to h d the value of the auxiliary inductor.
Solving equation (3 .Dl), L, is expressed as:
The value of the inductance as a function of input voltage and switching
frequency is plotted in Fig. 3.9
The per unit inductor value could be expressed as:
Fig. 3.9 The value of the auxiliary inductor for different switching frequencies and input voltage levels
3.4.2 Modes of Conduction of the Auxiliary Inductor
The auxiliary inductor is a key element in the operation of this circuit, it might
even be considered the most important component. As any inductor it might operate in
two modes of conduction:
1) Continuous Auxiliary Inductor Conduction Mode (CACM); when there is no
time interval where the current passing through it drops to zero. With higher inductance
values we operate in CACM.
II) ) Discontinuous Awiliary hductor Conduction Mode (DACM), when in some
time intervals the current passing through it drops to zero. With lower inductance values
we operate in DACM. There is a value of inductance, which gives an operation on the
boundary between rhese two modes.
As was mentioned before, for the proper operation of the circuit we must operate
in DACM ail the time, independent of the line and load conditions. The hductor shouid
be designed for extreme conditions of low line voltage and full Ioad.
The boundary is drawn using calculations for different input voltage ranges and
switching fieqtxencies. It is observed that maximum load and low input voltage are the
exireme conditions which define where this boundary occurs.
Fig. 3.10 shows the boundary between these two modes for input voltage range
Vin = 85-135 volts.
Fig. 3.1 1 shows the boundary between these two modes for input voltage range
Vin = 176-266 volts.
Fig. 3.10 Boundary of CCM and DCM for Vin = 85-135 volts
50
45
40
35
30
25
20
15
10
5 - O
1 I Discontinuous mode :Continuous mode
t I 1
- Continuous : Discontinuous Mode : Mode -
. -
- . . - f ~ ~ = 5 0 kH7 . - - fsw=70u7 - -
fsw=128 kHz - *
fsw=200 kHz
I 1 1
fsw=128 kHz
fsw=200 kHz i
0.85 0.9 0.95 - 1
D+D' 1 .O5
Fig. 3.11 Boundary of CCM and DCM for Vin = 176-266 volts
3.5 Dc Link Voltage
The waveforms of the auxiiiary current and voltage during a switching period are
s h o w in Fig. 3.12.
Fig. 3.12 Current through the auxiliary inductor
The peak current of the auxiliary inductor in each period, 'n', could be expressed
as:
or as:
where
Where, V, is the value of iine voltage at the beginning of each power transfer cycle.
Using equations (3.26) - (3.27) and the energy balance between the average input
and output power, the value of the awiiiary inductor could be found. The input power in
each half switching cycle could be found as:
and the overall average power is found by the summation of ail these average power
components over a line fkequency cycle (TL = l/fL ), where Ln - is the power cycle
duration and Ts - is the switching fiequency.
The output power (averaged over a line fiequency cycle) could be expressed as:
where, D - is the duty cycle, or power transfer period. The value of dc link capacitor
voltage and the required duty cycle can be found by solving the equations (3.30) and
(3.3 1) numericaiiy. Vdc is a function of load, duty cycle and output current.
3.6 Performance Characteristics - Ratin~s Of The Com~onents
3.6.1 RMS Current Through The Switches
The current passing through any of the fidl bridge switches is the sum of three
components:
1. Reflected load current
This expression is valid for continuous current mode of the output filter inductor.
2. Magnetizhg current
The expression for the switch current is:
And its RMS value over a period of Ts/2 is found by integrating the expression for iwitC:
from O to Ts/2. This is the RMS current for half a switching penod and the RMS switch
current is found by averaging all these partïcular areas over the line fiequency period.
The following expression is used to £ïnd the RMS value of the switch current:
This expression is valid for the case when the current waveform has an analytical-
continuous expression in the line fiequency period. In the given topology the switch
current consists of a discrete waveform which repeats itseif over switching Eequency
period with a clifference in amplitude between each cycle. So the RMS switch cunent is
found by using a modified formula of (3.37)
where
2 T ~ , nurnber of auxiliary current periods in a line fiequency period. f , = ~
We know that
Substituthg the expression for the output voltage fiom (3.40) in (3 -41) yields
And by integrating (3.41) we obtain
Dr- - 2
(3 -42)
Expression (3.42) is substituted in (3.38) and the result is used to plot the value of
the switch RMS current versus the output load as will be shown in later parts of this
thesis.
3-6-2 RMS I u ~ u t Current
The waveform of the input cunent is shown on Fig. 3.13
Fig. 3.13 Input current and auxiliary voltage waveforms
The rms. value of the input curent is expressed as
1
The Iust increasing part of the input current iinl is
and its square is
The correspondhg area under this curve is found as
The second decreasing part of the input current iia is
The corresponding area under this curve is found as
where
Using the following relationship (3.50) in (3.49) yields
and the expression for the overall RMS input current before filtering is obtained by
substituting (3.47) and (3.5 1) in (3 -44):
Using these equations, the current RMS value is plotted in later chapters.
The expression for input current after filtering could be found by averaging the
waveform of the current
and the RMS value of this current is found as:
DC Link Ca~acitor Current
Based on the waveform of the
in Fig. 3.8, during the first period
current passing through the dc link capacitor,
b, = DTJ2 the expression for the current is:
During the second penod blf= DG 1 2 the expression for the current is:
The RMS current is defined by the following formula:
where,
2 2 i ~ à k - n ( f ) = i ~ d c - i n ( t ) + i ~ a k - (3 .58)
First integrals of both dc capacitor currents in expressions (3.55) and (3.56) are
found as:
and the area for the second curent component is:
where
D' = D V& V& -G
The RMS current through the dc link capacitor is:
3.6.4 Oumut Filter Ca~acitor RMS Current
The RMS current through the output filter capacitor is a function of the allowed
current ripple which is in turn a fiinction of the inductor value. Fig 3.14 shows the
theoretical waveforms of the current through the output filter components.
Fig. 3.14 Current through the output nIter components
During the on tirne internai t = [O, DTs/2] the expression for the output capacitor
current is:
And the area under the square vaiue of this cwrent component is
During the remainder of the half switching period, t = [O, (1-D)Ts/4], the
expression for the output capacitor current is:
and the area under the square vaiue of this current component is
and the overall RMS current of the output Mter capacitor is
3.6.5 OutDut Filter Inductor And Current Rimle
The output voltage is expressed in ternis of the dc Lùik voltage and the duty cycle
The current ripple of the output filter inductor was shown in Fig. 3 -5 and equals
Also,
and the ripple factor is defïned as:
The value of the output fiiter inductor is found for a given npple factor by solving
(3.71)
Output Voltage IRimle
The output voltage ripplc
Then for a known value
is found to be
of dowed voltage and curent ripple, the output filter
ca~acitor is found fiom (3.731
3.6.7 b u t Power Factor
The input power factor is defined as the turns ratio of the real power to the
apparent input power. As was assumed in previous sections if the system has 100 %
efficiency and the apparent input power equals the average output power, then power
factor could be expressed as:
Ali variables in equation (3.73) codd be defined either fiom circuit specincation
or the performance characteristics of the circuit, as in the case of the input RMS current
dehed in section 3.5.2.
3.6.8 Total Harmonic Distortion
Total harmonic distortion is represented by the following expression
3.7 Conciusions
The steady state analysis of the proposed converter have been performed in this
chapter. The operation of the circuit was described based on three States of operation of
the converter. A method for calculating the auxiliary inductance, tum ratios of the high
fiequency transformer, RMS currents in the circuit, and the DC link voltage value have
been presented. It is concluded that the DC link Voltage value is Load dependent for the
COCM and varies in a wide range of 5 to 1 fiom 10 % to 100% load. This is why the use
of this converter in this mode is recommended for operation fiom input line voltage of