Applied Materials External A Plasma Doping Process for 3D FinFET Source/ Drain Extensions JTG 2014 Cuiyang Wang*, Shan Tang, Harold Persing, Bingxi Wood, Helen Maynard, Siamak Salimian, and Adam Brand [email protected]Varian Semiconductor Equipment | Silicon Systems Group
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Applied Materials External
A Plasma Doping Process for3D FinFET Source/ DrainExtensions
JTG 2014
Cuiyang Wang*, Shan Tang, Harold Persing,Bingxi Wood, Helen Maynard,Siamak Salimian, and Adam Brand
Fin height: ~130nm, Fin width: ~50nm, Fin pitch: ~110nm
Applied Materials External
Implant Approach: EDS Verification ofDopant into Fin Sidewall
JTG Meeting, 2014
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As
Co
mp
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itio
n(%
)
Sio
rO
co
mp
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n(%
)
EDS Line Scan Site
O
Si
As
EDS as-implanted line scan demonstrates As doping into fin sidewall
Si Fin SiO2
Si Fin
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Fin height: ~130nm, Fin width: ~50nm, Fin pitch: ~110nm
Applied Materials External
Outline
A Plasma Doping Process for 3D FinFET Source/ Drain Extensions
1. Plasma Doping for 3D FinFETs
2. Metrology for FinFET Doping Characterization
3. Doping Responses and Fin conductance
4. Summary and Acknowledgements
JTG Meeting, 20142
Applied Materials External
Summary
Plasma doping of Fin structures by an implant based approachhas been demonstrated
The application of plasma doping into logic device technology israpidly accelerating
Efforts to enhance fundamental understanding and to enablepredictive approaches are in progress
As 3D transistor technology continues to be implemented, PLADwill be required for doping and material property modification
14 JTG Meeting, 2014
Applied Materials External
Acknowledgements
Appreciation is extended to Alexander Pagdanganan, MartinHilkene, and Matthew Castle for providing the poly-silicondeposition and process flows at the Maydan Center
We would also like to thank Peter Ryan for his support of theplasma doped sample preparation