Page 1
2013 Master Thesis
A novel interface controlled
silicidation process
for future 3D Schottky devices
Yuta Tamura
11M36253
Department of Electrical and Electronic Engineering
Tokyo Institute of Technology
Supervisor
Professor: Hiroshi Iwai
Associate Professor: Kuniyuki Kakushima
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A novel interface controlled silicidation process for future 3D Schottky devices
i
Contents Chapter 1. Introduction
1.1 CMOS scaling .............................................................................................................2
1.2 Introduction of Schottky barrier S/D FET....................................................................5
1.3 Issues in Schottky barrier S/D FET..............................................................................6
1.4 Reports on Schottky barrier S/D FET ..........................................................................9
1.5 Purpose of this study ................................................................................................. 11
1.6 Outline of this thesis ..................................................................................................13
References ......................................................................................................................15
2.1 Fabrication procedure ...............................................................................................19
2.2 Experimental details..................................................................................................20
2.2.1 SPM cleaning and HF treatment .............................................................................20
2.2.2 RF magnetron sputtering .......................................................................................20
2.2.3 Lift-off process .....................................................................................................21
2.2.4 Vacuum evaporation for Al deposition.....................................................................21
2.2.5 Rapid thermal annealing (RTA) ..............................................................................22
2.3 Electrical characterization of Schottky diode .............................................................24
2.3.1 Metal-silicon contact .............................................................................................24
2.3.2 Image-force lowering ............................................................................................25
2.3.3 Thermionic emission .............................................................................................26
References ......................................................................................................................28
3.1 Introduction ..............................................................................................................30
3.2 Thermal stability of Ni silicide films...........................................................................31
3.3 Bonding states of Ni silicide film ................................................................................33
3.4 Conclusion ................................................................................................................34
References ......................................................................................................................35
4.1 Introduction ..............................................................................................................38
4.2 Interface reaction ......................................................................................................39
4.3 Morphology and composition.....................................................................................41
4.3.1 Thermal stability of stacked silicidation process .......................................................41
4.3.2 XRD analysis of stacked silicide film......................................................................43
4.3.3 XPS analysis of stacked silicide film.......................................................................47
4.3.4 Annealing temperature dependent the phase of stacked silicide ..................................48
4.3.5 The effect of sputtering pressure on sheet resistance of stacked silicide.......................50
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A novel interface controlled silicidation process for future 3D Schottky devices
ii
4.4 Stacked silicidation process of other semiconductor substrates ...................................54
4.4.1 Characteristics of stacked silicide on different Si orientation .....................................54
4.4.2 Characteristics of stacked silicide on other semiconductor substrates..........................56
4.5 Extension of stacked silicidation process for Ti...........................................................59
4.6 Conclusion ................................................................................................................61
References ......................................................................................................................62
5.1 Introduction ..............................................................................................................65
5.2 Schottky diode characteristics....................................................................................66
5.3 TiN capping on stacked silicide ..................................................................................68
5.4 Conclusion ................................................................................................................70
References ......................................................................................................................70
6.1 Introduction ..............................................................................................................72
6.2 Bn modulation with stacked silicidation process.........................................................74
6.2.1 Interface reaction of impurity incorporation .............................................................74
6.2.2 SIMS impurity profiles..........................................................................................75
6.2.3 Bn modulation by impurity incorporation................................................................76
6.3 Bn controllability by impurity incorporation .............................................................78
6.3.1 Annealing conditions dependent J-V characteristics with impurity at the interface .......78
6.3.2 Impurity position dependent J-V characteristics........................................................79
6.3.3 Annealing conditions dependent J-V characteristics with impurity far from the interface80
6.3.4 Impurity amount dependent diode characteristics .....................................................83
6.4 Conclusion ................................................................................................................85
References ......................................................................................................................86
7.1 Introduction ..............................................................................................................88
7.2 Fabrication process ...................................................................................................88
7.3 Electrical characteristics for SB-FET .........................................................................89
7.4 Conclusion ................................................................................................................91
References ......................................................................................................................91
Chapter 8 ........................................................................................................................92
Acknowledgments...........................................................................................................98
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Chapter 1. Introduction
1
Chapter 1 Introduction
1.1 CMOS scaling
1.2 Introduction of Schottky barrier S/D FET
1.3 Issues in Schottky barrier S/D FET
1.4 Reports on Schottky barrier S/D FET
1.5 Purpose of this study
1.6 Outline of this thesis
References
Page 6
Chapter 1. Introduction
2
1.1 CMOS scaling
Very Large Scale Integration (VLSI) technology has been considered
essential to modern information society. VLSI circuits have been constructed by
Complementally Metal-Oxide-Semiconductor (CMOS) Field-Effect-Transistor
(FET). It is necessary for development of Information Technology (IT) that
CMOSFET with high speed, low power consumption is achieved. The key to the
advancement of VLSI technology is the device scaling which means scaling down
the size of MOSFETs. Table 1.1 and figure 1.1 show the scaling rules for various
device and circuit parameters. Scaling rules show speed up of circuit and reduction
of power consumption are obtained with the scaling of the device dimensions [1.1].
Therefore, scaling leads to improvement of convenience for people and saving
energy.
Table 1.1 Constant-field scaling of MOSFET device and circuit parameters.
The scaling remains electrical field unchanged.
1Electric field (E)
1/kJunction depth (xj)
kDoping concentration (N)
1/kDepletion layer width (Wd)
1/k2Device area (A)
1/kCircuit delay time (t)
1/k2Power consumption (P)
1/kGate oxide thickness (tox)
1/kChannel width (W)
1/kChannel length (L)
Multiplicative factorParameters
1Electric field (E)
1/kJunction depth (xj)
kDoping concentration (N)
1/kDepletion layer width (Wd)
1/k2Device area (A)
1/kCircuit delay time (t)
1/k2Power consumption (P)
1/kGate oxide thickness (tox)
1/kChannel width (W)
1/kChannel length (L)
Multiplicative factorParameters
Page 7
Chapter 1. Introduction
3
Source Drain
Gate oxide
Gate
Wd
xj
tox
L
Wd/kxj/k
tox/k
L/k
DrainSource
Gate
Gate oxideScaling
Figure 1.1 Schematic illustration of scaling MOSFET.
A lot of the performance of MOSFET has been improved by scaling, however,
semiconductor industry has entered the era of material- and structure-limited device
scaling [1.2]. Thus, the introduction of new materials such as high-k gate insulators
(to replace SiO2 gate insulators), strained silicon, Ge and III-V substrates (to replace
Si substrates) metal gates (to replace polysilicon gates) and metal source/drains
(S/Ds) (to replace doped silicon S/Ds), and structures such as silicon on insulator
(SOI), Fin and silicon nanowires (SiNWs), have been investigated as shown in table
1.2 and figure 1.2 [1.3]. However, there remain some issues in MOSFET with
extremely scaling, such as short channel effect.
Page 8
Chapter 1. Introduction
4
Table 1.2 The building-block materials of conventional and new material MOSFETs.
Strained-Si, Ge, III-VSiSubstrate
Metal (silicide)DopedS/D
MetalPolysiliconGate electrode
high-kSiO2Gate insulator
New materialConventional
Strained-Si, Ge, III-VSiSubstrate
Metal (silicide)DopedS/D
MetalPolysiliconGate electrode
high-kSiO2Gate insulator
New materialConventional
Source Drain
Gate
BOX
SOI FET
Si sub
BOX
Source
GateDrain
Multi-Gate FET SiNW FET
Si sub
BOX
Source
GateDrain
Si Nanowire
Figure 1.2 Schematic illustration of MOSFET with new structures.
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Chapter 1. Introduction
5
1.2 Introduction of Schottky barrier S/D FET
When device size is scaled down, short channel effects occur. For short
channel MOSFETs, there are some issues which are decrease of threshold voltage,
drain induced barrier lowering (DIBL) and so on. Thus, it is one of the key for
suppression of short channel effects to achieve abrupt and shallow junction at S/D
[1.4]. An approach to realize the abrupt and shallow junction is using Schottky
barrier S/D, which is typically formed by silicide. Schottky barrier S/D has some
advantages which is atomically abrupt and shallow junctions and low parasitic
resistance [1.5]. In addition to these advantages, a low temperature process
capability is another advantage of Schottky barrier S/D [1.6]. Therefore, Schottky
barrier S/D is the key technology to realize suppression of short channel effects
(figure 1.3).
Hardmask
Gate
SourceDrain
SourceDrain
Gate
Lphy
Do
pant
Co
nc.
y position
Gate
(a) Conventional doping S/D
Gate
Metal Metal
MetalMetal
Gate
Me
tal C
onc.
y position
Gate
Lphy = Leff
(b) Schottky barrier S/D
Figure 1.3 (a) 3D-FETs with conventional pn junctions suffer from short channel
effects with channel length scaling due to the dopant diffusions which lower the
abruptness. (b) Metal (silicide) Schottky junction is one of the solutions to suppress
short channel effects because of abrupt junctions [1.7, 1.8].
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Chapter 1. Introduction
6
1.3 Issues in Schottky barrier S/D FET
Schottky barrier S/D has been investigated for replacing conventional
doping S/D to overcome short channel effects discussed in previous chapter.
Especially, Ni silicides are expected as the material of Schottky barrier S/D because
of some advantages which are relatively low resistivity, relatively low formation
temperature and relatively small Si consumption during the formation for application
to nanoscale structure [1.9]. However, there are some challenges in Ni silicides. One
is changing silicide phases depending on initial Ni thickness and annealing
temperature as shown in figure 1.4 [1.10, 1.11, 1.12]. Silicide characteristics, such as
resistivity, B and so on, change with changing silicide phases as shown in table 1.3
[1.13, 1.14]. Thereby, it is important to control the silicide phase to obtain stable
characteristics at wide process temperature range.
Morphology problemdue to agglomerationtNi
(nm)
4nm
Annealing temperature (oC)500400300 800
NiSi2
NiSi
NiSi2
Ni-richphase
NiSi+NiSi2
Figure 1.4 A schematic image of crystalline phases of Ni silicides on the initial Ni
thickness and annealing temperature [1.10, 1.11, 1.12].
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Chapter 1. Introduction
7
Table 1.3 Phase dependent characteristics of Ni silicides [1.13, 1.14].
0.7
0.7 ~ 0.75
0.7 ~ 0.75
Bn (eV)
――CubicDopant
dependentSi
3.663.61Cubic34-50NiSi2
1.832.20Orthorhombic10.5-18NiSi
0.911.47Orthorhombic24-30Ni2Si
0.611.31Cubic80-90Ni3Si
1.22
0.71
0
Si comsunption / TNi
1.75Orthorhombic60-70Ni3Si2
1.40Hexagonal90-150Ni31Si12
1Cubic7-10Ni
Tsilicide / TNiCrystal structureResistivity (・cm)
Phase
0.7
0.7 ~ 0.75
0.7 ~ 0.75
Bn (eV)
――CubicDopant
dependentSi
3.663.61Cubic34-50NiSi2
1.832.20Orthorhombic10.5-18NiSi
0.911.47Orthorhombic24-30Ni2Si
0.611.31Cubic80-90Ni3Si
1.22
0.71
0
Si comsunption / TNi
1.75Orthorhombic60-70Ni3Si2
1.40Hexagonal90-150Ni31Si12
1Cubic7-10Ni
Tsilicide / TNiCrystal structureResistivity (・cm)
Phase
Another is pattern dependent reaction. Figure 1.5 shows excess encroachment of
silicide (a) near STI [1.15] or (b) into narrow channel (SOI/Fin/SiNW) due to
supplying excess Ni atoms [1.16]. Forming facets or interface roughness degrades
diode characteristics such as B or n-factor. On the other hand, encroachment into
narrow channel also degrades controllability of junction position [1.17]. Therefore, it
is significant to control interface reaction.
SiSTI
STI
(111) facet
Si(100)
NiSi2
(a)
(111) facet
Ni atom diffusion
(b)
silicideencroachment
Ni
200nm
50nm
Ni source
Figure 1.5 Pattern dependent silicide reactions (a) near STI region and (b) Si Fin
structure. Forming facets or encroachment of silicide degrade diode characteristics
or controllability of junction position, respectively.
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Chapter 1. Introduction
8
The other is control of B. Bn and Bp, which are B for electron and B for hole,
respectively, should be optimized for n-type SB-FET and p-type SB-FET,
respectively. It is investigated that large Bn and Bp lead to low on-currents, poor
subthreshold swing and ambipolar characteristics [1.5]. Thus, it is necessary for
achieving high performances of SB-FET to reduce Bn and Bp.
As shown in figure 1.6, the exact control of both (a) the junction position and (b) B
improves the device performance [1.6]. Therefore, it is the key for achieving the
high performance of Schottky barrier S/D MOSFET (SB-FET) to control of junction
position and B.
(a) (b)
Figure 1.6 (a) Dependence of Ion-Ioff characteristics on junction position in SB-FETs.
(b) Ion-Ioff characteristics for Bn = 0~0.3 eV. The data in (a) and (b) were estimated
by simulation [1.6].
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Chapter 1. Introduction
9
1.4 Reports on Schottky barrier S/D FET
B is determined by channel Si and silicide materials at S/D. Proper silicide
materials at S/D have to be selected to reduce B. Pt/Pd silicides and Er/Yb silicides
have been proposed for p- and n-type SB-FET, respectively [1.18]. However, there
has a problem which is control of silicide formation of these silicides [1.19, 1.20].
Furthermore, when CMOSFETs are taken into account, it is necessary to control two
different silicidation.
On the other hand, to obtain the proper B, midgap B silicide (Ni/Co) with dopant
segregation has been examined [1.21, 1.22]. There have two ways to achieve dopant
segregation as shown in figure 1.7. One is (a) ion implantation before silicidation
where dopants pile up at silicide/Si interface with silicidation and the other is (b) ion
implantation after silicidation where dopants segregate at silicide/Si interface by
activation annealing. The advantage of dopant segregation method is that the control
of silicidation is only single silicide material. However, the issues of dopant
segregation are (a) junction position control with silicidation and (b) control of the
dopant position, especially 3D devices such as Si Fin or SiNW. Therefore, control of
junction position and dopants are the key.
Page 14
Chapter 1. Introduction
10
(a)
(b)
Figure 1.7 Methods of dopant segregation to modulate B. (a) ion implantation
before silicidation where dopants pile up at silicide/Si interface [1.23], (b) ion
implantation after silicidation where dopants segregate at silicide/Si interface by
activation annealing [1.6].
Page 15
Chapter 1. Introduction
11
1.5 Purpose of this study
As discussed in previous chapters, it is necessary for SB-FET with high
performance to control silicide phase, junction position and impurity position and to
modulate B. The purpose of this study is to overcome these issues of SB-FET. Thus,
a novel stacked silicidation process is proposed. In this process, a set of Ni/Si is
cyclically stacked on Si substrates to form NiSi2 at low temperature. The concept of
this process is to suppress the interface reaction between Ni and Si substrate by Si
deposition in addition to Ni as shown in figure 1.8. Moreover, B and impurity
incorporated position can be controlled by deposition of impurity without ion
implantation process. Finally, the device concept with stacked silicidation process
for SOI, Fin, SiNW FETs is proposed as shown in figure 1.9. Atomically flat
silicide/channel interface with no pattern dependent silicide reaction and no
encroachment, also with B modulation should be realized.
n-Si(100)
NiSi2(corresponding to atomicconcentration of 2:1)
・・・
n-Si(100)
Si/Ni
Annealing
Figure 1.8 Schematic illustration of stacked silicidation process. A set of Si/Ni, with
an atomic ratio of 2:1, is cyclically stacked on n-Si (100) substrates, followed by
annealing in N2 ambient to form NiSi2 film.
Page 16
Chapter 1. Introduction
12
Flat silicide/channel interface with Bn modulation
SiNW
silicide
gate
SiNW FETFinFET gate
silicide
Si FinSOI
silicide
gate
SOI
Figure 1.9 Schematic illustrations of the device concept with stacked silicidation
process for SOI, Fin, SiNW FETs. Atomically flat silicide/channel interface with
keeping the shape of various Si substrates is achieved by using stacked silicidation
process.
Page 17
Chapter 1. Introduction
13
1.6 Outline of this thesis
Figure 1.10 shows the contents of this thesis. This thesis is consisted of 8
parts.
In chapter 1, the introduction of this thesis is stated.
In chapter 2, the fabrication process of devices and electrical characterization of
Schottky diodes are explained.
In chapter 3, Ni film thickness dependent characteristics are investigated. It
becomes obvious that NiSi2 which is formed by 3.0-nm-thick Ni layer can be formed
at low temperature and has stable characteristics at wide temperature range.
In chapter 4, characteristics of Ni silicide which is formed by stacked silicidation
process are examined. An atomically flat interface and stable characteristics can be
achieved by using stacked silicidation process. Moreover, an extension of stacked
silicidation process to Ti is investigated.
In chapter 5, electrical characteristics of Ni silicide Schottky diodes are investigated.
Schottky diode using stacked silicidation process has ideal characteristics.
In chapter 6, Schottky barrier height modulation with impurity incorporation is
examined. It is realized that Schottky barrier height is modulated by impurity
incorporation to the interface. Moreover, Schottky barrier height modulation
controllability is investigated.
In chapter 7, SB-FET using stacked silicidation process is demonstrated. It is
confirmed that ambipolar characteristics are suppressed by modulating Schottky
barrier height.
Finally, chapter 8 summarizes this study.
Page 18
Chapter 1. Introduction
14
Chapter 1Introduction
Chapter 2Fabrication and characterization
Chapter 3Thickness dependent
characteristics of Ni silicides
Chapter 5Electrical characteristics of Ni silicide Schottky diodes
Chapter 7Demonstration of silicide Schottky S/D FET
with barrier height modulation
Chapter 8Conclusion
Chapter 4Ni silicides using
stacked silicidation process
Chapter 6Schottky barrier height modulation
Figure 1.10 Contents of this thesis
Page 19
Chapter 1. Introduction
15
References
[1.1] Y. Taur, T. H. Ning, “Fundamentals of MODERN VLSI DEVICES”,
Cambridge University Press (1998).
[1.2] International Technology Roadmap for Semiconductors (ITRS) 2009 roadmap.
[1.3] T. Skotnicki, James A. Hutchby, Tsu-Jae King, H.-S. Philip Wong and Frederic
Boeuf, “The end of CMOS scaling: toward the introduction of new materials and
structural changes to implove MOSFET performance”, IEEE Circuits and Devices
Mag., 21, pp. 16-26 (2005).
[1.4] K. Tanaka, K. Takeuchi and M. Hane, “Practical FinFET Design considering
GIDL for LSTP (Low Standby Power) Devices”, IEDM Tech. Dig., pp.980-983
(2005).
[1.5] John M. Larson and John P. Snyder, “Overview and Status of Metal S/D
Schottky-Barrier MOSFET Technology”, IEEE Trans. Electron Devices, 53,
pp.1048-1058 (2006).
[1.6] W. Mizubayashi, S. Migita, Y. Morita, and H. Ota, “Exact Control of Junction
Position and Schottky Barrier Height in Dopant-Segregated Epitaxial NiSi2 for High
Performance Metal Source/Drain MOSFETs”, Symp. on VLSI Tech. Dig., pp.88-89
(2011).
[1.7] A. Kaneko, A. Yagishita, K. Yahashi, T. Kubota, M. Omura, K. Matsuo, I.
Mizushima, K. Okano, H. Kawasaki,T. Izumida, T. Kanemura, N. Aoki, A. Kinoshita,
J. Koga, S. Inaba, K. Ishimaru, Y. Toyoshima, H. Ishiuchi, K. Suguro, K. Eguchi,
Y.tsunashima, “High-Performance FinFET with Dopant-Segregated Schottky
Source/Drain”, IEDM Tech. Dig., pp.1-4 (2006).
Page 20
Chapter 1. Introduction
16
[1.8] S. Migita, Y. Morita, W. Mizubayashi and H. Ota, “Epitaxial NiSi2 Source and
Drain Technology for Atomic-Scale Junction Control in Silicon Nanowire
MOSFETs”, Inter. Workshop on Junction Techno. (2010).
[1.9] H. Iwai, T. Ohguro and S. Ohmi, “NiSi salicide technology for scaled CMOS”,
Microelectronic Eng., 60, pp.157-169 (2002).
[1.10] K. Tsutsui, R. Xiang, K. Nagahiro, T. Shiozawa, P. Ahmet, Y. Okuno, M.
Matsumoto, M. Kubota, K. Kakushima, and H. Iwai, “Analysis of irregular in sheet
resistance of Ni silicides on transition from NiSi to NiSi2”, Microelectronic Eng., 85,
pp.315-319 (2008).
[1.1] K. De Keyser, C. Van Bockstael, R. L. Van Meirhaeghe, C. Detavernier, E.
Verleysen, H. Bender, W. Vandervorst, J. Jordan-Sweet, and C. Lavoie, “Phase
formation and thermal stability of ultrathin nickel-silicides on Si(100)”, Appl. Phys.
Lett., 96, pp.173503 (2010).
[1.12] L. Knoll, Q. T. Zhao, S. Habicht, C. Urban, B. Ghyselen, and S. Mantl,
“Ultrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained
Silicon”, IEEE Electron Devices Lett., 31, pp.350-352 (2010).
[1.13] L. J. Chen, “Silicide Technology for Integrated Circuits”, The Institution of
Electrical Engineers, London (2004).
[1.14] S. P. Murarka, “SILICIDES FOR VLSI APPLICATIONS”, Academic Press,
New York (1983).
[1.15] O. Nakatsuka, A. Suzuki, S. Akimoto, A. Sakai, M. Ogawa and S. Zaima,
“Dependence of Electrical Characteristics on Interfacial Structure of Epitaxial
NiSi2/Si Schottky Contacts Formed from Ni/Ti/Si System”, J. J. Appl. Phys., 47,
pp.2402-2406 (2008).
Page 21
Chapter 1. Introduction
17
[1.16] Y. C. Lin, Y. Chen, D. Xu and Y. Huang, “Growth of Nickel Silicides in Si and
Si/SiOx Core/Shell Nanowires”, Nano Lett., 10, pp.4721-4726 (2010).
[1.17] W. M. Weber, L. Geelhaar, A. P. Graham, E. Unger, G. S. Duesberg, M.Liebau,
W. Pamler, C. Chèse, H. Riechert, P. Lugli, and F. Kreupl, “Silicon-Nanowire
Transistors with Intruded Nickel-Silicide Contacts”, Nano Lett., 6, pp.2660-2666
(2006).
[1.18] R. Kuroda, H. Tanaka, Y. Nakao, A. Teramoto, N. Miyamoto, S. Sugawa and T.
Ohmi, ”Ultra-low Series Resistance W/ErSi2/n+-Si and W/Pd2Si/p+-Si S/D
Electrodes for Advanced CMOS Platform”, IEDM Tech. Dig., pp.580-583 (2010).
[1.19] S. Zhu, J. Chen, M. F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A.
Chin and D. L. Kwong, “N-Type Schottky Barrier Source/Drain MOSFET Using
Ytterbium Silicide“, IEEE Electron Devices Lett., 25, pp.565-567 (2004).
[1.20] E. Alptekin, M. C. Ozturk and V. Misra, “Tuning of the Platinum Silicide
Schottky Barrier Height on n-Type Silicon by Sulfur Segregation”, IEEE Electron
Devices Lett., 30, pp.331-333 (2009).
[1.21] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida and J. Koga, “Solution for
High-Performance Schottky-Source/Drain MOSFETs: Schottky Barrier Height
Engineering with Dopant Segregation Technique”, Symp. on VLSI Tech. Dig.,
pp.168-169 (2004).
[1.22] N. Mise, S. Migita, Y. Watanabe, H. Satake, T. Nabatame and A. Toriumi,
“(111)-Faceted Metal Source and Drain for Aggressively Scaled Metal/High-k
MISFETs”, IEEE Trans. Electron Devices, 55, pp.1244-12498 (2008).
[1.23] A. Kinoshita, “Dopant Segregated Schottky S/D and Application to High
Performance MOSFETs”, Inter. Workshop on Junction Techno. (2009).
Page 22
Chapter 2. Fabrication and characterization
18
Chapter 2 Fabrication and characterization
2.1 Fabrication procedure
2.2 Experimental details
2.3 Electrical characterization of Schottky diode
References
Page 23
Chapter 2. Fabrication and characterization
19
2.1 Fabrication procedure
Figure 2.1 shows fabrication procedure of Schottky diodes. The diodes were
fabricated on n-type (100)-oriented Si substrate. The substrate impurity
concentration is 3 x 1015 cm-3. To determine the diode area, 400nm thermal oxide
was formed, patterned by photolithography and etched SiO2 by buffered HF (BHF).
After SPM cleaning and HF treatment, thermal oxidation was performed because of
protecting Si surface from resists and developers. Lift-off patterning and HF
treatment due to removing SiO2 formed by thermal oxidation were performed. Metal
layer was deposited by RF sputtering. Metal which exists at excess area was
removed by lift off process. An Al film was formed as a back contact by thermal
evaporation. Rapid thermal annealing (RTA) in N2 ambient was performed due to
silicidation.
SPM and HF cleaning
Deposition by RF sputtering in Ar
Silicidation by RTA in N2
Diode patterning
Backside Al contact
BHF etching of SiO2
Lift-off
n-Si(100) Sub with 400 nm SiO2 (3x1015 cm-3)
Figure 2.1 Fabrication flow of Schottky diode.
Page 24
Chapter 2. Fabrication and characterization
20
2.2 Experimental details
2.2.1 SPM cleaning and HF treatment
Particles and organic substance at the surface of Si substrate become a cause
of false operation. Therefore, it is important to clean the surface of Si substrate. SPM
cleaning is one of the effective cleaning methods. The cleaning liquid is made from
H2O2 and H2SO4 (H2O2:H2SO4 = 1:4). Because of its oxidizability, particles and
organic substance are oxidized and separated from the surface of Si substrate.
However, the surface of Si substrate is oxidized and SiO2 is formed during SPM
cleaning. 1% HF is used to eliminate the SiO2.
2.2.2 RF magnetron sputtering
Metal is deposited by radio frequency (RF) magnetron sputtering with Ar
gas. An RF with 13.56 MHz is applied between substrate side and target side.
Because of the difference of mass, Ar ions and electrons are separated. A magnet is
set underneath the target, so that the plasma damage is minimized. Electrons run
through the circuit from substrate side to target side, because substrate side is
subjected to be conductive and target side is subjected to be insulated. Then, target
side is negatively biased and Ar ions hit the target.
Page 25
Chapter 2. Fabrication and characterization
21
Ar+ Ar+
Substrate
Plasma
Target (Ni, Si, Ni3P, B, Ti)
~
Figure 2.2 Schematic illustration of RF magnetron sputtering.
2.2.3 Lift-off process
Lift-off is the process which selectively removes deposited films. Following
photolithography and deposition, resists and deposited films which exist on excess
area are left by ultrasonic cleaning with acetone.
2.2.4 Vacuum evaporation for Al deposition
Al for wiring and backside contact is deposited by vacuum evaporation. Al
source is set on W boat and heated up to boiling point of Al by joule heating.
However, melting point of W is higher than boiling point of Al, W boat doesn’t melt.
The base pressure in the chamber is maintained to be 10-3 Pa (Fig. 2.4).
Page 26
Chapter 2. Fabrication and characterization
22
AlAl
Al
Substrate
Al source
W boat
←
~ 10-3 Pa
Figure 2.3 Schematic illustration of vacuum evaporation.
2.2.5 Rapid thermal annealing (RTA)
Rapid thermal annealing (RTA) is performed for silicidation. Heating
chamber is filled with N2 to interfere with oxidation. In this study, the time of
elevated temperature is 30 seconds and the time of annealing is 1 minute.
A schematic illustration of Schottky diode fabrication process is shown in figure
2.4.
Page 27
Chapter 2. Fabrication and characterization
23
n-Si(100)
SiO2 SiO2 400 nm
n-Si(100)
SiO2 SiO2
SiO2
n-Si(100)
SiO2 SiO2
Resist
n-Si(100)
SiO2 SiO2
n-Si(100)
SiO2 SiO2
Metal
n-Si(100)
SiO2 SiO2
n-Si(100)
SiO2 SiO2
Al
SPM and HF cleaning
Diode patterning
BHF etching of SiO2
Thermal oxidation to protect Si surface
Lift-off patterning
HF treatment
Deposition by RF sputtering in Ar
Lift-off by ultrasonic cleaning with acetone
Backside Al contact by vacuum evaporation
Figure 2.4 Schematic illustration of Schottky diode process.
Page 28
Chapter 2. Fabrication and characterization
24
2.3 Electrical characterization of Schottky diode
Schottky diode characteristics are evaluated by J-V characteristics, B and
n-factor. B and n-factor can be extracted by fitting with ideal J-V curve. In this study,
for analyzing Schottky diode characteristics, image force lowering and thermionic
emission are considered [2.1]. In this chapter, Schottky diodes of metal (silicide) and
n-Si contacts are discussed.
2.3.1 Metal-silicon contact
When metal and silicon contact, these must share the same free electron
level at the interface [2.2]. Also, at thermal equilibrium or when there is no net
electron or hole current through a system, the Fermi level of the system is spatially
constant. These two factors lead to the band diagram as shown in figure 2.5 for a
metal-n-Si contact at thermal equilibrium. Considering free electron energy level,
Schottky barrier height for electron (Bn0) is given by
mBn qq 0 (2.1)
where m is the metal work function and is the electron affinity of silicon.
Page 29
Chapter 2. Fabrication and characterization
25
EcEf
Ev
Ef
qBn0qbi
Metal n-Si
EcEf
Ev
Metal n-Si
Ef
qm
q qs
Free electron level(a) (b)
Figure 2.5 Band diagram of metal-n-Si contact. (a) When the metal and the Si are
far apart. (b) When the metal is in contact with the Si. bi is built-in potential.
2.3.2 Image-force lowering
Image-force lowering is the image-force-induced lowering of the barrier
energy for charge carrier emission [2.2]. Image-force lowering () for the metal-Si
contact is
Si
mqE
4 (2.2)
where Em is maximum value of electric field and Si is the Si permittivity. Therefore,
Schottky barrier height (Bn), considering image-force lowering, is given by
0BnBn qq (2.3)
as shown in figure 2.6.
Page 30
Chapter 2. Fabrication and characterization
26
EcEfEf
qBn0qBn
q
Figure 2.6 Band diagram of metal-n-Si contact incorporating image-force lowering.
2.3.3 Thermionic emission
In thermionic emission, the simplest theory is to deal with the electron as an
ideal gas that follows Boltzman statistics in energy distribution [2.1]. The electron
emission current from Si into metal (Js→m) is given by
nkT
qV
kT
qTAJ Bn
ms expexp 02* (2.4)
where A* is effective Richardson’s constant, n is ideality factor (n-factor) and V is
applied voltage. On the other hand, the electron emission current from metal into Si
(Jm→s) is
kT
qTAJ Bn
sm02* exp
(2.5)
Therefore, the total current Jn0 is given by
Page 31
Chapter 2. Fabrication and characterization
27
1expexp 02*
0 nkT
qV
kT
qTAJ Bn
n
(2.6)
In addition to image-force lowering, total current Jn is
1expexp
1expexp
2*
02*
nkT
qV
kT
qTA
nkT
qV
kT
qTAJ
Bn
Bnn
(2.7)
as shown in figure 2.7. Bn and n-factor are extracted by fitting measurement data
and (2.7).
EcEfEf
Jm→sJs→m
qBn
Figure 2.7 Band diagram of metal-n-Si contact incorporating image-force lowering
to show the thermionic emission current.
Page 32
Chapter 2. Fabrication and characterization
28
References
[2.1] Y. Taur, T. H. Ning, “Fundamentals of MODERN VLSI DEVICES”,
Cambridge University Press (1998).
[2.2] S. M. Sze, Kwok K. NG, “Physics of Semiconductor Devices”, Wiley, New
York (2006).
Page 33
Chapter 3. Thickness dependent characteristics of Ni silicides
29
Chapter 3 Thickness dependent characteristics
of Ni silicides
3.1 Introduction
3.2 Thermal stability of Ni silicide films
3.3 Bonding states of Ni silicide film
3.4 Conclusion
References
Page 34
Chapter 3. Thickness dependent characteristics of Ni silicides
30
3.1 Introduction
Ni silicides have been widely investigated for contact materials in
microelectronic devices because of relatively low resistivity, relatively low
formation temperature and relatively small Si consumption during the formation in
comparison with other silicide materials [3.1]. One of the issues of Ni silicides is that
the formed NiSi, a low-resistive phase in Ni silicides, starts to agglomerate at an
annealing temperature of 600 oC [3.2]. As the agglomeration is the results of
minimizing the gain boundary between NiSi grains and the interface energy of NiSi
and Si substrate, the temperature for agglomeration decreases when the thickness of
NiSi is reduced [3.3]. Recently, Ni films with thicknesses less than 4 nm were found
to be resistant to agglomeration up to an annealing temperature of 850 oC [3.4]. The
difference in the silicide films is the formation of NiSi2 phase even at an annealing
temperature of 300 oC, which is commonly formed at an annealing temperature of
800 oC [3.5]. Therefore, the suppression of the agglomeration can be understood by
the difference in the energy of NiSi2 and NiSi phases. The suppression of
agglomeration is also advantageous to obtain a flat interface between silicides and Si
substrates. The interface of silicide and Si substrates tends to form pyramid shapes
with Si(111) plane [3.6]. Therefore, another advantage of agglomeration-resistant Ni
silicides is the suppression of forming interfaces with different crystallographic
orientations. This chapter confirms the phase and the surface morphology changes of
Ni silicide films on annealing temperature.
Page 35
Chapter 3. Thickness dependent characteristics of Ni silicides
31
3.2 Thermal stability of Ni silicide films
Figure 3.1 and figure 3.2 show sheet resistance (sh) and surface roughness
of the films on annealing temperature, respectively. For the sample with
5.5-nm-thick Ni layer, sh showed a large decrease over 300 oC, which is attributed
to the formation of NiSi phase in the silicide. When the annealing temperature is
over 500 oC, the sh showed a large increase due to agglomeration of the silicides
which is shown in figure 3.2. On the other hand, for the sample with Ni thickness of
3.0 nm, a gradual reduction in the sh was observed over 300 oC, and the value
became stable at annealing temperatures from 400 to 800 oC, which is in good
agreement with previous reports [3.4, 3.6]. Considering the resistivity of typical bulk
NiSi2 (34~50 cm) [3.7], the phase of the silicide film can be considered as NiSi2.
Consequently, both of the thickness of these samples is estimated about 10 nm [3.7].
300
0
400
500
Sh
eet
resi
stan
ce
sh
(/s
q)
200
100
600
400 600Annealing temperature (oC)
800200
RTA : 1min in N2
tNi:3.0nm
tNi:5.5nm
agglomeration
wide process window
n-Si(100)
Ni:5.5nm
n-Si(100)
Ni:3.0nm
Figure 3.1 Sheet resistance (sh) of silicides with 3.0 and 5.5 nm thick Ni layers on
annealing temperature (tNi is Ni thickness).
Page 36
Chapter 3. Thickness dependent characteristics of Ni silicides
32
400 600Annealing temperature (oC)
800200
0.6
0.4
0.2
0.8
1.0
0
rms
Ro
ug
hn
ess
(n
m)
RTA : 1min in N2
agglomeration
tNi:3.0nm
tNi:5.5nm
3 x 3 m2
n-Si(100)
Ni:5.5nm
n-Si(100)
Ni:3.0nm
Figure 3.2 Surface roughness of silicide films with 3.0 and 5.5 nm thick Ni layers on
annealing temperature.
Page 37
Chapter 3. Thickness dependent characteristics of Ni silicides
33
3.3 Bonding states of Ni silicide film
Ni 2p3/2 spectra of the samples annealed at various temperatures are shown
in figure 3.3. The binding energy at the peak intensity was found to shift to higher
energy from pure Ni, which was obtained by as-deposited sample. At an annealing
temperature of 250 oC, the spectrum indicates the main composition is Ni-rich phase,
which is in good agreement with the sh as high resistivity is reported for Ni-rich
phase. The sample with 5.5-nm-thick-Ni showed a single peak at 500 oC annealing,
which corresponds to the NiSi phase at 853.72 eV [3.8]. For 3-nm-thick-Ni samples,
while increasing the annealing temperature, two peak intensities, one at 854.19 eV
with large intensity and the other Ni-rich phase with small intensity, were observed
at 500 oC. The intensity at 854.19 eV further increased when the sample was
annealed at 800 oC, indicating that the residual Ni-rich phase was converted to NiSi2
phase by annealing [3.9].
Binding energy (eV)851853855857
RTA : 1min in N2
h=7938.57eVNi2p3/2
250 oC
500 oC
500 oC
tNi:3.0nm
tNi:5.5nm
tNi:3.0nm
tNi:3.0nm
Inte
nsi
ty (
a.u
.)
as depo
Ni-rich
Ni
NiSi
NiSi2
800 oCtNi:3.0nm
TOA=80o
Figure 3.3 Ni 2p3/2 spectra of the silicide films annealed at various temperature.
Page 38
Chapter 3. Thickness dependent characteristics of Ni silicides
34
3.4 Conclusion
Ni silicides, reactively formed by 3.0-nm-thick Ni, have shown a stable
sheet resistance, flat morphology against annealing temperature up to 800 oC
compared to those formed with thicker Ni film. These properties are owing to the
formation of stable NiSi2 phase at a temperature as low as 500 oC. The summary of
Ni silicide phase and morphology change is shown in figure 3.4.
Ni Ni-rich NiSi
agglomeration
Ni Ni-richNi-rich+NiSi2
as depo 300 oC 500 oC 600 oC 800 oC
NiSi2
Ni < 4.0 nm
Si substrate
Si substrate
NiSi2
Si substrate Si substrate
Ni-rich+NiSi2
Si substrate Si substrate
Si substrate Si substrate Si substrate Si substrateNiSi
Ni > 4.0 nm
Figure 3.4 Ni silicide phase and morphology change dependent on Ni thickness.
Page 39
Chapter 3. Thickness dependent characteristics of Ni silicides
35
References
[3.1] H. Iwai, T. Ohguro, S Ohmi, ”NiSi salicide technology for scaled CMOS”,
Microelectron. Eng. 60, pp.157-169 (2002).
[3.2] K. Tsutsui, R. Xiang, K. Nagahiro, T. Shiozawa, P. Ahmet, Y. Okuno, M.
Matsumoto, M. Kubota, K. Kakushima, and H. Iwai, “Analysis of irregular in sheet
resistance of Ni silicides on transition from NiSi to NiSi2”, Microelectron. Eng., 85,
pp.315-319 (2008).
[3.3] T. P. Nolan and R. Sinclair, R. Beyers, “Modeling of agglomeration in
polycrystalline thin films: Application to TiSi2 on a silicon substrate”, J. Appl. Phys.,
71, pp.720-724 (1992).
[3.4] K. De Keyser, C. Van Bockstael, R. L. Van Meirhaeghe, C. Detavernier, E.
Verleysen, H. Bender, W. Vandervorst, J. Jordan-Sweet, and C. Lavoie, “Phase
formation and thermal stability of ultrathin nickel-silicides on Si(100)”, Appl. Phys.
Lett., 96, pp.173503 (2010).
[3.5] C. Lavoie, C, Detavernier, C. Cabral Jr., F. M. d’Heurle, A. J. Kellock, J.
Jordan-Sweet, J. M. E. Harper, ”Effects of additive elements on the phase formation
and morphological stability of nickel monosilicide films”, Microelectron. Eng., 83,
pp.2042-2054 (2006).
[3.6] L. Knoll, Q. T. Zhao, S. Habicht, C. Urban, B. Ghyselen, and S. Mantl,
“Ultrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained
Silicon”, IEEE Electron Devices Lett., 31, pp.350-352 (2010).
[3.7] L. J. Chen, “Silicide Technology for Integrated Circuits”, London: The Institute
of Electrical Engineers (2004).
Page 40
Chapter 3. Thickness dependent characteristics of Ni silicides
36
[3.8] P. J. Grunthaner and F. J. Grunthaner, A. Madhukar, Chemical bonding and
charge redistribution: Valence band and core level correlations for the Ni/Si, Pd/Si,
and Pt/Si systems J. Vac. Sci. Technol., 20, pp.680-683 (1982).
[3.9] S. Ray, J. Hommet, G. Schmerber, F. Le Normand, “Diamond growth on
polycrystalline nickel silicides”, J. Crys. Grow., 216, pp.225-234 (2000).
Page 41
Chapter 4. Ni silicides using stacked silicidation process
37
Chapter 4 Ni silicides using stacked
silicidation process
4.1 Introduction
4.2 Interface reaction
4.3 Composition and morphology
4.4 Stacked silicidation process of other semiconductor substrates
4.5 Extension of stacked silicidation process for Ti
4.6 Conclusion
References
Page 42
Chapter 4. Ni silicides using stacked silicidation process
38
4.1 Introduction
As described in chapter 3, in the case of 3.0-nm-thick Ni layer deposition,
the stable composition and morphology can be obtained at wide process temperature
range because NiSi2, which is the most stable phase in Ni silicides, is formed at low
temperature. However, there remain some issues which are pattern dependent
reaction and limitation of silicide thickness because of limitation of initial Ni
thickness within 4.0 nm to form NiSi2 at low temperature [4.1, 4.2, 4.3]. Thereby, to
solve these issues, stacked silicidation process is proposed as shown in figure 4.1. In
this process, interface reaction can be suppressed because Si substrate reacts with
only first 0.5-nm-thick Ni layer and silicide thickness can be changed easily by
changing the number of a set of Ni/Si. In this chapter, therefore, characteristics of Ni
silicide using stacked silicidation process are investigated. Furthermore, stacked
silicidation process of other semiconductor substrates and extension of stacked
silicidation process to Ti are examined.
n-Si(100)
NiSi2(corresponding to atomicconcentration of 2:1)
・・・
n-Si(100)
Si/Ni
Annealing
Figure 4.1 Schematic illustration of stacked silicidation process. A set of Si/Ni, with
an atomic ratio of 2:1, is cyclically stacked on n-Si (100) substrates, followed by
annealing in N2 ambient to form NiSi2 film.
Page 43
Chapter 4. Ni silicides using stacked silicidation process
39
4.2 Interface reaction
As shown in figure 4.2, TEM images of silicide/Si interface formed from
Ni/Si stacked silicidation process before (Figure 4.2(a)) and after annealing at 500 oC
for 1 min in N2 ambient to form NiSi2 (Figure 4.2(b)). TEM images revealed the
formation of 10-nm-thick stacked silicide, no change in the thickness and atomically
flat interface and surface before and after annealing at 500 oC because consumption
of Si from substrate is limited to the first Ni layer.
Owing to little reaction of NiSi2 formed from stacked silicidation process
with Si channel, diffusions of Ni atoms into channels can be well suppressed. Figure
4.3 shows SEM images of Si Fins after annealing with (a) Ni or (b) stacked silicide
stripe on the right-hand-side. Due to excess supply of Ni atoms into Si Fins, in the
case of Ni deposition, lateral silicidations were observed with scattered
encroachment length.
as deposited
10nm
Si(100)
8 sets of Si(1.9nm)/Ni(0.5nm)
RTA: 500 oC
10nm
NiSi2
Si(100)
Figure 4.2 TEM images of stacked silicidation process at (a) as deposited and (b)
after annealing at 500 oC. Atomically flat interface and surface are achieved.
Page 44
Chapter 4. Ni silicides using stacked silicidation process
40
On the other hand, with the use of stacked silicidation process, one can observe a
complete inhibition of encroachments into Si Fins, owing to suppression of interface
reaction between silicide and Si Fins. In other words, interface position can be
well-defined by using stacked silicidation process. Although suppression of lateral
encroachments has been reported with 2-step annealing or nitrogen atom
incorporation [4.4, 4.5], stacked silicidation process has an advantage for S/D in 3D
Si channels as it completely suppresses the encroachments.
(a) Ni case
Ni Ni silicide
BOX
Si Fin
Ni silicideencroachment
Ni
500nm
Si Fin Ni
Encroachment of Ni atoms
Ni silicide
500oC
(b) stack case
Ni/Si stack
500nm
Si Fin
No encroachment
500oC
BOX
SiNiSi2
NiSi2Si Fin
No encroachment
Figure 4.3 SEM images of Si Fins after annealing with (a) Ni or (b) stacked silicide.
(a) Ni atoms encroach into Si Fin. (b) Complete suppression of encroachment can be
achieved using Ni/Si stacked silicidation process.
Page 45
Chapter 4. Ni silicides using stacked silicidation process
41
4.3 Morphology and composition
4.3.1 Thermal stability of stacked silicidation process
Figure 4.4 and figure 4.5 show sheet resistance (sh) and surface roughness
of the films on annealing temperature, respectively. The silicide thickness of all
samples is 10 nm. For the sample with Ni/Si stacked silicidation process showed a
decrease over 325 oC and kept the stable value up to 875 oC. Although sh of stacked
silicide is slightly larger than 3.0-nm-thick Ni layer, sh of stacked silicide is stable at
wide process temperature window. On the other hand, the surface roughness of
stacked silicide is slightly larger than those of 3.0-nm-thick Ni sample, however, the
value is small enough. The surface morphology of stacked silicide was flat over wide
range temperature.
300
0
400
500
Sh
eet
resi
stan
ce
sh
(/s
q)
200
100
600
400 600Annealing temperature (oC)
800200
RTA : 1min in N2
agglomeration
wide process window
n-Si(100)
n-Si(100)
Ni:3.0nm
n-Si(100)
Ni:5.5nm
Figure 4.4 sh of stacked silicide, 3.0-nm- and 5.5-nm- thick Ni layers on annealing
temperature. sh of stacked silicide is stable at wide process window.
Page 46
Chapter 4. Ni silicides using stacked silicidation process
42
400 600Annealing temperature (oC)
800200
0.6
0.4
0.2
0.8
1.0
0
rms
Ro
ug
hn
ess
(n
m)
RTA : 1min in N2
agglomeration
3 x 3 m2
n-Si(100)
n-Si(100)
Ni:3.0nm
n-Si(100)
Ni:5.5nm
Figure 4.5 Surface roughness of stacked silicide, 3.0-nm- and 5.5-nm-thick Ni layers
on annealing temperature. Surface roughness of stacked silicide is stable at wide
process window.
Page 47
Chapter 4. Ni silicides using stacked silicidation process
43
4.3.2 XRD analysis of stacked silicide film
Figure 4.6 shows Out-of-plane XRD (2/ scan) profile of stacked silicide.
NiSi2(004) peak can be detected at 2 = 70.56o. Whereat, Rocking curve
measurement ( scan) at 2 = 70.56o is shown in figure 4.7. Because rocking curve
width is about 0.1o which is narrow value, it is considered that NiSi2 formed by
stacked silicidation process is epitaxially grown.
727068662 (deg)
Inte
ns
ity
(a.u
.)
NiS
i 200
4Si 0
04Out-of-plane XRD500 oC, 1min in N2
Figure 4.6 Out-of-plane XRD (2/ scan) profile of stacked silicide annealed at 500
oC. NiSi2(004) peak can be detected at 2 = 70.56o.
Page 48
Chapter 4. Ni silicides using stacked silicidation process
44
Rocking curve: 2 = 70.56o
35.1 (deg)
35.2 35.3 35.4 35.5 35.6
Inte
ns
ity
(a.u
.)
500 oC, 1min in N2
Rocking curve width (FWHM)= 0.114o
Figure 4.7 Rocking curve measurement ( scan) at 2 = 70.56o. Because rocking
curve width is about 0.1o which is narrow value, it is considered that NiSi2 formed by
stacked silicidation process is epitaxially grown.
Figure 4.8 shows that In-plane XRD (2/ scan) profile of stacked silicide
annealed at 500 oC in = 0.3o. In-plane XRD has some characteristics which are
large irradiated area and small penetration depth due to low incident angle. Red line
shows X-ray incident direction can be observed Si(400) peak ( = 0o) and blue line
shows = 15o. In the case of = 0o, NiSi2(200) and NiSi2(220) peaks are detected.
When is displaced to 15o, NiSi2(200) can not be observed, on the other hand,
NiSi2(220) can be observed. Rocking curve measurement ( scan) at NiSi2(200) is
shown in figure 4.9. Because rocking curve width is about 0.6o which is narrow
value, it is considered that NiSi2 is epitaxially grown. On the other hand, when is
Page 49
Chapter 4. Ni silicides using stacked silicidation process
45
displaced, NiSi2(220) can be observed. Thus, it is expected that in-plane orientation
is random. Therefore, it is predict that the element which is cube-on-cube epitaxially
grown for Si substrate and the oriented element that (110) axis is distributed at
random in in-plane exist. However, NiSi2(200) peak can not be observed in = 15o
(figure 4.8 blue line). From this result, it is expected that the oriented element has a
texture that (111) axis is oriented to surface normal direction. In the crystal structure
of NiSi2 (Fluorite type structure), (111) plane is dense plane, it is suggested that this
orientation texture can be formed in addition to the epitaxial element as shown in
figure 4.10.
806040202 (deg)
Inte
nsi
ty (
a.u
.)
In-plane XRD500 oC, 1min in N2
= 15o
= 0o
Figure 4.8 In-plane XRD (2/ scan) profile of stacked silicide annealed at 500 oC
in = 0.3o. Red line is = 0o and blue line is = 15o. When is displaced to 15o,
NiSi2(200) peak can not be observed, on the other hand, NiSi2(220) peak can be
observed.
Page 50
Chapter 4. Ni silicides using stacked silicidation process
46
58.5 (deg)
59.0 59.5 60.0
Inte
ns
ity
(a.u
.)
Rocking curve at NiSi2(200)500 oC, 1min in N2
Rocking curve width (FWHM) = 0.63o
Figure 4.9 Rocking curve measurement ( scan) at NiSi2(200). Because rocking
curve width is about 0.6o which is narrow value, NiSi2 is epitaxially grown.
202 (deg)
40 60 80
Inte
nsi
ty (
a.u
.)
(001)-oriented: epitaxial
(111)-oriented: in-plane at random
In-plane XRD500 oC, 1min in N2
= 0o
Figure 4.10 The images of orientation of NiSi2 film. It is suggested that
(111)-oriented texture can be formed in addition to the epitaxial element.
Page 51
Chapter 4. Ni silicides using stacked silicidation process
47
4.3.3 XPS analysis of stacked silicide film
Ni 2p3/2 spectra of the samples annealed at various temperatures are shown
in figure 4.11. Stacked silicide showed similar peaks with 3.0-nm-thick-Ni, thus, the
phase of stacked silicide is NiSi2.
Ni 2p3/2 spectra of the stacked silicide annealing at 500 oC measured
changing photoelectron take-off angles (TOAs) from 30o to 80o are shown in figure
4.12. Inelastic mean free path () is calculated by TPP-2M. In this case, is equal to
9.6 nm. All spectra were close to the same each other independent of TOAs. From
the results of TEM images, XRD profiles and Ni 2p3/2 spectra, it is considered that
stacked silicide film is uniform and epitaxially grown NiSi2.
Binding energy (eV)851853855857
RTA : 1min in N2
h=7938.57eVNi2p3/2
500 oC
500 oC
tNi:5.5nm
tNi:3.0nm
tNi:3.0nm
Inte
nsi
ty (
a.u
.)
as depoNi
NiSi
NiSi2
500 oCNi/Si stack
TOA=80o
Figure 4.11 Ni 2p3/2 spectra of the silicide films annealed at 500 oC. The phase of
stacked silicide is NiSi2.
Page 52
Chapter 4. Ni silicides using stacked silicidation process
48
Binding energy (eV)851853855857
Inte
nsi
ty (
a.u
.)Ni2p3/2 TOA
80o
30o
NiSi2
Ni/Si stack
52o
40o
RTA : 500 oC, 1min in N2
h=7938.57eV
sin80o = 9.4 nm
sin40o = 6.2 nm
sin30o = 4.8 nm
sin52o = 7.5 nm
= 9.6 nm
Figure 4.12 Ni 2p3/2 spectra of stacked silicide annealed at 500 oC measured by
Angle Resolved-XPS (AR-XPS) changing TOAs from 30o to 80o. Stacked silicide film
is uniform NiSi2.
4.3.4 Annealing temperature dependent the phase of stacked silicide
Ni 2p3/2 spectra of stacked silicide annealed at various temperatures are
shown in figure 4.13. The phase of stacked silicide is Ni-rich silicide from as
deposited to 300 oC. At 325 oC, the phase of stacked silicide is Ni-rich silicide and
NiSi2. The Ni-rich silicide intensity decreased and NiSi2 intensity increased with
increase in annealing temperature, indicating that the residual Ni-rich silicide is
converted to NiSi2 by annealing. Therefore, the silicide phase change on annealing
temperature corresponds with sh of stacked silicide on annealing temperature. Then,
Ar 1s spectra of stacked silicide annealed at various temperatures are shown in figure
4.14. Ar intensity is large from as deposited to 300 oC. Over 325 oC, Ar intensity
Page 53
Chapter 4. Ni silicides using stacked silicidation process
49
decrease. This trend corresponds with the trend of sh. Therefore, it is speculated that
the decrease of Ar in stacked silicide film causes the decrease of sh, which means
formation of NiSi2. In the following chapter, the relation between the amount of Ar
in the stacked silicide film and the annealing temperature is investigated.
Binding energy (eV)851853855857
RTA : 1min in N2
h=7938.57eVNi2p3/2
325 oC
400 oC
300 oC
350 oC
Inte
nsi
ty (
a.u
.) 250 oC
Ni
Ni-rich
NiSi2800 oC
500 oC
TOA=80o
as depo
tNi:3.0nm as depo
n-Si(100)
Figure 4.13 Ni 2p3/2 spectra of stacked silicide on annealing temperature. The phase
of stacked silicide changes from Ni-rich silicide to NiSi2 with increase in annealing
temperature.
Page 54
Chapter 4. Ni silicides using stacked silicidation process
50
Binding energy (eV)319731993201
RTA : 1min in N2
h=7938.57eVAr1s
Inte
nsi
ty (
a.u
.)
TOA=80o
Ni/Si stack
325 oC
400 oC
300 oC
350 oC
250 oC
as depo
300
0
400
500
Sh
eet
resi
stan
ce
sh
(/s
q)
200
100
300 400Annealing temperature (oC)
500200
RTA : 1min in N2
1000
Figure 4.14 Ar 1s spectra of stacked silicide on annealing temperature. The
decreasing of Ar intensity is related to the decreasing of sh.
4.3.5 The effect of sputtering pressure on sheet resistance of stacked
silicide
As previously indicated, it is shown that there are Ar atoms into the silicide
film and NiSi2 is formed by desorption of Ar atoms from the silicide film with
annealing. Thus, in this section, stacked silicide is deposited in various sputtering
pressures to change the amount of Ar atoms in the silicide film. Thereby, the effect
of Ar atoms which are in the silicide film on the formation of NiSi2 is investigated.
The amount of Ar atoms in sputtering chamber by increasing sputtering pressure,
consequently, it is considered that the amount of Ar atoms in silicide film increases.
Also, there is a relationship between sputtering pressure and film properties, such as
surface morphology, crystallographic orientation and grain size [4.6, 4.7]. Therefore,
Page 55
Chapter 4. Ni silicides using stacked silicidation process
51
it is possible to relate to quality of NiSi2.
Figure 4.15 shows the sh of stacked silicide on annealing temperature deposited in
various sputtering pressures. The temperature of decreasing sh decreased with
decrease in sputtering pressure. The sample of 0.55 Pa achieves the lowest sh and
the lowest annealing temperature of formation of NiSi2. Because for the sample of
0.55 Pa, the amount of initial Ar atoms in silicide film is few in comparison to the
sample of 2 Pa, it can be formed NiSi2 at lower annealing temperature. Thus, it is
considered that NiSi2 can be formed at low temperature by decreasing sputtering
pressure to decrease the amount of Ar in the stacked silicide film.
The crystallinity of NiSi2 film dependent on sputtering pressure is discussed below.
Figure 4.16 shows XPS profile of stacked silicide which is deposited in 0.55 Pa
annealed at 500oC. NiSi2(004) peak can be detected at 2 = 70.50o. Whereat,
Rocking curve measurement ( scan) at 2 = 70.50o is shown in figure 4.17.
Because rocking curve width is about 0.2o which is narrow value, it is considered
that NiSi2 formed by stacked silicidation process is epitaxially grown. However, the
crystallinity of the sample of 2 Pa is well in comparison to the sample of 0.55 Pa
from the result of rocking curve width (figure 4.7). From the results of sh, it is
considered that NiSi2 is formed by desorption of Ar atom from stacked silicide film.
However, from the XRD profiles, the crystallinity of NiSi2 is good when the the
amount of Ar in the film is few. The relationship of these results has not cleared yet.
SIMS profile of Ar should be measured.
Page 56
Chapter 4. Ni silicides using stacked silicidation process
52
300
0
400
Sh
eet
resi
stan
ce
sh
(/s
q)
200
100
500
400 600Annealing temperature (oC)
800200
RTA : 1min in N2
0.55Pa
2Pa
1Pa
n-Si(100)
Figure 4.15 sh of stacked silicide on annealing temperature. sh of stacked silicide
is stable at wide process window. When the sputtering pressure is 0.55 Pa, sh
decrease occurs at the lowest annealing temperature.
Page 57
Chapter 4. Ni silicides using stacked silicidation process
53
727068662 (deg)
Inte
ns
ity
(a.u
.)
NiS
i 200
4Si 0
04
Out-of-plane XRD500 oC, 1min in N2
Figure 4.16 Out-of-plane XRD (2/ scan) profile of stacked silicide annealed at
500 oC. NiSi2(004) peak can be detected at 2 = 70.50o.
35.0 (deg)
35.1 35.2 35.3 35.4 35.5
10
20
30
40
50
Inte
nsi
ty (
a.u
.)
Rocking curve: 2 = 70.50o
500 oC, 1min in N2
Rocking curve width (FWHM)= 0.190o
Figure 4.17 Rocking curve measurement ( scan) at 2 = 70.50o. Because rocking
curve width is about 0.2o which is narrow value, it is considered that NiSi2 formed by
stacked silicidation process is epitaxially grown.
Page 58
Chapter 4. Ni silicides using stacked silicidation process
54
4.4 Stacked silicidation process of other semiconductor substrates
4.4.1 Characteristics of stacked silicide on different Si orientation
Figure 4.18 shows the sh of stacked silicide which is several thicknesses
deposited on various oriented Si substrates. Figure 4.11(a), (b) and (c) show Si(100),
Si(110) and Si(111), respectively. In these results, morphology of stacked silicide is
stable at wide temperature range independent of stacked silicide thickness and Si
substrate orientations. Therefore, it is considered that the stacked silicidation process
is promising for Si Fin or Si nanowire FETs.
Page 59
Chapter 4. Ni silicides using stacked silicidation process
55
Sh
eet
resi
stan
ce
sh(
/sq
)
400 600Annealing temperature (oC)
800200
RTA : 1min in N2
4 layer
16 layer
8 layer400
200
600
800
1000
0
・・・
n-Si(100)
4,8,16layer
(a)
Sh
eet
resi
stan
ce
sh(
/sq
)
400 600Annealing temperature (oC)
800200
RTA : 1min in N2
4 layer
16 layer
8 layer
400
200
600
800
1000
0
・・・
n-Si(110)
4,8,16layer
(b)
0
400
Sh
eet
resi
stan
ce
sh(
/sq
)
200
600
400 600Annealing temperature (oC)
800200
RTA : 1min in N2
4 layer
16 layer
8 layer
800
1000・・・
n-Si(111)
4,8,16layer
(c)
Figure 4.18 sh of different stacked silicide thickness on annealing temperature.
Each stacked silicide is deposited on (a) n-Si(100), (b) n-Si(110) and (c) n-Si(111)
substrate. sh of stacked silicide is stable at wide process window independent of Si
substrate orientation.
Page 60
Chapter 4. Ni silicides using stacked silicidation process
56
4.4.2 Characteristics of stacked silicide on other semiconductor
substrates
Germanium has been receiving attention as an alternative channel material
[4.8, 4.9] because of its high intrinsic mobility (two times higher for electrons and
four times higher for holes as compared to those in silicon). Reduction of parasitic
resistance of metallic contact on Ge substrate is one of the issues for Ge FETs, and
low contact resistance of NiGe with Ge substrate has been studied as metallic contact
on Ge substrate [4.10]. However, agglomeration of NiGe roughens metal/Ge
interface thereby increasing the sheet resistance at the interface [4.11]. Therefore, in
order to obtain resistant agglomeration compared to NiGe, Ni/Si stacked silicidation
process is applied for Ge substrate.
Figure 4.19 shows sh of stacked silicide on Ge substrate on annealing temperature.
Although small sheet resistance could be obtained by forming NiGe on Ni films,
process temperature were limited (Ni-5.5-nm film was from 250 oC to 375 oC) due to
agglomeration of the NiGe surface. On the other hand, once NiSi2 is formed over
350 oC, stable sheet resistances can be obtained up to 700 oC, which gives process
compatibility for dopant activation in Ge devices.
Page 61
Chapter 4. Ni silicides using stacked silicidation process
57
300
0
400
Sh
eet
resi
stan
ce
sh
(/s
q)
200
100
500
400 600Annealing temperature (oC)
800200
RTA : 1min in N2
tNi:5.5nm/Ge
agglomeration
stack/Si
stack/Ge
n-Ge(100)
Ni:5.5nm
n-Si(100)
Ni/Si stack
n-Ge(100)
Ni/Si stack
Figure 4.19 sh of stacked silicide on Ge substrate on annealing temperature. sh of
stacked silicide on Ge is more stable than that of 5.5-nm-thick Ni layer on Ge.
Page 62
Chapter 4. Ni silicides using stacked silicidation process
58
GaN based devices have been focused as a semiconductor for power
electronics applications [4.12]. One of the issues is that metal contact with GaN
based devices is degraded by surface agglomeration. Thus, it is proposed that
stacked silicidation process is applied for GaN based devices.
Figure 4.20 shows sh of stacked silicide on GaN and AlGaN substrates on
annealing temperature. It is considered that stable rsh can be obtained due to
suppression of interface reaction and formation NiSi2 at low temperature.
300
0
400
500
Sh
eet
resi
stan
ce
sh
(/s
q)
200
100
600
400 600Annealing temperature (oC)
800200
RTA : 1min in N2
GaN
AlGaN
n-Si (100) n-Si(100)GaNAlGaN
Ni/Si stack
Substrate
Figure 4.20 sh of stacked silicide on GaN and AlGaN substrates on annealing
temperature. sh of stacked silicide on each substrate is stable.
Page 63
Chapter 4. Ni silicides using stacked silicidation process
59
4.5 Extension of stacked silicidation process for Ti
TiSi2 is the most stable phases in Ti silicides, however, there are two crystal
structure in TiSi2. One is C49-TiSi2 and the other is C54-TiSi2 [4.13]. C54-TiSi2 is
the most stable phase in Ti silicides [4.14]. C54-TiSi2 has been used due to low
resistivity but there are some issues. One of the issues is that formation temperature
is high and the other is degradation of surface morphology by agglomeration [4.15].
As previous indicated, stacked silicidation process using Ni has some advantages
compared to conventional Ni silicidation process. Thus, it is investigated about
extension of stacked silicidation process for Ti as shown in figure 4.21.
Figure 4.22 shows sh of Ti silicide formed by stacked silicidation process and by
deposition 20-nm-thick Ti layer on annealing temperature. In 20-nm-thick Ti layer, it
is confirmed that sh decreases over 600 oC and further decreases at 800 oC that
correspond with formation of C49-TiSi2 and C54-TiSi2, respectively. On the other
hand, Ti/Si stacked silicidation process shows different trend to 20-nm-thick Ti layer.
Moreover, Ti/Si stacked silicide can not achieve stable sh at wide range temperature
range.
(corresponding to atomicconcentration of 2:1)
・・・
n-Si(100)
Si(1.1 nm)/Ti(0.5 nm)
Figure 4.21 Schematic illustration of Ti/Si stacked silicidation process. A set of Si/Ti,
with an atomic ratio of 2:1, is cyclically stacked on n-Si (100) substrates.
Page 64
Chapter 4. Ni silicides using stacked silicidation process
60
The reaction of Ti/Si stacked silicide is between thin-Ti-layer and thin-Si-layer, on
the other hand, the reaction of 20-nm-thick Ti layer is between thick-Ti-layer and
single crystal Si substrate. Therefore, it is considered that the phase or crystallinity of
these samples is different. However, the phase and crystallinity of Ti/Si stacked
silicide is not still measured. It is considered that to form the most stable silicide
phase by stacked silicidation process at wide process temperature range is unique
characteristics of Ni silicide.
40
0
60
Sh
eet
resi
stan
ce
sh
(/s
q)
20
80
400 600Annealing temperature (oC)
800200
RTA : 1min in N2
Ti/Si stack
tTi:20nm
1000
agglomeration
C54-TiSi2
C49-TiSi2
n-Si(100)
n-Si(100)
Ti:20nm
Figure 4.22 sh of Ti silicide which is formed by Ti/Si stacked silicidation process
and 20-nm-thick-Ti layer on annealing temperature.
Page 65
Chapter 4. Ni silicides using stacked silicidation process
61
4.6 Conclusion
In order to achieve the control of interface reaction and stable composition
and morphology at wide temperature range, stacked silicidation process has been
investigated. It is realized that an atomically flat interface and surface are formed
before and after annealing and Ni atoms encroachment into Si Fin is suppressed
completely. In fact, it is an advantage for scaled 3D devices that the shape of Si
substrate after silicidation does not change due to suppression of interface reaction.
Second, it is achieved that NiSi2 which is formed by staked silicidation process is
stable composition and morphology at wide temperature range. Moreover, it is
suggested that NiSi2 formation is advanced by desorption of Ar atoms which are in
silicide films.
Third, it is accomplished that the sh of stacked silicide on various substrates is
stable at wide temperature range. Stacked silicidation process can be applied for 3D
Si channel and other semiconductor substrates.
And finally, extension of stacked silicidation process for Ti has been examined. It is
considered that to form the most stable silicide phase by stacked silicidation process
at wide process temperature range is unique characteristics of Ni silicide.
As discussed above, it is considered that Ni/Si stacked silicidation process is the
key for future scaled 3D SB-FET.
Page 66
Chapter 4. Ni silicides using stacked silicidation process
62
References
[4.1] M. Koyama, N. Shigemori, K. Ozawa, K. Tachi, K. Kakushima, O. Nakatsuka,
K. Ohmori, K. Tsutsui, A. Nishiyama, N. Sugii, K. Yamada and H. Iwai,
“Si/Ni-Silicide Schottky Junctions with Atomically Flat Interfaces using NiSi2
Source”, Proc. 41st ESSDERC, pp.231-234 (2011).
[4.2] K. De Keyser, C. Van Bockstael, R. L. Van Meirhaeghe, C. Detavernier, E.
Verleysen, H. Bender, W. Vandervorst, J. Jordan-Sweet, and C. Lavoie, “Phase
formation and thermal stability of ultrathin nickel-silicides on Si(100)”, Appl. Phys.
Lett., 96, pp.173503 (2010).
[4.3] O. Nakatsuka, A. Suzuki, S. Akimoto, A. Sakai, M. Ogawa and S. Zaima,
“Dependence of Electrical Characteristics on Interfacial Structure of Epitaxial
NiSi2/Si Schottky Contacts Formed from Ni/Ti/Si System”, J. J. Appl. Phys., 47,
pp.2402-2406 (2008).
[4.4] H. Arai, H. Kamimura, S. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii,
K. Natori, T. Hattori, H. Iwai, ” Annealing Reaction for Ni Silicidation of Si
Nanowire”, ECS Trans., 25, pp.447-454 (2009).
[4.5] N. Shigemori, S. Satou, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.
Sugii, K. Natori, T. Hattori, H. Iwai, “Suppression of Lateral Encroachment of Ni
Silicide into Si Nanowires using Nitrogen Incorporation”, ECS Trans., 33, pp.19-26
(2011).
[4.6] John A. Thornton, “Influence of apparatus geometry and deposition conditions
on the structure and topography of thick sputtered coatings”, J. Vac. Sci. Technol., 11,
pp.666-670 (1974).
Page 67
Chapter 4. Ni silicides using stacked silicidation process
63
[4.7] John A. Thornton, “The microstructure of sputter-deposited coatings”, J. Vac.
Sci. Technol. A, 4, pp.3059-3065 (1986).
[4.8] A. Ritenour, S. Yu, M. L. Lee, N. Lu, W. Bai, A. Pitera, E. A. Fitzgerald, D. L.
Kwong, and D. A. Antoniadis, “Epitaxial strained germanium p-MOSFETs with
HfO2 gate dielectric and TaN gate electrode”, IEDM Tech. Dig., pp.433 (2003).
[4.9] C. O. Chui, S. Ramanathan, B. B. Triplet, P. C. McIntyre, and K. C. Saraswat,
“Germanium MOS Capacitors Incorporating Ultrathin High-k Gate Dielectric”,
IEEE Electron Device Lett., 23, pp.473 (2002).
[4.10] X. V. Li, M. K. Husain, M. Kiziroglou, and C.H. de Groot, “Inhomogeneous
Ni/Ge Schottky barriers due to variation in Fermi-level pinning”, Microelectronic
Engineering, 86, pp.1599-1602 (2009).
[4.11] Q. Zhang, N. Wu, T. Osipowicz, L. K. Bera, and C. Zhu, “Formation and
Thermal Stability of Nickel Germanide on Germanium Substrate”, J. J. Appl. Phys.,
pp.44, L1389-L1391 (2005).
[4.12] O. Ambacher, “Growth and applications of Group III-nitrides”, J. Phys. D, 31,
pp.2653-2710 (1998).
[4.13] L. J. Chen, “Silicide Technology for Integrated Circuits”, The Institution of
Electrical Engineers, London (2004).
[4.14] K. L. Saenger, C. Cabral, Jr., L. A. Clevenger, R. A. Roy and S. Wind, “A
kinetic study of the C49 to C54 TiSi2 conversion using electrical resistivity
measurements on single narrow lines”, J. Appl. Phys., 78, pp.7040-7044 (1995).
[4.15] T. P. Nolan and R. Sinclair, R. Beyers, “Modeling of agglomeration in
polycrystalline thin films: Application to TiSi2 on a silicon substrate”, J. Appl. Phys.,
71, pp.720-724 (1992).
Page 68
Chapter 5. Electrical characteristics of Ni silicide Schottky diodes
64
Chapter 5 Electrical characteristics of Ni
silicide Schottky diodes
5.1 Introduction
5.2 Schottky diode characteristics
5.3 TiN capping on stacked silicides
5.4 Conclusion
References
Page 69
Chapter 5. Electrical characteristics of Ni silicide Schottky diodes
65
5.1 Introduction
In chapter 3 and 4, the physical properties of silicide films, which are
formed by different methods, such as interface reaction, composition and
morphology are examined. In this chapter, the electrical characteristics of Schottky
diodes which are formed by those silicides are investigated.
There are some problems in Ni silicide Schottky diodes [5.1]. One is increasing the
reverse leakage current because of the leakage current at the electrode periphery
where excess silicidation occurs, and the other is the variation of Bn and n-factor
due to existing on roughness and facets at the interface and the electrode periphery.
Thus, to obtain the ideal Schottky diode characteristics, it is necessary to achieve an
atomically flat interface including the electrode periphery. In this chapter, therefore,
Schottky diode characteristics using stacked silicidation process which can be
obtained an atomically flat interface are investigated.
(a) 350 oC (b) 350 oC
(c) 750 oC
Figure 5.1 The presence of facets and roughness which occur leakage currents at
interface and periphery [5.1].
Page 70
Chapter 5. Electrical characteristics of Ni silicide Schottky diodes
66
5.2 Schottky diode characteristics
Figure 5.2 shows diode current density-voltage (J-V) characteristics of the
fabricated Ni silicide Schottky diodes. For 3-nm-thick and 5.5-nm-thick Ni samples,
the increase of reverse current from theoretical value was observed. On the other
hand, for stacked silicide, the increase of reverse current from theoretical was not
observed. Figure 5.3 shows Bn and ideality factor (n-factor) extracted by J-V
characteristics on annealing temperature. For stacked silicide, it is observed that Bn
is stable value 0.61 ~ 0.63 eV and n-factor is less than 1.05 up to 700 oC. On the
other hand, for 3.0-nm-thick and 5.5-nm-thick Ni samples, Bn was not stable and
n-factor was worse than that of stacked silicide. From these results, it is considered
that these differentials between stacked silicide and conventional silicides depend on
a method of silicide formation. For conventional silicide which formed by reacting
between Ni film and Si substrate, issues of interface reaction such as excessive
growth of silicide at the periphery of the electrodes and formation of plane
orientation which is not Si(100) existed [5.1, 5.2]. Thereby, it is considered that
increasing reverse current from theoretical value and variation of Bn and n-factor
occurred. On the other hand, for stacked silicide, issues of interface such as
conventional silicide did not occur because stacked silicide was able to form
suppressing the reaction with Si substrate as shown in figure 4.1. Using stacked
silicide, the issues of conventional silicide are overcome.
Page 71
Chapter 5. Electrical characteristics of Ni silicide Schottky diodes
67
increase10-1
10-2
10-3
10-4
Cu
rren
t d
ensi
ty (
A/c
m2 )
-1.0 0 0.2Applied voltage (V)
-0.6 -0.2
tNi:3.0nm
RTA : 500 oC, 1min in N2
theoretical value
tNi:5.5nm
Ni/Si stack
0.54 eV
0.63 eV
0.56 eV
No increasen-Si(100)
n-Si(100)
Ni:3.0nm
n-Si(100)
Ni:5.5nm
Figure 5.2 The Schottky diode J-V characteristics of stacked silicide, 3.0-nm- and
5.5-nm-thick Ni layers. J-V characteristic of stacked silicide is ideal.
Bn
(eV
)
1.00
0.50
1.10
n-f
acto
r
1.20
400 600Annealing temperature (oC)
800200
0.60
0.70
RTA : 1min in N2
n-Si(100)
n-Si(100)
Ni:3.0nm
n-Si(100)
Ni:5.5nm
Figure 5.3 Bn and n-factor of stacked silicide, 3.0-nm- and 5.5-nm-thick Ni layers
on annealing temperature. Bn and n-factor of stacked silicide are stable value up to
700 oC.
Page 72
Chapter 5. Electrical characteristics of Ni silicide Schottky diodes
68
5.3 TiN capping on stacked silicide
Ni silicides should be protected by etchant, which is used in etching process,
in fabrication process of transistors because Ni silicides can be etched by HF [5.3].
Then, the protection of Ni silicides by TiN capping is proposed. In this section, the
effect of TiN capping on electrical characteristics is stated.
Figure 5.4 shows the fabrication procedures of Schottky diodes with or
without TiN capping. 50-nm-TiN layer is deposited by sputtering.
Figure 5.5 shows J-V characteristics of diodes with or without TiN capping. It is
clear that J-V characteristics remain ideal even with TiN capping. However, Bn of
with TiN capping is a little bit larger than that of without TiN capping. Figure 5.6
shows Bn and ideality factor (n-factor) extracted by J-V characteristics on annealing
temperature. It is investigated that stable Bn and n-factor remain even with TiN
capping, furthermore, scatter of Bn and n-factor with TiN capping is suppressed
compared with without TiN capping. Therefore, it is considered that TiN capping on
stacked silicide does not degrade electrical characteristics of Schottky diode.
n-Si(100)
SiO2 SiO2
Al
Stacked silicide
without TiN capping
n-Si(100)
SiO2 SiO2
Al
TiN
with TiN capping
SPM and HF cleaning
Ni/Si stacked deposition by RF sputtering in Ar
Silicidation by RTA in N2
Diode patterning
Backside Al contact
BHF etching of SiO2
Lift-off
n-Si(100) Sub with 400 nm SiO2 (3x1015 cm-3)
TiN deposition by RF sputtering in Ar:N2=8:2
Figure 5.4 Fabrication processes of Schottky diodes with or without TiN capping.
Page 73
Chapter 5. Electrical characteristics of Ni silicide Schottky diodes
69
10-1
10-2
10-3
10-4
Cu
rren
t d
ensi
ty (
A/c
m2 )
-1.0 0 0.2Applied voltage (V)
-0.6 -0.2
RTA : 500 oC, 1min in N2
w/o TiN
w TiN0.65 eV
0.63 eV
10-5
10-6
n-Si(100)
Ni/Si stack
n-Si(100)
Ni/Si stack
TiN
Figure 5.5 The Schottky diode J-V characteristics of stacked silicide with or without
TiN capping. J-V characteristics remain ideal characteristics even with TiN capping.
Bn
(eV
)
1.00
0.50
1.10
n-f
acto
r
1.20
400 600Annealing temperature (oC)
800200
0.60
0.70
RTA : 1min in N2
0
n-Si(100)
Ni/Si stack
n-Si(100)
Ni/Si stack
TiN
Figure 5.6 Bn and n-factor of stacked silicide with or without TiN capping on
annealing temperature. Scatter of Bn and n-factor with TiN capping is suppressed
compared with without TiN capping.
Page 74
Chapter 5. Electrical characteristics of Ni silicide Schottky diodes
70
5.4 Conclusion
Electrical characteristics of Schottky diodes using Ni silicides are
investigated. Schottky diode characteristics of conventional Ni silicides show the
reverse leakage current and the variation of Bn and n-factor due to excess
silicidation at the electrode periphery. On the other hand, those of stacked silicide are
achieved ideal diode characteristics and robust Bn and n-factor because of formation
of an atomically flat interface including the electrode periphery. Moreover, more
robust Bn and n-factor even with ideal J-V characteristics are obtained by TiN
capping on stacked silicide.
References
[5.1] O. Nakatsuka, A. Suzuki, S. Akimoto, A. Sakai, M. Ogawa and S. Zaima,
“Dependence of Electrical Characteristics on Interfacial Structure of Epitaxial
NiSi2/Si Schottky Contacts Formed from Ni/Ti/Si System”, J. J. Appl. Phys., 47,
pp.2402-2406 (2008).
[5.2] L. Knoll, Q. T. Zhao, S. Habicht, C. Urban, B. Ghyselen, and S. Mantl,
“Ultrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained
Silicon”, IEEE Electron Devices Lett., 31, pp.350-352 (2010).
[5.3] S. P. Murarka, “SILICIDES FOR VLSI APPLICATIONS”, Academic Press,
New York (1983).
Page 75
Chapter 6. Schottky barrier height modulation
71
Chapter 6 Schottky barrier height modulation
6.1 Introduction
6.2 Bn modulation with stacked silicidation process
6.3 Bn controllability by impurity incorporation
6.4 Conclusion
References
Page 76
Chapter 6. Schottky barrier height modulation
72
6.1 Introduction
As described in chapter 1, it is necessary to modulate B to achieve SB-FET
with high performance [6.1]. B modulation has been achieved by dopant segregation
using ion implantation, however, there are some issues [6.2, 6.3]. Thereby, it is
proposed that the method of impurity incorporation without ion implantation, and B
modulation by the impurity incorporation is examined.
In this study, P and B are used as impurity. It is reported that Bn becomes small
value by P and Bn becomes large value by B [6.4, 6.5]. The method of impurity
incorporation with stacked silicidation process is to deposit Ni3P or B by sputtering.
For B incorporation, pure B target is used for sputtering, whereas for P case, a
0.68-nm-thick Ni3P layer is deposited instead of the first 0.5-nm-thick Ni layer as
shown in figure 6.1. The number of Ni atoms in 0.68-nm-thick-Ni3P layer equals that
of 0.5-nm-thick Ni layer. This method can incorporate impurity without ion
implantation, moreover, the control of impurity position is expected because stacked
silicidation process can suppress interface reaction.
In this chapter, interface reaction with impurity incorporation at the interface,
impurity profiles and electrical characteristics with impurity incorporation are
investigated. Furthermore, Bn modulation depending on impurity position and
amount are examined.
Page 77
Chapter 6. Schottky barrier height modulation
73
・・・
n-Si(100)
Ni3P(0.68 nm)
Si(1.9nm)/Ni(0.5nm)
x 7 layers
・・・
n-Si(100)
B(0.13 nm)
Si(1.9nm)/Ni(0.5nm)
x 8 layers
impurity process
P (Ni/Si)x7+(Ni3P/Si)
B (Ni/Si)x8+B
impurity process
P (Ni/Si)x7+(Ni3P/Si)
B (Ni/Si)x8+B
Figure 6.1 Schematic illustration of stacked silicidation process with impurity
incorporation. P is incorporated at the interface by 0.68-nm-thick Ni3P deposition
instead of the first Ni layer. B is incorporated at the interface.
Page 78
Chapter 6. Schottky barrier height modulation
74
6.2 Bn modulation with stacked silicidation process
6.2.1 Interface reaction of impurity incorporation
As shown in figure 6.2, TEM images of silicide/Si interface formed from
Ni/Si stacked silicidation process incorporated P (Figure 6.2(a)) and B (Figure
6.2(b)) at the interface at annealed 500 oC for 1 min in N2 ambient. TEM images
revealed no change in the thickness and atomically flat interface and surface. Even
with impurity incorporation, the interface reaction with stacked silicidation process
is also maintained.
10nm
Si(100)
(a) P incorporated
RTA: 500 oC
10nm
Si(100)
(b) B incorporated
RTA: 500 oC
Figure 6.2 TEM images of stacked silicidation process incorporated (a) P and (b) B
at the interface after annealing at 500 oC. Even with impurity incorporation,
atomically flat interface and surface are maintained.
Page 79
Chapter 6. Schottky barrier height modulation
75
6.2.2 SIMS impurity profiles
Figure 6.3 shows SIMS profiles of (a) P and (b) B before and after
annealing when impurities incorporated at interface. Although some of the impurities
diffused into silicide layer, significant amount of them remained at the silicide/Si
interface which is initial incorporated position. Therefore, impurity position can be
controlled by stacked silicidation process because stacked silicidation process can be
suppressed interface reaction.
1019
10 200
1020
1021
1022
NiSi2 Si Sub.
P c
on
cen
trat
ion
(cm
-3)
Depth (nm)
as depo
500 oC
P
n-Si(100)P
NiSi2
(a)
1018
10 200
1019
1020
1021
Si Sub.
B c
on
cen
trat
ion
(cm
-3)
Depth (nm)
as depo
500 oC
B
NiSi2
n-Si(100)B
NiSi2
(b)
Figure 6.3 SIMS profiles of (a) P and (b) B before and after annealing. Although
some of the impurities diffused into silicide layer, significant amount of them
remained at silicide/Si interface.
Page 80
Chapter 6. Schottky barrier height modulation
76
6.2.3 Bn modulation by impurity incorporation
Figure 6.4 shows the J-V characteristics of the stacked silicide Schottky
diodes with P and B incorporation annealed at 500 oC. Bn can be effectively
modulated by placing P or B atoms at the interface, where the initial Bn of 0.63 eV
was modulated to ohmic and 0.68 eV, respectively. Furthermore, robust Bn and
n-factor were obtained at wide process window as shown in figure 6.5.
104
102
10-2
10-4
-1.0 -0.5 0 0.5 1.0
Cu
rre
nt
den
sity
(A
/cm
2 )
Applied voltage (V)
100
Control: 0.63 eV
P: Ohmic
B: 0.68 eV
RTA : 500oC, 1min in N2
10-6
n-Si(100)
NiSi2
n-Si(100)P
NiSi2
n-Si(100)B
NiSi2
Figure 6.4 J-V characteristics of stacked silicide with P and B incorporation
annealed at 500 oC. Successful effectively Bn shift by P or B incorporation with
stacked silicidation process.
Page 81
Chapter 6. Schottky barrier height modulation
77
Bn
(eV
)
1.00
0.80
1.10
n-f
acto
r
1.20
400 600Annealing temperature (oC)
800200
0.60
RTA : 1min in N2
P: Ohmic
Control
B
Control
B
0.40
n-Si(100)
NiSi2
n-Si(100)B
NiSi2
Figure 6.5 Bn and n-factor of the diodes extracted from J-V characteristics
depending on annealing temperature. Ohmic characteristic and larger Bn is realized
by incorporating P and B, respectively. Bn and n-factor were stable up to 700 oC.
Page 82
Chapter 6. Schottky barrier height modulation
78
6.3 Bn controllability by impurity incorporation
6.3.1 Annealing conditions dependent J-V characteristics with impurity
at the interface
Figure 6.6 shows J-V characteristics of stacked silicide incorporated P at the
interface annealed at (a) 400 oC, (b) 500 oC and (c) 600 oC for 1 min and 30 min. As
shown in figure 6.6(a), annealed at 400 oC, large current density can be obtained by
annealing for 30 min compared to the sample annealed for 1 min. On the other hand,
current density is almost unchanged annealed 500 oC and 600 oC independent of
annealing time. Therefore, large current density can be achieved by long time or high
temperature annealing.
Page 83
Chapter 6. Schottky barrier height modulation
79
10-1
-1.0 -0.5 0 0.5 1.0
Cu
rren
t d
ensi
ty (
A/c
m2 )
Applied voltage (V)
30min
RTA : 400oC in N2102
10-2
1min101
100
(a)
n-Si(100)P
NiSi2
10-1
-1.0 -0.5 0 0.5 1.0
Cu
rren
t d
ensi
ty (
A/c
m2 )
Applied voltage (V)
30min
RTA : 600oC in N2102
10-2
1min101
100
(c)
n-Si(100)P
NiSi2
10-1
-1.0 -0.5 0 0.5 1.0
Cu
rren
t d
ensi
ty (
A/c
m2 )
Applied voltage (V)
30min
RTA : 500oC in N2102
10-2
1min101
100
(b)
n-Si(100)P
NiSi2
Figure 6.6 J-V characteristics of stacked silicide incorporated P at the interface
annealed at (a) 400 oC, (b) 500 oC and (c) 600 oC for 1 and 30 min. Ohmic
characteristics can be achieved by long time or high temperature annealing.
6.3.2 Impurity position dependent J-V characteristics
As shown in figure 6.6, when P is incorporated at the interface, ohmic
characteristics can be obtained by annealing at 500 oC for 1min. In this chapter, the
impurity position dependent J-V characteristics investigated. Figure 6.7 shows J-V
characteristics of stacked silicide depending on the position of P incorporation
annealed at 500 oC for 1 min. When the position of P incorporation gradually comes
Page 84
Chapter 6. Schottky barrier height modulation
80
10-3
-1.0 -0.5 0 0.5 1.0
Cu
rren
t d
ensi
ty (
A/c
m2 )
Applied voltage (V)
10-1
Control
P1
RTA : 500oC, 1min in N2
101
10-5
P3
P5
n-Si(100)
NiSi2
n-Si(100)P1
NiSi2
n-Si(100)
P3NiSi2
n-Si(100)
P5NiSi2
Figure 6.7 J-V characteristics of stacked silicide dependent the position of P
incorporation annealed at 500 oC. When the position of P incorporation gradually
comes close to the interface, small Bn and ohmic characteristic are obtained.
close to the interface, small Bn and ohmic characteristic are obtained. Therefore, it is
considered that P which exists at interface is the key to modulate Bn.
6.3.3 Annealing conditions dependent J-V characteristics with impurity
far from the interface
Figure 6.8 shows J-V characteristics of stacked silicide incorporated P far
from the interface annealed at (a) 400 oC, (b) 500 oC and (c) 600 oC for 1 min and 30
min. As shown in figure 6.8(a), which is annealed at 400 oC, J-V characteristics are
Schottky characteristics both of annealing for 1min and 30 min, however, Bn of 30
min is smaller than that of 1 min. On the other hand, Ohmic characteristics are
obtained by annealing for 30 min at 500 oC and 600 oC as shown in figure 6.8(b) and
Page 85
Chapter 6. Schottky barrier height modulation
81
(c), respectively. Therefore, it is realized that Bn modulation and ohmic
characteristics can be achieved even with the position of P incorporation far from the
interface because P atoms are diffused by high temperature or long time annealing
and arrive at interface as shown figure 6.8(d).
10-1
-1.0 -0.5 0 0.5 1.0
Cu
rren
t d
ensi
ty (
A/c
m2 )
Applied voltage (V)
30min
RTA : 500oC in N2102
10-2
1min
101
100
10-3
10-4
(b)
10-1
-1.0 -0.5 0 0.5 1.0
Cu
rren
t d
ensi
ty (
A/c
m2 )
Applied voltage (V)
30min
RTA : 600oC in N2102
10-2
1min
101
100
10-3
10-4
(c)
10-1
-1.0 -0.5 0 0.5 1.0
Cu
rren
t d
ensi
ty (
A/c
m2 )
Applied voltage (V)
30min
RTA : 400oC in N2102
10-2
1min
101
100
10-3
10-4
(a)
n-Si(100)
P
NiSi2
n-Si(100)
PAnnealing
(d)
Figure 6.8 J-V characteristics of stacked silicide incorporated P far from the
interface annealed at (a) 400 oC, (b) 500 oC and (c) 600 oC for 1 min and 30 min. (d)
the image of P diffusion by annealing. Ohmic characteristics can be achieved by
long time or high temperature annealing.
Page 86
Chapter 6. Schottky barrier height modulation
82
Finally, electrical characteristics of P incorporation depending on
incorporated position and annealing temperature and time are summarized as shown
in table 6.1, and here the origin of Bn modulation is discussed. One of the origins is
the formation of a dipole which is generated from dopant at the silicide/Si interface
as shown in figure 6.9 [6.4]. The other of the origins is the change of silicide work
function by impurity doping into silicide [6.5]. As the result of table 6.1, it is
considered that the origin of Bn modulation is not so much the change of silicide
work function as the presence of impurities at the interface in using stacked
silicidation process.
Table 6.1 Electrical characteristics of P incorporation depending on incorporated
position and annealing temperature and time
300
P7400
500
300
P1400
500
600
300
P3400
500
600
300
P5500
600
Sample10 20
600
400
30・・・10
Annealing time (min)Annealing temperature (oC)
300
P7400
500
300
P1400
500
600
300
P3400
500
600
300
P5500
600
Sample10 20
600
400
30・・・10
Annealing time (min)Annealing temperature (oC)
Ohmic
Schottky
Page 87
Chapter 6. Schottky barrier height modulation
83
Figure 6.9 Schematic images of interface dipole model [6.4].
6.3.4 Impurity amount dependent diode characteristics
In the previous chapters, it is investigated that impurities which exist at the
interface cause Bn modulation. In this chapter, it is stated that impurity amount
dependent diode characteristics. Figure 6.10 shows J-V characteristics of stacked
silicide dependent the amount of B incorporation at the interface annealed at 500 oC
for 1 min. Reverse currents decrease with increasing the amount of B incorporation
at the interface compared to control sample. In addition, figure 6.11 shows Bn of the
diodes extracted from J-V characteristics depending on the amount of B
incorporation at the interface. Large Bn modulation can be achieved by increasing
the amount of B incorporation at the interface. Therefore, effective Bn modulation is
controlled by controlling the amount of B atoms which exist at interface.
Page 88
Chapter 6. Schottky barrier height modulation
84
101
10-5
10-7
-1.0 -0.5 0 0.5 1.0
Cu
rren
t d
ensi
ty (
A/c
m2 )
Applied voltage (V)
10-3
RTA : 500oC, 1min in N2
10-9
10-1
B:2.6nm
n-Si(100)
NiSi2
B:0.065nmn-Si(100)
NiSi2
n-Si(100)
NiSi2B:0.13nm
n-Si(100)
NiSi2B:0.26nm
n-Si(100)
NiSi2
Control
Figure 6.10 J-V characteristics of stacked silicide dependent the amount of B
incorporation at the interface annealed at 500 oC. Bn can be controlled by the
amount of B incorporation.
Bn
(eV
)
0.90
0.80
0.70
RTA : 500oC, 1min in N20.60
0 0.01 0.1 1B incorporation amount (nm)
1.0010
Figure 6.11 Bn of the diodes extracted from J-V characteristics depending on the
amount of B incorporation at the interface. Large Bn modulation can be achieved by
increasing the amount of B incorporation at the interface.
Page 89
Chapter 6. Schottky barrier height modulation
85
6.4 Conclusion
The effect of impurity incorporation on Bn is investigated. At first, even
with impurity incorporation, the interface reaction with stacked silicidation process
is also maintained. Second, it is obtained that the significant amount of the
impurities remained at the initial incorporated position due to suppression of
interface reaction. Further, effective Bn modulation is achieved by impurity
incorporation at interface with stacked silicidation process. Moreover, impurity
incorporation position and amount dependent Bn modulation is examined. As a
result, the main fact of Bn modulation is that impurity exists at the interface.
Additionally, it is found that Bn modulation is controlled by controlling the amount
of impurity which exists at interface.
Page 90
Chapter 6. Schottky barrier height modulation
86
References
[6.1] W. Mizubayashi, S. Migita, Y. Morita, and H. Ota, “Exact Control of Junction
Position and Schottky Barrier Height in Dopant-Segregated Epitaxial NiSi2 for High
Performance Metal Source/Drain MOSFETs”, Symp. on VLSI Tech. Dig., pp.88-89
(2011).
[6.2] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida and J. Koga, “Solution for
High-Performance Schottky-Source/Drain MOSFETs: Schottky Barrier Height
Engineering with Dopant Segregation Technique”, Symp. on VLSI Tech. Dig.,
pp.168-169 (2004).
[6.3] N. Mise, S. Migita, Y. Watanabe, H. Satake, T. Nabatame and A. Toriumi,
“(111)-Faceted Metal Source and Drain for Aggressively Scaled Metal/High-k
MISFETs”, IEEE Trans. Electron Devices, 55, pp.1244-12498 (2008).
[6.4] T. Yamauchi, Y. Nishi, Y. Tsuchiya, A. Kinoshita, J. Koga and K. Kato, “Novel
doping technology for a 1nm NiSi/Si junction with dipoles coforting Schottky (DSC)
barrier”, IEDM Tech. Dig., pp.963-966 (2007).
[6.5] T. Nakayama, K. Kakushima, O. Nakatsuka, Y. Machida, S. Sotome, T.
Matsuki, K. Ohmori, H. Iwai, S. Zaima, T. Chikyow, K. Shiraishi and K. Yamada,
“Theory of Workfunction Control of silicides by Doping for Future Si-Nano-Devices
based on Fundamental Physics of Why Silicides Exist in Nature”, IEDM Tech. Dig.,
pp.375-378 (2010).
Page 91
Chapter 7 Demonstration of Schottky barrier S/D FET with barrier height modulation
87
Chapter 7 Demonstration of Schottky barrier
S/D FET with barrier height modulation
7.1 Introduction
7.2 Fabrication process
7.3 Electrical characteristics for SB-FET
7.4 Conclusion
References
Page 92
Chapter 7 Demonstration of Schottky barrier S/D FET with barrier height modulation
88
7.1 Introduction
As described above, it is considered that stacked silicidation process with
impurity incorporation is the key to achieve the future scaled 3D SB-FETs. In this
chapter, SB-FET using stacked silicidation process with Bn modulation is
demonstrated. Then, the effect of Bn modulation on the device characteristics is
investigated.
7.2 Fabrication process
SB-FET using the stacked silicide with B or P incorporation at S/D was
fabricated on a SOI wafer as shown in figure 7.1. After SOI patterning, gate oxide
was formed by thermal oxidation in 1000 oC. To form S/D, stacked silicidation
process with impurity incorporation was performed. SiO2 was deposited by plasma
CVD (TEOS) owing to passivation. After gate metal deposition and etching, Al was
deposited as contact by vacuum evaporation. Finally, annealing was performed at
500 oC in forming gas (F.G.) (N2:H2=97:3), so that the effect of terminating the
dangling bonds with H+ at the interface of oxide/Si substrate is obtained. Therefore,
this process can achieve a process temperature below 500 oC, except for the gate
oxidation.
Page 93
Chapter 7 Demonstration of Schottky barrier S/D FET with barrier height modulation
89
BOXSOI
stackedsilicide
metaloxide
Fabrication process
SOI patterningGate oxide (1000 oC)Stacked silicide for S/D
TEOS (200 oC)Gate metal depo./etch.ContactFG anneal (500 oC)
(with B or P)
The process temperature was set below 500 oC except for gate oxide formation.
Figure 7.1 Fabrication process of Schottky S/D FET.
7.3 Electrical characteristics for SB-FET
Id-Vg characteristics are shown in figure 7.2. B incorporated device showed
ambipolar characteristics. On the other hand, P incorporated device can suppress
ambipolar characteristics with lower Bn, moreover, improvement in the on-current
(Vg=Vd=3V) also supports the Bn modulating. The schematic illustration of band
diagram for operation is shown in figure 7.3 [7.1, 7.2, 7.3].
Page 94
Chapter 7 Demonstration of Schottky barrier S/D FET with barrier height modulation
90
-3 -2 -1 0 1 2 3Gate voltage (V)
10-5
10-7
10-11
10-13
Dra
in c
urr
ent
(A)
10-9Vd = 3 V
Vd = 3 V
Vd = 0.1 V
W/L=6.0/1.5mtSi=30nmtox=76nm
Vd = 0.1 V
PB
n-Si(100)B
NiSi2
n-Si(100)P
NiSi2
Figure 7.2 Id-Vg characteristics of SB-FET with Bn modulated stacked silicide. P
incorporated device shows larger on-current with suppressed ambipolar
characteristics.
Vd=0.1V
Vd=3.0V
ambipolar
with B
with P
(Vg=3.0V) (Vg=-3.0V)(a) ON (b) OFF
S
S
S
S
D
D
D
D
Figure 7.3 Band diagram of the SB-FET at (a) on and (b) off-states with different Bn.
Ambipolar characteristics are suppressed and larger on-current is obtained by
modulating Bn to smaller value.
Page 95
Chapter 7 Demonstration of Schottky barrier S/D FET with barrier height modulation
91
7.4 Conclusion
SB-FETs using stacked silicidation process with B or P incorporation at S/D
were fabricated below 500 oC except for the gate oxidation. The effect of Bn
modulation on the device characteristics is confirmed. It is considered that ambipolar
characteristics are suppressed and on-current is improved because Bn is modulated
to small value. It is necessary for high performance to modulate Bn to smaller value.
References
[7.1] M. Zhang, J. Knoch, Q. T. Zhao, U. Breuer and S. Mantl, “Impact of dopant
segregation on fully depleted Schottky-barrier SOI-MOSFETs”, Solid-State
Electron., 50, pp.594-600 (2006).
[7.2] C. Urban, C. Sandow, Q. T. Zhao, J. Knoch, S. Lenk, S. Mantl, “Systematic
study of Schottky barrier MOSFETs with dopant segregation on thin-body SOI”,
Solid-State Electron., 54, pp.185-190 (2010).
[7.3] L. E. Calvet, H. Luebben and M. A. Reed, C. Wang, J. P. Snyder, J. R. Tucker,
“Suppression of leakage current in Schottky barrier matal-oxide-semiconductor
field-effect transistors”, J. Appl. Phys., 91, pp.757-759 (2002).
Page 96
Chapter 8. Conclusions
92
Chapter 8 Conclusions
Page 97
Chapter 8. Conclusions
93
In this thesis, a novel stacked silicidation process is proposed for future
scaled 3D devices. In this chapter, the studies are summarized below.
(i) Thickness dependent characteristics of Ni silicides (chapter 3)
Ni silicides, reactively formed by 3.0-nm-thick Ni, have shown a stable
sheet resistance, flat morphology against annealing temperature up to 800 oC
compared to those formed with thicker Ni film. These properties are owing to the
formation of stable NiSi2 phase at a temperature as low as 500 oC.
(ii) Ni silicides using stacked silicidation process (chapter 4)
In order to achieve the control of interface reaction and stable composition
and morphology at wide temperature range, stacked silicidation process has been
investigated. It is realized that an atomically flat interface and surface are formed
before and after annealing and Ni atoms encroachment into Si Fin is suppressed
completely. Further, it is achieved that NiSi2 which is formed by staked silicidation
process is stable composition and morphology at wide temperature range. Moreover,
it is accomplished that the sh of stacked silicide on various substrates is stable at
wide temperature range. On the other hand, extension of stacked silicidation process
for Ti has been examined. It is considered that the formation of the most stable
silicide phase, such as NiSi2, can be formed by stacked silicidation process at low
temperature is unique characteristics of Ni silicide.
(iii) Electrical characteristics of Ni silicide Schottky diodes (chapter 5)
Electrical characteristics of Schottky diodes using Ni silicides are
investigated. Schottky diode characteristics of conventional Ni silicide show the
Page 98
Chapter 8. Conclusions
94
reverse leakage current and the variation of Bn and n-factor due to excess
silicidation at the electrode periphery. On the other hand, those of stacked silicide are
achieved ideal diode characteristics and robust Bn and n-factor because of formation
of an atomically flat interface including the electrode periphery.
(iv) Schottky barrier height modulation (chapter 6)
The effect of impurity incorporation on Bn is investigated. At first, even
with impurity incorporation, the interface reaction with stacked silicidation process
is also maintained. Second, impurity position can be controlled by stacked
silicidation process because significant amount of the impurities remained at the
silicide/Si interface. Further, Bn modulation is achieved by impurity incorporation at
interface with stacked silicidation process. Moreover, impurity incorporation
position and amount dependent Bn modulation is examined. As a result, the main
fact of Bn modulation is that impurity exists at the interface. Additionally, it is found
that Bn modulation is controlled by controlling the amount of impurity which exists
at interface.
(v) Demonstration of Schottky barrier S/D FET with barrier height modulation
(chapter 7)
SB-FETs using stacked silicidation process with B or P incorporation at S/D
were fabricated below 500 oC except for the gate oxidation. The effect of Bn
modulation on device characteristics is confirmed. It is considered that ambipolar
characteristics are suppressed and on-current is improved because Bn is modulated
to small value.
Page 99
Chapter 8. Conclusions
95
Publications and Presentations
Publications
(1) Yuta Tamura, Ryo Yoshihara, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori
Kataoka, Akira Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo
Hattori, and Hiroshi Iwai, “Interface controlled silicide Schottky S/D for future 3D
devices”, IEICE Technical Report, 110, 90, pp.87-92 (2012).
(2) Yuta Tamura, Ryo Yoshihara, Kuniyuki Kakushima, Hiroshi Nohira, Osamu
Nakatsuka, Parhat Ahmet, Yoshinori Kataoka, Akira Nishiyama, Nobuyuki Sugii,
Kazuo Tsutsui, Kenji Natori, Takeo Hattori, and Hiroshi Iwai, “Physical and
electrical properties of ultra-thin nickel silicide Schottky diodes on Si (100)”, J.
Phys.: Conf. Ser., 417, 012015 (2013).
(3) Yuta Tamura, Ryo Yoshihara, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori
Kataoka, Akira Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo
Hattori, and Hiroshi Iwai, “A Proposal of Schottky Barrier Height Tuning Method
with Interface Controlled Ni/Si stacked Silicidation Process”, to be published in ECS
Transactions.
Page 100
Chapter 8. Conclusions
96
Invited Talk
(1) Yuta Tamura, Ryo Yoshihara, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori
Kataoka, Akira Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo
Hattori, and Hiroshi Iwai, “Interface controlled silicide Schottky S/D for future 3D
devices”, SDM 2012, The University of Nagoya, Aichi, June (2012).
International Presentations
(1) Yuta Tamura, Ryo Yoshihara, Kuniyuki Kakushima, Parhat Ahmet, Akira
Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo Hattori, and Hiroshi
Iwai, “A novel Ni silicidation technology for Schottky diode formation”, IS-AHND,
Tokyo, October (2011).
(2) Yuta Tamura, Ryo Yoshihara, Kuniyuki Kakushima, Osamu Nakatsuka, Parhat
Ahmet, Hiroshi Nohira, Kazuo Tsutsui, Akira Nishiyama, Nobuyuki Sugii, Kenji
Natori, Takeo Hattori, and Hiroshi Iwai, “Electrical Properties of
Ultrathin-Nickel-Silicide Schottky Diodes on Si (100)”, ICTF-15, Kyoto, November
(2011).
(3) Yuta Tamura, Ryo Yoshihara, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori
Kataoka, Akira Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo
Hattori, and Hiroshi Iwai, “A Proposal of Schottky Barrier Height Tuning Method
with Interface Controlled Ni/Si stacked Silicidation Process”, 222th ECS Meeting,
Hawaii, October (2012).
Page 101
Chapter 8. Conclusions
97
(4) Yuta Tamura, Ryo Yoshihara, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori
Kataoka, Akira Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo
Hattori, and Hiroshi Iwai, “Stacked Ni-Silicidation Process for Schottky Barrier
FET”, WIMNACT 37, Tokyo, February (2013).
Domestic Presentations
(1) Yuta Tamura, Kuniyuki Kakushima, Osamu Nakatsuka, Parhat Ahmet, Kazuo
Tsutsui, Akira Nishiyama, Nobuyuki Sugii, Kenji Natori, Takeo Hattori, Hiroshi Iwai,
“Effect of Annealing Temperature on Sheet Resistance of Ni Silicide Formed by
Multi-layered Ni and Si Films”, 72th JSAP Autumn Meeting, Yamagata University,
September (2011).
(2) Yuta Tamura, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori Kataoka, Akira
Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo Hattori, Hiroshi
Iwai, “Influence of substrate on annealing-temperature dependence of sheet
resistivity of stack NiSi2”, 59th JSAP Spring Meeting, Waseda University, March
(2012).
Page 102
Acknowledgments
98
Acknowledgments
First of all, I would like to express my gratitude to my supervisor Prof. Hiroshi
Iwai for his continuous encouragement and advices for my study. He also gave me
many chances to attend conferences. The experiences are precious for my present
and future life.
I would like to thank Associate Prof. Kuniyuki Kakushima for many kindnesses,
supports and encouragements for my study in Iwai Lab.
I deeply thank to Prof. Takeo Hattori, Prof. Kenji Natori, Prof. Kazuo Tsutsui, Prof.
Nobuyuki Sugii, Prof. Akira Nishiyama, Prof. Yoshinori Kataoka, Prof. Hitoshi
Wakabayahi and Associate Prof. Parhat Ahmet for useful advice and great help
whenever I met difficult problem.
I would like to thank Prof. Hiroshi Nohira of Tokyo City University for XPS
observation and Park Systems Japan Inc. for AFM observation.
Also, I thank research colleagues of Iwai Lab. for their friendship, active many
discussions and many of encouraging words. Especially, Shinichi Kano, Yuya Suzuki,
Yuki Tanaka, Kana Tsuneishi, Michihiro Hosoda and Kazuki Matsumoto are the
members who get in Iwai Lab. in the same year and have good friendships.
I would like to appreciate the support of secretaries, Ms. Nishizawa and Ms.
Matsumoto.
Finally, I would like to thank my parents Yoshihiro and Akiko and my brother
Shinya and Hiroki for their endless support and encouragement.
Yuta Tamura
February, 2013