A LOW POWER CMOS TRANSCEIVER DESIGN FOR MEDICAL IMPANT COMMUNICATION SERVICE Huseyin S Savci, Pin Ying, Zheng Wang and Prof. Numan S. Dogan North Carolina A&T State University An ultra low power CMOS transceiver has been designed for a usage in medical implant communication service devices. The FCC regulated MICS band which is 402- 405 MHz, requires ultra low power transceiver for medical implants. The following section gives a brief description of different sections of transceiver. The schematic and measurement results are included for each sub-block of the transceiver. There are three main section in this transceiver; Receiver, Transmitter and Frequency Synthesizer. 1. RECEIVER The architecture of Ultra Low Power CMOS MICS Homodyne Receiver is shown in Figure 1-1. The direct conversion architecture is selected for its lower power consumption. The communication system was designed to work with FSK modulation scheme. The receiver has LNA, Mixer, Pre-Amplifier, BB Filter, and Limiting Amplifier. The total voltage gain is more than 120 dB. This gain is high enough to allow limiting amplifier clip the amplitude of very low power incoming signals (-115 dBm) at VDD. The receiver has tunable bandwidth between 170 kHz and 250 kHz. The analog circuits at the downconverted path were designed to have lower flicker noise. The receiver uses DC-free modulation scheme which takes care the dc offset problem by ac coupling the signal between blocks. The overall power dissipation is around 4 mW. In order to have low power dissipation and moderate RF performance all of the transistors are biased in moderate inversion region where the device parameters are highly dependent on the process variations. Therefore the process corner analyses are carefully employed to ensure the proper operations of the circuits.
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A LOW POWER CMOS TRANSCEIVER DESIGN FOR MEDICAL
IMPANT COMMUNICATION SERVICE Huseyin S Savci, Pin Ying, Zheng Wang and Prof. Numan S. Dogan
North Carolina A&T State University
An ultra low power CMOS transceiver has been designed for a usage in medical
implant communication service devices. The FCC regulated MICS band which is 402-
405 MHz, requires ultra low power transceiver for medical implants. The following
section gives a brief description of different sections of transceiver. The schematic and
measurement results are included for each sub-block of the transceiver. There are three
main section in this transceiver; Receiver, Transmitter and Frequency Synthesizer.
1. RECEIVER
The architecture of Ultra Low Power CMOS MICS Homodyne Receiver is shown
in Figure 1-1. The direct conversion architecture is selected for its lower power
consumption. The communication system was designed to work with FSK modulation
scheme. The receiver has LNA, Mixer, Pre-Amplifier, BB Filter, and Limiting Amplifier.
The total voltage gain is more than 120 dB. This gain is high enough to allow
limiting amplifier clip the amplitude of very low power incoming signals (-115 dBm) at
VDD. The receiver has tunable bandwidth between 170 kHz and 250 kHz. The analog
circuits at the downconverted path were designed to have lower flicker noise. The
receiver uses DC-free modulation scheme which takes care the dc offset problem by ac
coupling the signal between blocks. The overall power dissipation is around 4 mW. In
order to have low power dissipation and moderate RF performance all of the transistors
are biased in moderate inversion region where the device parameters are highly
dependent on the process variations. Therefore the process corner analyses are carefully
employed to ensure the proper operations of the circuits.
Figure 1-1: Complete Receiver Architecture
Low Noise Amplifier
Figure 1-2 has a circuit topology that is commonly used in the design of CMOS
low noise amplifiers. This circuit has an inductive source degenerated input stage to
provide both input match and current gain at the resonant frequency. The cascode
transistor reduces reverse gain through the amplifier by mitigating the interaction
between the input tank and output tank which results increased stability of the circuit.
Furthermore, it reduces the Miller effect of Cgd of M1 by presenting a low impedance
node at the drain of M1. The output inductor Ld is designed to resonate at w0 with the
node capacitance at the drain node of the cascode transistor. In order to have ultra low
power consumption the transistors designed to on border of moderate inversion region.
The total power dissipation is about 830 µW. It has power gain of ~12dB and noise figure
of 1.3 dB.
Figure 1-2: Differential LNA
After all the measurements are performed the component and trace loss of the
PCB has been measured by removing the chip and soldering the semi-rigid coaxial
connectors. Then the board losses are de-embedded from the measured gain based on the
gain relation formula of cascaded two port networks and de-embedded from the noise
figure based on the friis formula. Figure 1-3 and Figure 1-4 shows the measured results of
LNA after de-embedding process.
Figure 1-3: Measured LNA Small Signal Parameters
Figure 1-4: Measured NF of LNA a) before & b) after; de-embedding the PCB and
Component Losses
Double Balanced Gilbert Mixer
A double balanced differential mixer has been designed to be used as direct
conversion mixer. The mixer has 7 dB conversion gain and consumes only 750 µW.
Figure 1-5 shows the schematic drawing of the mixer.
Figure 1-5: Double Balanced Gilbert Mixer
The mixer measurement is done with Tektronix Active Differential Probe at the
IF port. Figure 1-6 shows the down-converted output of the mixer for an RF signal at the
input with -30dBm power level. The output is capacitively coupled to the probe. Due to
the high pass characterictic of such a coupling, the output reaches its normal value which
is -23 dBm after a while. The figure shows that the conversion gain of the mixer is 7 dB.
Figure 1-6 The IF output spectrum of Mixer for an input RF signal with -30 dBm power
Low Voltage High Phase Margin OTA
A low voltage, low current, two-stage OTA with a phase margin enhanced common-
mode feedback (CMFB) circuit has been designed to be used in the tunable channel select
filter. The schematic of OTA is shown in Figure 1-7. The input stage is designed to
satisfy the desired bandwidth and noise characteristics whereas the output stage is to
drive the resistive and capacitive loads. The input transistor pairs are chosen as wide as
possible to lower the flicker noise. To access body terminal of input nMOS devices,
triple-well transistors were used. The body terminals of these devices are biased with a
voltage of VDD/2. The resulting forward biased body-source lowers the VT and further
increases inversion level. The transistors operates near the weak-moderate inversion level
which increases input transconductance, gm, at lower drain current hence the lower power
dissipation. The miller compensation capacitors and resistors adjust the unity gain
frequency while increasing the phase margin.
Figure 1-7 Schematic of Operational Transconductance Amplifier
The common-mode feedback circuit designed in this work is composed of transistors
M1A-B-C-D, M2A-B and M3A-B. The CMFB circuit senses the DC outputs of OTA, compares
it with reference voltage VREF thru the mirrored current and generates an error voltage to
bias M3 and M4. The change in the bias point of M3 and M4 inversely affects the DC
output voltage of OTA. This closed loop continuously forces the output voltage to be
equal to the reference voltage. The CMFB loop has very high gain. The stability of this
loop is ensured by means of CC3 and RC3 which simply enhance the phase margin. The
common mode feedback circuit is designed to have accurate output balancing and stable
operation.
The simulated performance is summarized in Table 1-1. The gain and phase response of the amplifier are shown in Figure 1-8.
Table 1-1 Simulated performance parameters of OTA
Power Dissipation 86 µW Gain Bandwidth Product 17.25 MHz OpenLoop DC Gain 70 dB Input Noise 15.95 nV/√HzPhase Margin 52 ° CMFB Phase Margin 46 ° Unity Gain Frequency 20 MHz Dominant Pole Frequency 5.4 kHz
Figure 1-8 Gain and phase response of OTA
The individual measurement of OTA has not been performed. The performance of
the OTA can be indirectly estimated from the measurement of the filter.
Tunable Continuous-Time Low Pass Filter
A 5th order continuous time tunable elliptic low pass filter has been design for
channel selection of the receiver. The elliptic filter gives enough attenuation with high
selectivity in the stopband. The leap frog configuration is used as shown in Figure 1-9.
Figure 1-9: 5th Order Elliptic Low Pass Filter
100 101 102 103 104 105 106 107 108-60
-40
-20
0
20
40
60
80
Gai
n (d
B)
Frequency (Hz)100 101 102 103 104 105 106 107 108
-225
-180
-135
-90
-45
0
45
90
Ph
(d)
GainPhase
RL RL
RL RL RLRL
CL CL CLCL
RLRL
RL RL RLRLRLRL
CL
CL
CL CL
RL RL RLRL
RLRL
CL CL
RL RL RLRLRLRL
RL RL
RL RL
CL CL
RL
CL
CL
CL
CL
CL
CL
Vbias Vbias
VbiasVbias
VbiasVbias
VbiasVbias Vbias
RL
Vbias
Vout-
Vout+
Figure 1-10 shows the measured frequency response of the filter. The total power
consumption is around 480 µW. The filter has digitally assisted tuning range of 80 kHz
from 170 kHz to 250 kHz.
Figure 1-10: Measured Normalized Gain of Tunable Continuous-Time LPF
Limiting Amplifier
The final stage in the zero-IF receiver before ADC is limiting amplifier. Limiting
amplifiers are used when a circuit requires amplitude compression. They supply a good
protection for subsequent components by preventing input overdrive and removing the
amplitude modulation from frequency modulated signals. The limiting amplifier is
cascaded of simple differential amplifiers. The number of amplifier can be determined
based on the gain requirement. The amplifiers have high pass filter characteristics at the
input which eliminates the DC offset problem. Single stage of limiting amplifier is shown
in Figure 1-11.
Figure 1-11: Limiting Amplifier
Figure 1-12 shows the output waveform of whole receiver so the limiting
amplifier for a input of sinusoidal RF signal at 404.2MHz with -80 dBm power. The
peaking at falling edge and amplitude imbalance is due to the active calibration error of
differential active probe used to measure baseband signal.
Figure 1-12 Measured output waveform of the receiver for a sine RF signal at the input
20 25 30 35 40 45 50
-0.6
-0.4
-0.2
0
0.2
0.4
Time (µs)
Am
plitu
de (V
)
Figure 1-13 shows the die microphotograph of the MICS transceiver. The
different building-blocks highlighted.
Figure 1-13: Chip photo with sub-block representation
A single testboard has been designed for different measurement schemes. Figure
1-14 shows the photo of the testboard. An FR-4 substrate with 31 mil thickness has been
used. CPW structure is adopted for RF traces for its compact size.
Figure 1-14: Testboard for Receiver Section
2. TRANSMITTER Figure 2-1 shows the transmitter architecture. Compare to the reported MICS
architecture [1][2], this transmitter has both nonlinear transmitter path and linear
transmitter path. The low power operation is based on the nonlinear transmitter. For the
nonlinear transmitter, FSK has been chosen as the fundamental transmit modulation
scheme for it is the simplest nonlinear modulation that allows low current circuit design.
The linear transmitter allows much higher data rate with linear modulation schemes such
as 8 phase shift keying (8PSK). The data rate will be close to the three multiples of
channel spacing 300 KHz. The high speed of linear transmitter can be used when high
speed transmission such as image is needed. Same as nonlinear transmitter, relatively
high efficiency design is needed while ensuring the required linearity and output power.
Figure 2-1 Proposed Transmitter Architecture
Nonlinear Transmitter
The designed class E PA schematic is shown in Figure 2-2 and 2-3. L1 provide
DC feed. L2 and C1 provide serial resonance to the load R. C2 is the capacitor parallel to
the switching transistor. The ideal nonlinear model could be found in [3][4]. M1, M2 and
M3 M4 makes two inverters to buffer the FSK signal from VCO. M5 and M6 is the
switch for the class E power amplifier. At 400 MHz, the inductor values are too big to be
on chip so that L1,L2, and C1 have to be on board. The ideal value of inductor L1 and L2
is 4.7uH and 1.3 uH. However, commercially available inductors at such big value are
having very low self resonant frequency. Therefore, both L1 and L2 can only be 150 nH
the maximum. The SPICE model of the 150 nH inductors are shown in Figure 3.1.
Because SAW filter could have its impedance to be the same as the optimum load of for
1V, -2dBm PA, which is 100 ohm, the class E PA tank works as impedance matching as
well. M7 and M8 block is a process and supply sensor. The drain voltage is used as a
negative feedback voltage to bias the body of M6, in order to maintain constant output
level of nonlinear transmitter. M6 is a deep N-well device.
Figure 2-2 Nonlinear Transmitter Schematics Top Level
Figure 2-3 Nonlinear Transmitter Schematics
Linear Transmitter
Figure 2-4 Linear Transmitter Schematics –Top Level
Figure 2-5 Linear Transmitter Schematics -Modulator I Branch
Vee
Figure 2-6 Linear Transmitter Schematics -Push Pull Class-AB PA Figure 2-4, 2-5, and 2-6 are the linear transmitter schematics. Figure 2-4 is the top
level test setup and the no external component. Figure 2-5 is the I branches of modulator.
Figure 2-6 is the buffer, balun and class AB power stage.
Both I and Q branch has a double balanced mixer with differential input and
output. Here the tail inverter mixer is used for its more complete switching than Gilbert
Cell mixer in this low supply voltage case. The double balance is needed here to suppress
the LO to RF leakage. This proposed modulator architecture has potential for even lower
Since we could not tune the center frequency to wanted band, we only could
measure the rest of the PLL blocks separately. The prescaler is a frequency divider with a
factor more than 8000. The performance of this block is good. Figure 3-9 shows the
frequency detected at the output “Fbk,” which indicates a frequency of 100 kHz exactly.
Changing the division ratio when changing the input frequency simultaneously, we got
the same performance. And as predicted, the duty cycle is 50 percent. The part of PFD
and charge pump has not done yet since a two tune function generator is needed to have
two correlated signals.
Figure 3-9 The output frequency at test node of “Fbk.”
ACKNOWLEDGEMENT
The authors would like to thank MOSIS for the helps on Process Design Kit
during the course of this research and the fabrication grant of the chip on Aug 20, 2007 at
IBM 7RF fabrication run. We’d also like to acknowledge the Cadence Design Systems
for supplying the Cadence Software under Cadence University Program.
REFERENCES
[1] A. Tekin, M.R.Yuce, W.Liu, “A Low Power MICS Band Transceiver Architecture for Implantable Devices,” Conference Proceedings, IEEE WAMI 2005, Clearwater, FL. [2] A. Tekin, M.R.Yuce, J. Shabani, W.Liu, “A Low Power FSK modulator/demodulator for an MICS Band Transceiver ,” Radio and Wireless Symposium, 17-19 Jan 2006 IEEE, pp159-162. [3] “Class E- A New Class of High-Efficiency Tuned Single-End Switching Power Amplifiers” Nathan O Sokal and Alan D.Sokal, IEEE Journal of Solid state Circuits, Vol. SC-10, No.3, June, 1975 [4] Steve Cripps, RF Power Amplifiers for Wireless Communications, Artech House 1999, pp158-175. [5] RF Micro Devices, Application Notes, AN0001, 1997