3/18/20041 A Direct Conversion CMOS Transceiver for IEEE802.11a WLANs Pengfei Zhang RF Micro Devices, San Jose, California.

3/18/2004 1

A Direct Conversion CMOS Transceiver for IEEE802.11a

WLANs

Pengfei Zhang RF Micro Devices, San Jose, California

3/18/2004 2

Outline

• Introduction

• Transceiver Architecture

• Frequency Planning

• Circuit Design

• Measured Results

• Conclusion

3/18/2004 3

Wireless Connectivity

WLAN

Bluetooth™

Cellular

GPS

3/18/2004 4

WLAN - Mobility vs. Bit Rate

Mb/s1 10 1000.1

Ou

tdo

or

Stationary

Walk

Vehicle

Ind

oo

r

Stationary/Desktop

WalkMo

bili

ty WLAN

(IEEE 802.11a/b/g)

Bit Rate

LAN

W-CDMA/ EDGE

BluetoothZigbee (IEEE 802.15)

3/18/2004 5

WLAN - Cost vs. Bit Rate

Mb/s1 10 1000,1

Use

r C

ost /

bit

HIPERLAN/2

Bit Rate

LAN

Low

Medium

High

Very Low

$

WLAN(IEEE

802.11a/b/g) LAN

W-CDMA/ EDGE

W-CDMA/EDGE

BluetoothZigbee (IEEE 802.15)

3/18/2004 6

Two-Chip WLAN System

Ref. J. Bohac, Flexible chipset arms 802.11a/b/g WLANs, Microwaves and RF, May 2003

3/18/2004 7

Design GoalsPerformance Condition 11a Requirement

Frequency Range In-door 4.90*-5.35 GHz (*incl. Jpn

bands) 54 Mb/s -65 dBm

Minimum Receive Sensitivity 6 Mb/s -82 dBm

Maximum Transmit Constellation Error

54 Mb/s 16 dBm

-25 dB

• Design Goals: To exceed standard performance requirement, achieve low power consumption and low cost

3/18/2004 8

Direct Conversion vs. Low-IF Conversion (I)

Direct Conversion

Low-IF Conversion

Flicker Noise X DC Offset X Even Order Distortion

X X

LO Pulling X X LO Leakage X X

3/18/2004 9

Direct Conversion vs. Low-IF Conversion (II)

• Image Response– Direct conversion: No Image– Low-IF conversion:

• Analog image rejection – I/Q matching, Circuit complexity• DSP image rejection – large ADC dynamic range required

• ADC Sampling Rate f flow-IF conversion= 2*fdirect conversion

• Baseband Filters– Direct conversion: BW ~ 10 MHz– Low-IF conversion: BW ~ 20 MHz More Power!

3/18/2004 10

Transceiver Architecture

LNA

5.25GHz

90o

0o

LO-0o

LO-90o

RF IN

RF OUT

AGC

LPF

LPF

AGC

To ADC

To ADC

Receiver

LPF

LPF

LO-0o

LO-90o

FromDAC

FromDAC

PAD

Transmitter

Synthesizer

3/18/2004 11

Example of Frequency Planning (Ref.[2])

• Avoid pulling, reduce LO-RF interaction• However, unwanted sideband at /3:

– RX: image in highly populated band (1.8GHz) – TX: degrades efficiency; FCC requirement

Unwanted SidebandMixerDividerVCO

2

cos(2t/3) cos(t/3)

sin(t/3)

cos(t)+cos(t/3)

sin(t)+sin(t/3)

3/18/2004 12

Proposed Frequency Planning

• Quadrature VCO: cross coupled LC resonators• SSB Mixer: suppress unwanted sideband

LO DriverSSB MixerDividerBufferVCO

2

3.5

GH

z

1.75GHz 5.25GHz

cos(2t/3)

sin(2t/3)

cos(t/3)

sin(t/3)

cos(t)

sin(t)

3/18/2004 13

IM2 of Multi-carrier

Ref. K. Cai, P. Zhang, Microwave Journal, Feb. 2004

3/18/2004 14

ADS Simulation of IM2 Impairment

Ref. K. Cai, P. Zhang, Microwave Journal, Feb. 2004

3/18/2004 15

Receiver Architecture

• 7th order Chebyshev “leapfrog” LPF• Improved IP2: AC coupled RF, fully diff baseband• DC offset compensation: 7b DAC; Look-up-table

NotchFilter

AGC

LPF

LPF

AGC

To ADC

To ADC

Notch Filter

DAC

DACLNA V/I Converter

LO-0o

LO-90o

RF IN

From baseband

LUT I

Q

3/18/2004 16

Mixer Design

• Conventional single balanced mixer: tradeoff between 1/f noise and linearity

• Two-stage mixer: Independent biasing

• I2: linearity, I1: 1/f noise

I1

M1

M2 M3

R1 R2

Out+ Out-

LO+ LO-

RFC1

L1

I1

M1M2 M3

R1 R2

Out+ Out-

LO+ LO-

C1

I2RF

C2C2

3/18/2004 17

0 10 20 30 40 50 60-60

-50

-40

-30

-20

-10

0

Gai

n (

dB

)Digital Control Word

Digital Gain Control: R-2R LadderR/6 R/6 R/6 R/6R/6 R/6

Sj1 Sj3 Sj4 Sj5Sj2Sj0 S(j-1)0I1

VOUTR 2R 2R 2R

R R RS00Sn0 Sj0 S10

Mixer Current I1

VDD

When Sjk=1, Gjk=-6*j+20LOG(1+k/6) (dB)

• Mixer resistive load: 10-section R-2R ladder

• Monotonic, linear, fast settling and Constant Rout

3/18/2004 18

Notch Filter: Active-LC Trap

10M 100M-16

-12

-8

-4

0

Mag

nit

ud

e (d

B)

Frequency (Hz)

• Partial channel selection filter to relax linearity requirement of baseband stages• Synthesized L takes minimal silicon area• Large low frequency impedance of C1 minimize flicker noise contribution from M5

R1

I1

C2

C1

M5

VDD

VoutMixer

3/18/2004 19

AGC

60 48 36 24 12 0

-60

-40

-20

0

20

40

60

80

Output SNR

output noise power

output signal power

No

ise

Fig

ure

(d

B)

Po

wer

(d

Bm

)

Receiver Gain (dB)

For an input signal ramping in power, the RX gain is adjusted to maintain a constant output signal power level. Although the RX noise figure increases in low gain settings, the output SNR remains higher than 34 dB in the entire dynamic range.

3/18/2004 20

RX LPF Frequency Response

3/18/2004 21

Transmitter Architecture

• LPF: 4th order Butterworth• Off-chip PA used for system power saving

OffsetControl

LPF

OffsetControl

LPF

LO-0o

LO-90o

FromDAC

PA Driver

FromDAC Power Amp

I

Q

3/18/2004 22

TX LPF Frequency Response

3/18/2004 23

Transmitter RF Front-end

• LO leakage: Mixer DC offset tuning• D/S converter: No need of off-chip balun• Programmable Pout: Binary weighted PA driver

offsettuning

Vbbi

Vbbq

LOq

LOi

L1 L2

VddRFout

R0

M0C0

M4

M3

R1

M1C1

R2

M2C2

D0

D1

D2

C3

D/S Converter

3/18/2004 24

Frequency Synthesizer• Automatic

VCO band selection

• Accumulation mode NMOS varactors

• Off-chip 40 MHz XTAL and loop filter (~200 KHz)

PFD N

decision

timer

M3.5GHz

XT

AL

VH

VL Band Selection

3/18/2004 25

VCO Frequency Bands

3/18/2004 26

Die Photo

0.18 m 1P-6M CMOS with MIM-C

3/18/2004 27

Receiver Gain & Noise Figure

0 2M 4M 6M 8M 10M4

6

8

10

12

14

16RBW=50KHz

-3dB @ 8.7MHz

Baseband Output Frequency (Hz)

No

ise

Fig

ure

(d

B)

40

44

48

52

56

60

64G

ain (d

B)

3/18/2004 28

Receiver Sensitivity

-90 -80 -70

0.0

0.2

0.4

0.6

PER:10%

36 Mb/s 50 frm

54 Mb/s100 frm6 Mb/s

30 frm

Pac

ket

Err

or

Rat

e

Input Power (dBm)

3/18/2004 29

TX Transmit Spectrum

3/18/2004 30

TX Transmit Spectrum

3/18/2004 31

PAPR in OFDM System

• 52 Subcarriers:17dB (=10*log52) PAPR

0 50 100 150 200 250 3000

10

20

30

40

50

60

70

3/18/2004 32

Peak Power Probability

• Large peaks do not occur very often (Gaussian distribution)

4 5 6 7 8 9 10 11 12 13 140

2000

4000

6000

8000

10000

12000

PAPR(dB)

3/18/2004 33

TX Transmit Spectrum

5.28G 5.32G 5.36G-60

-50

-40

-30

-20

-10

0TransmitSpectrum

Mask

RBW=100KHzVBW=30KHz

Output Frequency (Hz)

Tra

nsm

it P

ow

er (

dB

m)

3/18/2004 34

Transmit Constellation

• Output power: 16.2dBm

• 64QAM, 54Mb/s

• Average EVM: 3.41%, -29.3dB

3/18/2004 35

LO Spectrum

1.72 1.74 1.76-80

-60

-40

-20

0

Divided-by-2Output

-66dBc13.3MHz

RBW: 10KHzVBW: 500Hz

Po

wer

(dB

m)

Frequency (GHz)

5.238 5.240

TXOutput

3/18/2004 36

LO Phase Noise

1M 10M 100M-160

-140

-120

-100

-80 Divided-by-2Output 1.75GHzOpen Loop

Ph

ase N

ois

e (

dB

c/H

z)

Offset Frequency (Hz)

10k 100k 1M 10M-130

-120

-110

-100

-90

-80

Phase error=1.5 degree

TX Output5.24GHzClose Loop

3/18/2004 37

RX Switch On Settling Time

-2µ -1µ 0 1µ 2µ0.0

0.4

0.8

1.2

1.6

1.6s

Signal

Clock

Time (second)

Clo

ck V

olt

age

(v)

-0.3

0.0

0.3S

ign

al Vo

ltage (v)

3/18/2004 38

TX Switch On Settling Time

-2µ -1µ 0 1µ 2µ0.0

0.4

0.8

1.2

1.6

Time (second)

Clo

ck V

olt

age

(v)

-0.15

0.00

0.15

1.6s

SignalClock

Sig

nal V

oltag

e (v)

3/18/2004 39

Performance Summary

Condition IEEE802.11a Requirement

This Work

6 Mb/s -82 dBm -91 dBm Sensitivity 54 Mb/s -65 dBm -74 dBm RX

Power Consumption

VDD=1.8v NA 171 mW

EVM 16 dBm Pout

-25 dB -29.3 dB*

LO Rejection 15 dBc 38 dBc TX Power Consumption

VDD=1.8v NA 135 mW

Chip Area 13 mm2

*External PA used

3/18/2004 40

Conclusion

• CMOS Direct-Conversion Transceiver with integrated VCO and frequency synthesizer fully compliant with IEEE 802.11a standard

• Exceeding standard performance requirement with low power consumption and small die area