A HIGH-SPEED, HIGH-RESOLUTION SIGMA-DELTA MODULATOR ANALOG-TO-DIGITAL CONVERTER by LIEYIFANG, B.S.,M.S. A DISSERTATION IN ELECTRICAL ENGINEERING Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of DOCTOR OF PHILOSOPHY Approved Chair]^erí/on of the Committee Accepted -4AM—^ 1 1 . m-»^ Dean of the Graduate School May, 2004
161
Embed
A HIGH-SPEED, HIGH-RESOLUTION SIGMA-DELTA MODULATOR ANALOG ...
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
A HIGH-SPEED, HIGH-RESOLUTION SIGMA-DELTA
MODULATOR ANALOG-TO-DIGITAL CONVERTER
by
LIEYIFANG, B.S.,M.S.
A DISSERTATION
IN
ELECTRICAL ENGINEERING
Submitted to the Graduate Faculty
of Texas Tech University in Partial Fulfillment of the Requirements for
the Degree of
DOCTOR OF PHILOSOPHY
Approved
Chair]^erí/on of the Committee
Accepted
-4AM—^ 1 1 . m-»^
Dean of the Graduate School
May, 2004
ACKNOWLEDGMENTS
First, I would like to express my gratefulness to Professor Kwong S. Chao, for his
continuous support, guidance, patience and friendship during the course of this work.
Without his encouragement, the success of this work would never have been possible. I
also would like to sincerely thank Professor Thomas Krile, Professor Sunanda Mitra, and
Professor Thomas F. Trost for their willingness to be my committee members, and their
time spent on advising of this work.
This work is supported in part by Texas Instruments Inc, Dallas. For this, I am
thankful to Mr. David Devincal, Dr. Eric Sonen, Dr. Frank Tasy, Mr. Hugh Mair, and Dr.
Hydar Bilhan. Technical discussions with Dr. Feng Chen and Dr. Ramesh
Chandrasekaran, on many respects such as design, layout, fabrication, and testing have
been extremely beneficial. Assistance from other staff members in Texas Instruments,
Inc. is also appreciated.
I owe special thanks to my peers, Martin Kinyua, Zhongqiang Zheng, Yeshoda
Devi Yedevelly, and Chun Hsien Su for many discussions and help.
I appreciate the support from the Department of Electrical and Computer
Engineering.
Thanks also go to my parents, brothers, and sister for their unfailing love.
Finally, but not least, I would like to dedicate this thesis to my wife, Lanyun Gao,
my daughter, Rebecca, and my son, David, for their unprecedented love and support
throughout my graduate studies. Without them, my study here would not be possible.
CONTENTS
ACKNOWLEDGMENTS i
ABSTRACT vi
LISTOFTABLES vii
LIST OF FIGURES viii
CHAPTER
1. INTRODUCTION 1
2. ANALOG-TO-DIGITAL CONVERTER 4
2.1. Overview 4
2.2. Typical specifications of analog-to-digital converters 6
2.3. Types of analog-to-digital converters 7
2.4. Limitations of conventional converters 9
3. BASICS OF OVERSAMPLING SIGMA-DELTA MODULATOR 11
3.1. Overview 11
3.2. Concepts used in the sigma-delta modulator 12
3.3. Simple sigma-delta modulator 16
3.4. High-order sigma-delta modulator 20
3.5. Advantages 25
3.6. Limitations and questions 25
4. MULTI-BIT SIGMA-DELTA MODULATOR BASED ADC 27
4.1. Overview 27
11
4.2. Multi-bit sigma-delta modulator without multi-bit DAC 30
4.3. Other multi-bit sigma-delta modulator systems 34
Sigma-delta modulators provide the means for achieving high-resolution analog-
to-digital conversion. The main hmitation faced in the high-resolution Sigma-Delta
approach is conversion speed. A multi-stage multi-bit sigma-delta modulator with
interstage gain scaling is proposed in this study, and it is designed and implemented in a
0.6 |am CMOS process. This topology employs a second-order single-bit modulator in the
main stage foUowed by an 8-bit quantizer in pipeline structure. The second stage of the
modulator consists of a first-order single-bit modulator followed by a 5-bit quantizer. A
gain stage is inserted between the two stages to scale the signal level to within the
reference level.
System and circuit level simulations have demonstrated that the proposed
modulator is capable of achieving high speed and high resolution in analog-to-digital
conversion. The detailed design considerations in circuit implementation of the proposed
modulator are also analyzed and discussed. The prototype is fabricated in a 0.6 im
CMOS process with 3.3V power supply. Experimental measurement of the prototype is
performed. Several factors limiting the performance are discussed.
VI
LIST OF TABLES
3.1. Reduction of the quantization noise power 16
3.2. The value at different nodes of the modulator in the first 10 steps 18
5.1. The high speed sigma-delta modulator converters 52
5.2. The relationships among analog coefficients and digital coefficients 57
5.3. The circuit specifications 62
6.1. Transistors size of the op-amp core 75
6.2. Summary of the op-amp 80
7.1. Summary of testing results 111
vii
LIST OF FIGURES
2.1. A typical analog-to-digital converter 4
2.2. An example of a uniform multilevel quantization characteristic that is represented by linear gain G and errorE 5
3.1. Diagram of sigma-delta modulator based analog-to-digital converter 13
3.2. Diagram of power spectral density of quantization noise of Nyquist converters, oversampling converters, and oversampling plus noise shaping converters 14
3.3. Noise shaping function (NSF) 16
3.4. A simple first order sigma-delta modulator 17
3.5. Integrator output u(kT) and the averaged output value of q(kT) as a
function of time 19
3.6. Pulse density modulation output to sinusoidal input in time domain 20
3.7. Dynamic range as a function of oversampling ratio r and order L of the single-bit modulator 21
3.11. Trade off between the resolution and speed for various converters 26 4.1. A simple first-order sigma-delta modulator employing an intemal multi-bit
quantizer and a multi-bit DAC 28
4.2. The topology (a) and its equivalent scheme (b) of a multi-bit sigma-delta modulator proposed by LesUe and Singh in 1990 31
4.3. The system topology proposed by Kinyua and Chao (1997) andBrooks,Robertson, andKelIy(1997) 32
Vll l
4.4. The system employing interstage scaling concept proposed by Chandrasekaran and Chao (1997) 33
4.5. The proposed system. I](z) and ^(z) are integrators. Hi(z) and H2(z) aredigital filters 35
4.6. Baseband power spectral density of the output of the proposed structure (top figure), the regular MASH topology with ideal multi-bit DAC (middle figure) and with nonideal multi-bit DAC (bottom figure) in the feedback loop of the second stage 38
4.7. SNR for the proposed structure (upper curve) and that of the regular MASH topology with nonideal multi-bit DAC (lower curve) as a function of input signal level 38
4.8. The multi-bit sigma-delta modulator employing interstage feedback 39
4.9. Comparison of various modulators in terms of quantization noise level reduction 41
4.10. Baseband power spectral density for the proposed system (lower curve) and that of the system (upper curve) in [23] and [24], the spikes in the graph is that of the input signal 43
4.11. SNR for the proposed system (upper curve) and that of the system (lower curve)
in [23] and [24] as afunction of input signal level 43
4.12. A multi-bit system with gain and pole errors being spectrally shaped 45
4.13. The extension of the system in Figure 4.12 to high order noise shaping 47
4.14. The power spectral density (PSD) of the output of both systems with both gain error andpole error are assumedto be 0.01 48
4.15. The effect of gain and pole errors on signal-to-noise ratio for the proposed system and the system in [20] 49
5.1. The performance of published sigma-delta modulator analog-to-digital converters in terms of resolution and signal bandwidth 52
5.2. Block diagram of the system 54
IX
5.3. The topology of third-ordermulti-bit sigma-delta modulator 56
5.4. The integrator output probabiHty density for a -6dB input signal 60
5.5. Power spectral density (PSD) of the sigma-delta modulator shown
inFigure 5.3. PSD in the baseband is shown at the bottom 61
6.1. The schematic of a typical two-stage amplifier core 67
6.2. The high frequency differential half-equivalent circuit for two-stage
amphfier shown in Figure 6.1 68
6.3. The continuous time common-mode feedback network 76
6.4. The switched-capacitor common-mode feedback network 77
6.5. Bias circuit employing extemal current reference 78
6.6. AC sweep of Spice simulation 80
6.7. The block of paired transistors 81
6.8. The layout of the op-amp 82
6.9. The schematic of the comparator 84
6.10. Layout of the comparator 85
6.11. Diagram of the sampling capacitor and switches and the equivalent circuit 86
6.12. The diagram of the sampling switch and capacitor (a), the MOSFET implementation (b) 89
6.13. Thediagram showing the clock feedthrough and charge injections 89
6.14. The power spectral density of the input signal and the harmonic distortions 91
6.15. The schematic of second-order sigma-delta modulator 95
6.16. The schematic of one stageof the pipehned ADC 98
6.17. The schematic of the first-order sigma-delta modulator 100
6.18. Theschematicofaflash ADC 101
6.19. The schematic of the clock generator 103
6.20. The uniform density function of the clock jitter 103
7.1. Die photograph of the prototype 107
7.2. Testing setup 108
7.3. Power spectral density of input signal level at-3dB 110
7.4. Power spectral density of first stage output when inputs are
shorted to PCB board 112
A. 1. Half circuit of the switched-capacitor integrator 120
B.l. Diagram of generic B-bit-per stage pipeline ADC 127
B.2. Diagram of 1.5-bit-per stage switched-capacitor A/D converter 131
B.3. Residue plot of 1.5-bit-per stage algorithmic ADC for ideal case 133
C. 1. Equivalent configuration of amplification phase or integrating phase 134
C.2. The equivalent circuit of a two-stage op-amp 142
D.l. The configuration of the gain stage during the amplification phase or that of integrator during the integrating phase 146
XI
CHAPTER I
INTRODUCTION
Data converters which include analog-to-digital converters (ADCs) and digital-to-
analog converters (DACs) are the devices that provide the link between the analog world
of the transducer or actuator and the digital world of signal processing, computing, digital
data collection or digital data processing [1]. They convert the analog signals to digital
counterparts which are processed in the digital domain or convert the digital code to
analog signals. High performance data converters are always in demand in view of the
rapid development of computing and digital signal processing. For example, the
consumer products such as compact disc players, camera recorders (CAMCORD),
telephones, modems, high-definition television (HDTV), asymmetrical digital subscriber
line (ADSL), etc, require a high resolution and/or high speed data converter to interface
to the analog world [2, 3, 4, 5].
The performance of digital signal processing and communication systems is
generally limited by the performance of the data converters. Achieving high resolution in
conventional data converters other than the sigma-delta modulator based approaches
requires high precision analog components that are very difficulty and costly in a Very
Large Scale Integrated (VLSI) process. The problem becomes more and more severe as
feature sizes of VLSI processes continue to shrink. On the contrary, the high precision
component matching and trimming are not needed in sigma-delta modulator based data
conversion technology. It is a cost effective altemative for high resolution (greater than
16 bits) converters which can be ultimately integrated on digital signal processor
integrated circuits (ICs).
Sigma-delta modulator based data converters use a coarse quantizer, for example
single bit, to achieve high resolution by employing two basic principles: oversampHng
and spectral shaping. The in-band quantization noise is reduced by the spectral shaping
function; the out-of-band noise is removed by the digital decimation filter. The overall
quantization noise is dramatically reduced. The resolution can be increased to as many as
20 or more bits by simply increasing the oversampling ratio and the order of the shaping
function [2, 3,4]. There is good linearity and accuracy. Since the signal bandwidth to be
converted is limited by the nature of the oversampling, it has seen applications mostly in
digital audio (low-frequency range). However, there is ever increasing need to apply
high-speed data converters with high resolution in the area of modem communication
systems such as ISDN, ADSL. This leads to the trend of extending the application of
sigma-delta modulator based data converters to higher signal frequencies. The problem
of how to achieve wide signal bandwidth, hence high speed, while retaining the high
resolution becomes a very important and interesting issue in the design of sigma-delta
modulator converters.
In this thesis, several system topologies that lead to high resolution and high
speed sigma-delta modulators are proposed and studied. One of these topologies based
on interstage scaling has been implemented and fabricated in a 0.6um, double-poly and
triple-metal 3.3voIts CMOS process.
In the context of this thesis, an overview of the conventional analog-to-digital
converters is described in Chapter 2. Different types of converters and their hmitations
are also briefly discussed. In Chapter 3, the basics of the sigma-delta modulator are
reviewed and several architectures are discussed along with their advantages and
limitations. In Chapter 4, the multi-bit sigma-delta modulator is reviewed and the existing
topologies are introduced. Some useful topologies leading to high-speed and high-
resolution modulators are proposed and reviewed. In Chapter 5, the high-speed, high-
resolution, sigma-delta modulator architecture and behavioral simulation are given. The
detailed VLSI implementation in 0.6um CMOS process is presented in Chapter 6.
An experimental prototype sigma-delta modulator has been fabricated, and its
results are presented in Chapter 7 along with discussions on key performance issues.
Finally, the conclusions are given in Chapter 8.
CHAPTER 2
ANALOG-TO-DIGITAL CONVERTER
2.1 Overview
As mentioned in Chapter 1, the analog-to-digital converter is the type of device
that converts the signals in the analog domain to its digital counterpart that can be
processed by a computer or digital signal processor in the digital domain.
An analog-to-digital converter performs two basic operations: sampling in time
and quantizing in amphtude [1, 2]. A typical analog-to-digital converter is shown in
Figure 2.1.
Analog Input
"^ ^
Anti-alias Filter
Ar
' ^ i
-^
lalog c
Sampler
ircuitry
X
->
! E
\/
Quantizer Y
^ Encoder
^
Digital Output
Figure 2.1. A typical analog-to-digital converter
The low-pass filter is an anti-alias filter that removes the components outside the
signal bandwidth to be converted. It eliminates aliasing when the Nyquist sampler is
applied. The analog signal is sampled in time and quantized in amplitude. The
quantization levels are encoded, resulting in digital code outputs. The digital code can
enter a computers or digital signal processors for signal conditioning. The sampling in
time results in discrete signals, and the quantization in amphtude causes errors to the
signal quantized. Figure 2.2 shows a uniform quantization that rounds off a continuous
signal X to integers in the range of ±5. In this example, the level space A is 2.
- > X
Y=GX+E
Figure 2.2. An example of a uniform multilevel quantization characteristic that is represented by linear gain G and error E.
The relationship between the quantized output Y and analog input X can be
described by the following equation:
Y = G^X-\-E, (2.1)
where E is quantization error and G, the overall gain of the converter, is arbitrary. It is
seen that the output signal of the quantizer is not exactly equal to the input signal. It is
contaminated by the error term E.
2.2 Typical specifications of analog-to-digital converters
Many types of specifications for analog-to-digital converters are quoted by
hardware manufacturers. Here only four are used: resolution, linearity, dynamic range,
and throughput; and they are explained in this section.
a. Resolution: The resolution of an analog-to-digital converter is the number of steps
the input range is divided into. The resolution is usually expressed in bits {n) and the
number of steps is expressed as 2 to the power n. With 12-bit resolution, for instance,
the range is divided into 2^ , or 4096, steps. In this case a -1 to 1 V range will be
resolved to 0.5mV, and a -lOOmV to lOOmV range will be resolved to O.OSmV.
Although the resolution can be increased if the input range is narrowed, there is no
point in trying to resolve signals below the noise level of the system; all one can get is
unstable readings.
b. Linearity: Ideally, an analog-to-digital converter with n-bit resolution will convert
the input range into 2n-l equal steps (4095 steps in the case of a 12-bit converter). In
practice, the steps are not exactly equal due to the nonlinearity of the circuits. This
leads to the nonlinearity in a plot of the analog-to-digital output against the input
amplitude.
c. Dynamic range: Dynamic range is the ratio of maximum allowable input level and
the minimum input level that can be converted in a monotonic and linear manner. It is
limited by the non-linearity of the conversion circuit. Ideally, the signal-to-noise plus
distortion ratio (SNDR) of the converter will be a straight line with different input
levels. However, there are many factors that limit the allowable input level in
practice.
d. Throughput: The throughput is the maximum rate at which the analog-to-digital
converter can output data values. In general, it will be the inverse of the samphng
periods of the analog-to-digital converter. Thus a converter that takes 0.1|Lis to acquire
and convert will be able to generate lOM samples per second. The throughput is
lOM/sec. in this case. Throughput can be increased by the use of pipeline stmctures,
such that a second conversion can start while the first is still in progress. Throughput
may be slowed down, however, by some factors that prevent data transfer at the full
rate.
2.3 Tvpes of analog-to-digital converters
Numerous types of analog-to-digital converters have been designed and
manufactured in VLSI processes. Those types typically used, such as flash converter,
pipelined converter, successive approximation converter, folding converter, and sigma-
delta modulator converters, are described briefly in this section.
a. Flash Converter. A flash converter is the fastest type of converter. It works by
comparing the input signal to a reference voltage, but a flash converter has as many
comparators as there are steps in the comparison. For an n-bit converter, the number
of comparators used will be ^''-l, which makes the high resolution (n>10) impractical.
With n=10, for instance, 1023 comparators are required and operated in parallel. This
makes the input capacitance too large, thus slowing down the operation speed.
Moreover, the reference step is Vref/1023, which is diffícult to achieve in the
modem VLSI process. In addition, a considerable amount of digital logic is required
to encode the comparator's outputs. The resolution of a flash converter is usually 8
bits or less.
b. Pipeline Converîer. A pipeline converter uses the concept of pipelining often used in
digital circuits. It can achieve higher speed where several operations are performed
serially. Generally, a pipehne converter consists of many conversion stages. Each
stage is a coarse quantizer that carries out an operation on a sample and passes the
residue to the following conversion stage. Once the result is passed on, each stage is
free to process the next sample coming down the pipe. Thus, at any given time, all the
stages are processing different samples concurrently. The throughput depends only on
the speed of each stage and the acquisition time of the next stage. A simple pipeline
converter is a one-bit-per-stage stmcture in which each stage resolves only one bit.
With n-bit resolution, n conversion stages are required, and n-1 operational amplifiers
are required to sample and hold the residuals of previous stages. The pipeline
converter with multi-bit quantizer in each stage is also designed such that a small
number of operational amplifiers is required; thus the power consumption is reduced.
In practice, pipehne converters can achieve up to 14 bits.
c. Successive approximation converter. A successive approximation converter (SAR)
works by first comparing the input signal with a voltage which is half of the input
range. If the input is larger than this level, it compares it with three quarters of the
range, and so on. If the input is below this level, it compares with a quarter of the full
input range, and so on. With n-bit resolution, n such steps are required; for instance,
twelve such steps gives 12-bit resolution. As these comparisons are taking place, the
signal is frozen in a sample and hold circuit. Practically, up to 14 bits of resolution is
possible. Usually sophisticated digital logic is needed.
d. Folding converter. A folding converter evolved from flash and two-step topologies
[6]. Flash converters are operated in one step without the need for post-processing,
but they suffer from the large input capacitance, large power dissipation, severe
offset, and severe timing problems as speed and resolution increase. Two-step
architecture, on the other hand, has much less hardware but requires a front-end
sample-and-hold circuit as well as analog post-processing. Folding architectures
perform analog preprocessing to reduce the hardware while maintaining the one-step
nature of flash architecture. The basic principle in folding is to generate a residue
voltage through analog preprocessing and subsequently quantize the residue to obtain
the least significant bits. The most significant bits can be resolved using a coarse flash
stage that operates in parallel with the folding circuit and hence samples the signal at
approximately the same time that the residue is sampled. It differs from the two-step
flash converter in that the residue is generated using simple wideband stages instead
of using a multi-bit DAC and an analog subtractor.
e. Sigma-delta modulator converter: A sigma-delta modulator converter is a new type of
converter. It emerged in the mid-1980s. It achieves extremely high resolution with
lower precision analog components. For example, it achieves more than 16-bit
resolution by employing only a one-bit quantizer. In general, very complex digital
circuitry is required for the decimation filter. Usually, no sample/hold and anti-alias
filter is necessary at its input. Up to 20-bit resolution can be achieved.
2.4 Limitations of conventional converters
Achieving high resolution requires high precision analog components in the
conventional converters. Consider a flash converter, for instance, with 12-bit resolution:
4095 comparators are required. The reference step is V^^j- /4095. If V^^j- = IV is assumed,
the reference step is only 0.24mV. Such fine steps are well below the offsets of the
comparators and the mismatch of the components used to obtain the reference voltages.
The offsets of the operational amplifier and comparators used in a pipeline converter also
make it difficult for the converter to achieve high resolution (>12-bit) in practice. In
addition, with VLSI offering high speed and high density, the accuracy of the analog
component is reduced. The signal range, thus the dynamic range, is also reduced due to
the scale down of the power supply. Moreover, the environment of the circuits becomes
noisy when more and more circuits are integrated into a single chip. The noisy
environments make the matching even worse. Therefore, it is impractical to achieve high
resolution in conventional converters.
10
CHAPTER 3
BASICS OF OVERSAMPLING SIGMA-DELTA MODULATOR
3.1 Overview
The use of oversampling and single-bit code words can be dated back to 1946
when delta modulation was fírst proposed. Many modifícations and variants of the delta
modulator have been suggested since then [2]. In a delta modulator, a coarse quantizer is
used and its output is integrated and subtracted from the input signal; the signal
difference between the input signal and the output of the integrator is the input of the
quantizer. The overall output of the modulator is the differentiation of the input signal
plus the quantization noise. The signal can be recovered by applying an integrator used at
the receiver; as a result, the quantization noise is shaped.
The techniques to spectrally shape noise, namely noise shaping, had been
proposed by Culter in 1954 [7]. His idea was to take a measure of the quantization error
in one sample and subtract it from the next input sample. Sigma-delta modulation
employing noise shaping was proposed by Inose and Yasuda in 1962 [8]. It is performed
by a delta modulator with the input signal integrated before entering into it. It eliminates
the need of using an integrator for the delta modulator to recover the input signal at the
receiver. However, this technique had not been used in practice until the mid-1980s,
because the use of a sigma-delta modulator required a digital decimation filter
suppressing the high frequency noise which was not realistic to build. In the mid-1980s,
the VLSI technology, especially the CMOS technology, had been advanced to
11
incorporate the digital signal processing circuits into a single chip [2]. Since then, sigma-
delta modulator based data converters have become a research area of interest.
There are two main application fields for oversampling sigma-delta modulator
converters. The first is the baseband converters, where the bandwidth is from dc to/s.
The other one is the bandpass sigma-delta modulators, where the modulator is designed
to perform noise shaping with the zeros of the noise transfer function placed at —/^
instead of dc. The bandwidth it converts is —/^ — / ^ to —/^ + —/^ [9]. In the context
of this thesis, only the former is discussed.
3.2 Concepts used in the sigma-delta modulator
Sigma-delta modulator based analog to digital converters employ two basic
concepts, oversampling and spectral noise shaping. The diagram of a sigma-delta
modulator based analog to digital converter is shown in Figure 3.1. Compared to the
conventional analog-to-digital converter, the quantizer in the diagram of Figure 2.1 is
replaced by the sigma-delta modulator in Figure 3.1, and the encoder there is replaced by
a digital decimation filter.
12
X s ^
Anti-alias Filter
• — f c
-.-* Sampler
Analog circuitry
í>
! E
ÍJ Z-A
Modulator
Y • j >
Decimation Filter ^
Digital Output
Figure 3.1. Diagram of sigma-delta modulator based analog-to-digital converter
The merit of oversampling and spectral shaping can be illustrated by Figure 3.2.
The required output of the converter can be expressed in the z-domain as
Y{z) = Giz) •X(z) + E{z) • NTF{z), (3.1)
where G(z) is the signal transfer function and NTF(z) is the quantization noise transfer
function or noise shaping function. Equation 3.1 is different from Equation 2.1 in that the
second term has an additional factor, NTF(z)- The signal transfer function and the
quantization noise transfer function are different while they are identical in the
conventional quantizer. If the shaping function, NTF(z), is chosen such that the error
term can be reduced dramatically, a high resolution converter can be realized.
In general, assuming that the quantization E is white noise and is uniformly
distributed in [-A/2, +A/2] if the quantizer is not saturated, where A is the space of
quantization level, the power of the quantization noise, PE, is given by [2, 4]
12 (3.2)
When a quantized signal is sampled at frequency / , the corresponding power spectral
density {PSD) can be written as
13
PSD,^ 12/.
(3.3)
where /^ is the sampling frequency. If the principle of oversampling is applied such that
the signal bandwidth converted /g = / .
2^0SR , where OSR is the oversampling ratio, then
the power of the quanzation error in the signal band becomes
E{0) 12 •OSR
(3.4)
Power Spectral Densitv A
/Quantization error of Nyquest converter
Quantization error of oveirsampling -i-noise shapi/ig
NTF(f)
Quantization error of oversampling converter
Figure 3.2. Diagram of power spectral density of quantization noise of Nyquist converters, oversampling converters, and oversampling plus noise shaping converters.
14
It shows that the power of the quantization error is OSR times reduced. The
reduction leads to — Iog2(05/?)bits improvement in conversion resolution. With
0SR=16, the power of quantization error is 16 times reduced; that is equivalent to 12dB
improvement in signal to noise ratio, or 2-bit increase in resolution. In addition to
oversampling, if NTF(z) is chosen to be of first order differentiator, l-z'\ such that
NTF{f) = l~e^^, the quantization error power can be even further reduced in this case.
The power of the quantization error by oversampling plus noise shaping, PE^O+S) '
becomes
p _ o
[^í ^ í ^ \^ n sin OSR
n (3.5) \OSRjj
For 0SR=16, the power of the quatization noise is reduced by 26dB, which means a more
than 4-bit increase in resolution. The higher the order, L, of the shaping functions, the
more high resolution is achieved (Figure 3.3). Table 3.1 shows the reduction of the
quantization noise power with different OSR and the number of order of shaping
functions.
15
0.1 0.2 0.3 0.4 Frequency normalized to fs
0.5
Figure 3.3. Noise shaping function (NSF).
Table. 3.1. Reduction of quantization noise power.
Shaping^ -- ..... ^ ^
Non
Firstorder, l-z'
Second order, (l-z'^)^
4
6dB
8dB
16 dB
8
9dB
17 dB
34 dB
16
12 dB
26 dB
52 dB
32
15 dB
35 dB
70 dB
3.3 Simple sigma-delta modulator
A first-order sigma-delta modulator is shown in Figure 3.4. It consists of a filter
and a single-bit quantizer enclosed in a feedback loop. Together with the filter, I(z), the
feedback loop acts to shape the quantization noise. It attenuates the quantization noise in
16
the low frequency range and emphasizes the high frequency noise. However, since the
signal is sampled at a frequency much higher than Nyquist rate, the high frequency noise
can be removed by a low pass digital fílter without causing any distortion of the signal.
The output of the modulator, Y, is in digital code and the input, X, is analog signal. The
quantizafíon error of the single-bit quantizer is represented by E.
+ _ v ( k î r ) -f-o ^ T O Aq(kT)
Y(kT)
Figure.3.4. A simple first order sigma-delta modulator.
If the loop filter/(z) = — is assumed, the overall output can be obtained by l-z
applying the linear analog-to-digital model analysis that
Y{z) = X{z)z-'+E{z){l-z-'). (3.6)
-1 Equations 3.6 and 3.1 are equivalent provided that G(z)~ z and
NTF{z) -l-z'^• The shaping function in Equation 3.6 is afirst-order differentiator.
The magnitude of the noise transfer function, l-z , is very close to zero in the low
frequency end. The quantization error term becomes negligible; therefore, the output Y is
17
a replica of the input signal X. So, ideally, the quanfízation error is suppressed but the
signal X is unaffected by the modulator. Note that any errors injected into the node after
the integrator will be noise shaped. Thus, unlike the conventional converters, the dc-
offset of of the comparators will not affect the performance of the sigma-delta modulator
converters.
The principles of how the sigma-delta modulator analog-to-digital converter
works can be illustrated by Table 3.2 and Figure 3.5.
Table 3.2. The value at different nodes of the modulator in first 10 steps.
The multi-bit quantization error EM is spectrally shaped by the second order shaping
function, (l-z^)^, as expectedfor a second-order modulator. The quantization errorE] of
the fírst stage and multi-bit DAC error ED of the second stage are completely cancelled.
The proposed system topology has been simulated in SMULINK and MATLAB
for a system that consists of a fírst-order modulator in the fírst stage and a 4-bit fírst-order
36
modulator in the second stage. The system is simulated with an 8kHz sinusoid as input,
an oversampling ratio of 64, and a sampling frequency of 2.62144MHz. For
demonstration purpose, the multi-bit DAC error is assumed to be a wideband noise with
its amplitude bounded by [- A/2, +A/2], where A is the step size of the multi-bit
quantizer. In comparison, the regular MASH topology with both ideal and nonideal DAC
is also simulated with the same settings. The power spectral density (PSD) and signal-to-
noise ratio (SNR) are calculated to evaluate the performance. The simulation results of
the proposed system and that of the regular MASH structure are given in Figures 4.6 and
4.7. For comparison purposes, the simulation result of a regular MASH with ideal multi-
bit DAC is also included in Figure 4.6. It is shown that the noise floor of the proposed
system is similar to that of the regular MASH structure with ideal DAC and is much
lower while the SNR is about 15 dB higher than that of the regular MASH structure with
nonideal DAC. The same order of improvement in dynamic range is also observed. These
results demonstrate that the multi-bit DAC error of the second stage is completely
cancelled in the proposed system.
37
P . S . D ( d B )
c
0
5 0
0 0 " _ , _ — A
0 5 1 1 .5 2 2
--
0 .5 1 .5
1 1 .5 F r e q u e n c y ( H z )
2 . 5 X 10
2 5 x 1 0
2 . 5 X 1 0
Fighure 4.6. Baseband power spectral density of the output of the proposed structure (top figure), the regular MASH topology with ideal multi-bit DAC (middle figure) and with nonideal multi-bit DAC (bottom figure) in the feedback loop of the second stage.
100 Comparison with regular MASH system
-100 -80 -60 -40 -20 Input amplitude (dB)
Figure 4.7. SNR for the proposed structure (upper curve) and that of the regular MASH topology with nonideal multi-bit DAC (lower curve) as a function of input signal level.
38
4.3.2 Multi-bit sigma-delta modulator ADC with interstage feedback
In order to improve the noise shaping function, a topology employing interstage
feedback is introduced [27]. The quantization error due to the multi-bit quantizer is fed
back to the modulator in the main stage to allow spectral shaping beyond that achieved
by the main modulator with the Candy structure. The topology combines the advantage
of high order noise shaping and the pipeline concept to achieve high resolution and high
speed A/D conversion. The proposed architecture is shown in Figure 4.8, where the main
stage is a modulator with a 1-bit quantizer and a multi-bit quantizer realized by a pipeline
system in the second stage. I(z) is integrator and Hi(z) and H^^z) are digital filters. The
blocks inside the dash line are the pipeline quantizer.
X ^ ^ I(z) ^ < V ^ Y
^ Hi(z) ^
*É, ôî Z' Y
HD F(z)
T 7 - I
H2(Z)
Figure 4.8. The multi-bit sigma-delta modulator employing interstage feedback.
The quantization error Ei generated by the single-bit quantizer is canceled by the
digital filters Hi(z) and H2(z), while the multi-bit quantization error Em is fed back to the
39
main modulator and noise shaped. Since the muki-bit quantizer is assumed to be
implemented in a one bit per stage pipeline system, it results in a one bit DAC that is
inherentiy linear in each stage of the pipehne system.
For simplicity, it is assumed that the main stage is of fírst order, I(z)=z^/(l-z^).
The digital outputs Y](z) and Y^^z) of the proposed system are expressed by
where F(z) = 1, H](z) = z'", H^íz) = I z\ and m is the number of unit delays required
for implementing the multi-bit quantizer. The resulting output Y(z) of the overall
modulator becomes
Y(z) = Yj(z)H](z)-Y2(z)H2(z)
= X(z)z-^"^'^ (1 z')(l - z^EUz). (4.11)
The multi-bit error is noise shaped by the function (1 z'^)(l z'^) instead of (1 z'^). If
the main modulator is of second order, then F(z) = (2 z'"), H](z) = z'", H^^z) = (1 - z'^/,
and the overall output can be shown as
y(z)=X(z)z-^'"^'^ (1 z'')\l z"'fEm(z). (4.12)
For a second-order main modulator, the multi-bit quantizer error can be shaped well
beyond the second order by an extra shaping factor (1- z'"^) . The effect of the additional
shaping factor can be seen in Figure 4.9. In the low-frequency end, even more reduction
of the quantization noise level is observed if we compare it with the third-order noise
shaping.
40
-200
M=2
0.05 0.1 0.15 ^(fs/2) (Normalized frequency)
0.2 -200
M=3
0.05 0.1 0.15 f (fe/2) (Normalized frequency)
0.2
Figure 4.9. Comparison of various modulators in terms of quantization noise level reduction.
The higher-order noise shaping is guaranteed by requiring the magnitude of the
extra shaping function to be less than 1 in the baseband. This can be achieved by the
proper selection of the oversampling ratio. It is of interest to fínd the condition under
which
l-z = 1 . (4.13)
The critical frequency/c at which the above condition holds can be obtained as
f - - ^ 6m
(4.14)
where / , is the oversamphng frequency and m is the number of the unit delays as defíned
previously. Thus, the oversampling ratio required to ensure that the magnitude of the
extra shaping function is less than 1 in the baseband is
0SR>3m. (4.15)
41
When compared with the results of the modulator described in [22] and [23], the
proposed topology gives a smaller error providing that the oversampling ratio is greater
than a critical value 3m. The condition is easy to satisfy. For example, only 3 unit delays
are required to implement a 6-bit pipeline quantizer in a 1-bit per stage structure. This
means OSR >9 is required. In the case of 0SR=9, the signal-to-noise ratio can be
improved by 4.5dB and 9dB due to the additional shaping factor (l - z'"") and (l - z"'" f,
respectively. Since the feedback error is the error of a multi-bit quantizer that is
relatively small, the instability problem can be mitigated in the main modulator.
The proposed system topology has been simulated in SEMULINK and MATLAB.
For a system whose main modulator is of second order and has a 5-bit quantizer in the
feed-forward path, the proposed system is simulated with a lOkHz sinusoid as input, an
OSR of 64, and a sampling frequency of 2.62144MHz. In the simulation, a one bit and
one unit time-delay per stage pipeline multi-bit quantizer is assumed. For the purpose of
comparison, the system given in [23] and [24] is also simulated with the same settings.
The power spectral density and signal-to-noise ratio of the proposed system and the one
presented in [23] and [24] are given in Figures 4.10 and 4.11, respectively. It is shown
that the noise floor of the proposed system is much lower while the SNR is about 25dB
higher than that of the system described in [23] and [24]. The same order improvement in
dynamic range is also observed.
42
50
P.S.D .(dB)
-50
-100
-150
Kinyua&Chao,1997 'Brooks,et al. 1997
Proposed system
1 1.5 Frequency (Hz) x10
2.5 4
Figure 4.10. Baseband power spectral density for the proposed system (lower curve) and that of the system (upper curve) in [23] and [24], the spikes in the graph is that of the input signal.
120 •100 -80 -60 ^ lripUanpiitu[fe(dB)
20 0
Figure 4.11. SNR for the proposed system (upper curve) and that of the system (lower curve) in [23] and [24] as a function of input signal level.
43
4.4.3 Multi-bit sigma-delta modulator with high-order noise-shaped integrator leakage
The multi-bit modulator system systems discussed so far are two-stage systems.
Like the MASH structure, the cancellation of the errors in the first stage depends upon
the matching between the analog filter and the digital filters applied. However, there are
mismatches between the digital filter and the analog circuits in practice; those errors
cannot be cancelled completely. Usually, these residual errors (namely, the integrator
leakage) limit the performance that the systems can achieve. For switched-capacitor
implementation of analog integrators, the mismatches in capacitors and the finite gain
and bandwidth of the operational amplifier cause gain and pole errors in the integrator
(see Appendix A).
Considering the structure of Figure 4.2(a), and assuming that
(l-a)z-^ I{z) ^— ——, where a, |3 are gain error and pole error, respectively, then the final
l-{l- ^)z
output will be Y{z) = X{z)-^ E,{z)a{l- z-') + E,{z)j3z-' + E^{1- z-'). (4.16)
While the gain error a is fírst-order shaped, the pole error p appears in the output
in its entirety. Therefore, similar to the MASH structure, the achievable performance is
limited by the idealities. The pole error of the integrator can be alleviated by an op-amp
gain compensated integrator [28, 29, 30, 31, 32, 33, 34], or digital calibrations [35, 36].
However, the gain error due to the capacitor mismatches in the switched capacitor
integrator with a compensated op-amp gain cannot be improved. The gain error becomes
the major limitation factor for low oversampling ratio even if it had been first order
44
spectrally shaped. A system in which both the gain error and pole error can be shaped is
proposed in Figure 4.12.
X ^ I , (
Figure 4.12. A multi-bit system with gain and pole errors spectrally shaped.
The analog blocks are outside the dashed line while the digital blocks are inside
the dashed line. A multi-bit quantizer is used in the feedforward path, and its output is fed
into a digital sigma-delta modulator. The truncated output of the digital modulator is fed
back into the input by a single-bit DAC that is inherently linear. Therefore, the
requirement for the linearity in a multi-bit DAC is greatly reduced. The proposed
architecture has some advantages over the existing ones. For example, the pole and gain
errors of the analog integrators that limit the achievable resolution in the cascaded
architecture can be spectrally shaped. Therefore, this architecture can achieve higher
resolutions than the existing ones.
45
The output of the system can be obtained by hnearized model analysis as
Figure 6.14. The power spectral density of the input signal and harmonic distortions.
91
6.5 Second-order modulator
There are two types of switched capacitor implementation of second-order
modulators. One is based on Candy's structure in which the first integrator does not have
a unit delay while the second integrator is implemented with a unit delay. The overall
loop delay is one unit. The other version is implemented by Wooley et al. [21] and has
one unit delay in each of the two integrators. Mathematically, both give the same output
and the same noise shaping, but extensive SPICE simulation results reveal that the former
requires less output swing for the same input signal. The lesser output swing requirement
is a big advantage for low-voltage applications. Therefore, the second-order modulator
implemented in this design is based on Candy's stmcture. Figure 6.15 shows its fuUy
differential, switched capacitor CMOS implementation. It consists of two parasitic-
insensitive integrators, a comparator, and a one-bit DAC. The comparator serves as the
one-bit quantizer. The one-bit DAC is implemented such that the positive reference
voltage or the negative reference voltage will be chosen as the output based on the level
of the modulator's output bit. For example, if the output bit is 1, then the positive
reference voltage is chosen; otherwise, the negative reference voUage is chosen. The
modulator operates on a two-phase, non-overlapping clock phase.
For the first integrator, in Phase (t)2, all of the switches at the input switch are
tumed on, connecting the bottom plate of the samphng capacitor Ci to input signals Vi""
and Vi". The top plates are connected to the common mode voltage VCM. In Phase (t)l,
the top plates of the sampling switches are connected to a 1-bit DAC and the bottom
plates are connected to the inverse input of the op-amp. The 1-bit DAC is implemented
92
by connecting to the positive reference or negative reference vohage, depending on the
output of the comparator; thus, it is inherently linear. The charges are integrated into
integrating capacitors C2 and C2'. For the second integrator, in Phase 4)1, all of the
switches at the input of A2 are tumed on, connecting the bottom plate of the sampling
capacitor Ci to the output of the first integrator. The top plates are connected to the
common mode voltage VCM. The bottom plates of C3 and C3' are connected to the 1-bit
DAC and the top plates are connected to the inverse input of the op-amp that gives the
output quantization error of the second order modulator entering the next stage. In Phase
([)2, the bottom plates of the sampling switches are connected to common mode voltage
VCM, and the top plates are connected to the inverse input of the op-amp. The charges
stored in capacitors C2 and C2' are integrated by integrating capacitors C f and C f'. Both
top plates and bottom plates of the capacitors C3 and C3' are connected to the common
mode voltage VCM. The output of the second integrator enters the comparator in the
same phase. The Latch signal goes active and the decision is made right after the falling
of phase (t)2. The output of the quantizer is valid during the next phase, (\>\. Therefore, the
overall loop delay is one clock cycle. The delayed versions of clock phases, (j)ld and (t)2d,
are used to minimize the signal dependent charge injections of the sampling switches as
discussed in section 6.4.2.
The ratio of the capacitance of the samphng capacitor to that of the integrating
capacitor determines the gain of the integrator (see Appendix A). The ratios C^ I C j and
C2 / Cj^ are set to be 0.5, and the ratio of C^ I Cj^ is set to be 0.25 to increase the input
93
signal range. The size of the sampling capacitor is determined by — noise; the larger
the size, the lower the thermal noise level (see Appendix D). However, the size of the
sampling capacitor is limited by the op-amp driving capability. The larger the capacitor,
the more heavy the load of the op-amp. These intrinsic thermal noises are the main
limitation factors for high-resolution analog-to-digital converters. The critical stage is the
first integrator which is the main concem in this design. The input sampling switch
thermal noise (differential implementation) is given by
V-J = ^^^ , (6.27) "' OSR • C ,
where Cs is the sampling capacitor. Neglecting the noise in later stages, the total input
referred noise voltage including the op-amp becomes
T-^2 2Â:r V = +
4kT ' In f ^ \^
OSR - 2 sin n
OSR r r^ \^-C f K^C J
,(6.28) " OSR • C 5 3FC c
(see Appendix D) where Cc is the compensation capacitor of the two-stage op-amp, C/is
the integrating capacitor, F is the feedback factor and OSR is the oversamphng ratio.
The sampUng capacitors Ci and Ci' are made to be 4pf. Capacitors C2 and C2' are
made to be 2pf. Accordingly, Cfi and Cfi' are 8pf, Cf2 and Cf ' are 4pf, and C3 and C3' are
Ipf. For OSR=16, Ci=4pf, Cc=2.5pf, and Cf=8pf, and assuming the input parasitic
capacitance of the op-amp Ci=lpf, the total noise is given by
- , __ ( 6 4 x 1 0 - 0 ^ (6.29) 25
and
94
^lvJ=\2.SuV (6.30)
For a sinusoidal input with amplitude of 1.6V, SNR=100dB can be achieved. To
minimize the integrator leakage error of the first stage (see Appendix A), errors due to the
capacitor mismatch are minimized through careful layout of the double-poly capacitors.
The unit square geometric capacitors are used. Dummy capacitors are placed around the
outer edge of the capacitor arrays. In addition, the differential signal routing paths are
balanced in terms of parasitics.
Ref p
Ref P Ref M
Ref M Ref P
Ref M
Cl'=Cl=l/2Cfl
C2'=C2=l/2 Cf2
C3'=C3=l/4Cf2
Latch
Figure 6.15. The schematic of second-order sigma-delta modulator.
95
6.6 Pipehne ADC
The 8-bit quantizer following the second-order sigma-deha modulator is
implemented using a pipelined structure. There are many types of pipelined architectures.
Some use one bit per stage, some use multi-bits per stage, and others use a mixture of
both.
The 8-bit pipeline ADC is implemented as 1.5-bit resolution per stage with
redundancy signed digit (RSD). The major advantage is that the offsets due to the
comparator, op-amp, charge injection and capacitor mismatches can be digitally
corrected. In this design, a total offset up to V4 reference voltage can be tolerated [see
Appendix B]. The schematic is shown in Figure 6.16. In Phase ^2, the reference voltages
are charged to Ci, Ci', C2, and C2', and the comparator offset is also stored in the same
capacitors. In Phase (t)l, the input signal (either the output of the second-order modulator
or the previous stage's residual output) is entered and the decision is made right after the
signal is settled to the final value.
The residual output is obtained by a muItiply-by-2 block (inside the dotted line).
During the sampling Phase (t)l, the input signal is sampled to capacitors Cs and Cf
(Cs=Cf). The offset due to the op-amp is stored to capacitors Cs and Cf in the same phase.
In amphfication Phase (t)2, the capacitor Cf is swapped to be the feedback capacitor. Its
bottom plate is connected to the output terminal of the op-amp and the top plate is
connected to the inverse input terminal of the op-amp. The bottom plates of the capacitor
Cs are connected to the MDAC output that is either a positive reference vokage, a
96
negative reference voltage, or a common-mode voltage, depending on the decision made.
Thus, the residual output is obtained such that
V^=2V^-dy^^^. (6.31)
where V, is the residual output entering into the next stage, and V/ is the input signal
entering this stage. Vr^/is the reference voltage, anddiis the decision that has been made,
whichcanbeei ther-1, +1 orO.
The 8-bit pipelined quantizer consists of 8 such identical stages. The residual
output of the last stage enters the first-order single-bit sigma-delta modulator to be
discussed in the next section.
The capacitors Cs and Cf are made to be Ipf. They are not scaled down as they
should be in the later stages simply because of the simplicity of implementation. Each
stage is laid out symmetrically; the differential signals' routing paths are carefully
balanced to minimize the mismatches. AII signal paths are shielded from clock signals
and any other signals by metal layers connecting to the analog ground. They are placed
side by side horizontally to reduce the complexity of routing.
97
Vi_P
Vi_M
REF1_P j o / .
2áy
REFl M
Id
REF2_P _2^_
\\ \ Id
^ "
\ "
Id
Id
J/.
^ y\
y\
*ES_P
£ES_M
'-^. REF
3_
3"— S 2 /
—^ VCM
X — ~ REF_P ^
S3^. S3
REF_P
VCM
M
^ . .
\ s, h
1/. Latch
REF2 M
X
H>H> Dl '^ D l
O — Sl
o^>J^ DO' DO
o— S2
S3
M
Latch
Dl DO Sl
0 0 0
0 I 0
1 0 1
S2
0
1
0
S3
1
0
0
Vin<REF2
REF2<Vin<REFl
Vin>REFl
Figure 6.16. The schematic of one stage of the pipeline ADC.
6.7 First-order modulator
Figure 6.17 shows a fully differential, switched capacitor CMOS implementation
of the first-order sigma-delta modulator. It consists of a parasitic-insensitive integrator, a
comparator that serves as the one-bit quantizer, and a distributed one-bit DAC. The
98
modulator operates on two-phase non-overiapping clock phases. In Phase (t)l, all of the
switches in the input switch are tumed on, connecting the bottom plate of the sampling
capacitors Ci to input signals Vi'' and Vi". In the same phase, the bottom plates of C2 and
C2' are connected to a one-bit DAC output which is either a positive reference voltage or
a negative reference voltage. The top plates of Ci are Ci'are connected to common mode
voltage VCM, and those of C2 and C2' are connected to the input terminals of the op-
amp. This causes a transfer of charge from sampling capacitor C2 onto the integrating
capacitor Cf; thus, quantization errors, ERROR_P and ERROR_M, which are the inputs
of the flash ADC, are obtained by subtracting the DAC outputs from the integrator output
of the previous Phase ^2. In Phase (t)2, the bottom plates of the sampling capacitors Ci
and Ci'are connected to the common-mode voltage, and the top plates are connected to
the input terminals of the op-amp. This causes a transfer of charge from the sampling
capacitor to the integration capacitor. The integrator output is sampled by capacitors C3
and C3' in Phase (^2. The charges on C2 and C2' are discharged by connecting both the
bottom and top plates to the common mode voltage. By the end of Phase (t)2, the Latch
signal goes active, thus causing ''decision making." As stated previously, the offset
cancellation scheme is used. In Phase (|)1, the bottom plates of capacitors C3 and C3' are
connected to the common-mode voltage and the top plates are connected to the input
terminals as well as the output terminals of the preamplifier; thus, the offsets are stored in
C3 and C3'. Therefore, the offsets do not affect the decision making in the next phase.
99
REF P >
REF M ^
Vi^
vr
5^_|J
2d
REF_P t> ^ I
REF M ^
Id N
T T
1.Í C2 :3
í^ 2dJ_ _L2
a
fí-
A.2
Cf
ERROR P
i : í
î C3
ERROR M
A
C1=C2
Latch
M
Figure 6.17. The schematic of the first-order sigma-delta modulator.
6.8 Flash ADC
The schematic of a 5-bit flash ADC is shown in Figure 6.18. In the design, an
interpolating principle is applied. Its differential non-linearity (DNL) is less than that of
the conventional schemes. In Phase (t)2, all the capacitors are charged to the reference
voltages and stored. In the next phase, Phase (t)l, the input signal (quantization error of
the first-order modulator) is entered and the decision is made after the input signal is
settled to the final value. The outputs of the comparators are encoded to give the final
digital binary code.
100
V. Vi.. M
REF31 M
2d
REF31_P
REF29 M
2d
REF29_P
REF27 M
2d
REF27 P-
REF4 M
2d
REF4_ 2d
REF2 M
REF2 2d
REFO M
2d
REFO 2d
\ \ '
Figure 6.18. The schematic of a flash ADC.
101
6.9 Clock generator
6.9.1 Nonoverlapped two-phase clock generator
To make the switched capacitor circuits operate properiy, the clocks driving the
switches must be designed accordingly. The timing to tum the switches on or off is very
important in switched capacitor circuits. A schematic of a two-phase nonoverlapping
clock generator similar to that in [46] is shown in Figure 6.19. This circuit is used in most
switched capacitor circuits. It generates clock phases PHPl and PHP2, and the inverted
forms, PHIPZ and PH2PZ, in order to drive both NMOS and PMOS switches. The
delayed versions of clock phases, PHl, PH2, PHIZ, and PH2Z are also generated.
Traditionally, both rising and falling edges of the clock are delayed in order to generate
the delayed waveforms [38]. In fact, to avoid signal-dependent charge injection, only the
falhng clock edge needs to be delayed. Hence, in this design the falling edges are delayed
and the rising edges are synchronized to efficiently use the short period. The clocks
generated are further buffered to drive the switches.
6.9.2 Clock jitter effect
Clock jitter is another source that degrades the overall performance of a system
implemented in switched capacitor circuits. If the clock's period is not constant (due to
the generator and interference from the substrate), the signal is sampled in a non-uniform
clock cycle which causes distortion. Thus, the signal to noise plus distortion ratio
decreases.
102
PHI
PHIZ
> .
3 1
PHIP
2 NAM2 yc3-
NAN2
PHIPZ
2 1
PHIZ
PHl
PH2
PH2Z
PH2PZ
PH2P
Figure 6.19. The schematic of the clock generator.
_\_ 2A
-A
Figure 6.20. The uniform density function of the clock jitter.
103
The effect of the clock jitter can be derived by assuming that the sampling period
at the i ^ clock Ti = To+ATi, where TQ is the desired clock period and ATi is a random
variance with uniform distribution (the more realistic assumption might be normal
distribution) shown in Figure 6.20. For a sinusoidal input, we have the sampled discrete
signal,
V inT ) = A sin( coI.T^) = A sin( COITQ + coI.A T^) . (6.32)
Assuming that the second term inside the parenthesis of Equation 6.32 is very small, then
Equation 6.32 can be rewritten as the following:
V{nT)= A sin( ænT^) + A cos( CúnTQ ){ú)I.A T.) . (6.33)
The first term is the desired discrete signal without clock jitter, and the second term is the
distortion caused by the clock jitter. Assuming that clock jitter is white noise, the signal-
to-distortion ratio (SDR) is given by
SDR=\0\og^^^ = \0\og{OSR)-20\og{ûA)-^5dB (6 34)
arâi
For the requirement of SDR=100dB and the signal frequency of/=lMHz, A=10ps is
tolerated for oversampling ratio OSR=16.
6.10 Svstem integration and layout issues
The subsystems described above are integrated to form the entire system shown in
Figure 6.1. The die photo of the entire chip is shown in Figure 7.1. In this design,
extemal off-chip instead of on-chip reference voltages and currents are used. The
differential input enters the chip from the left, and the third and fourth pad from the top.
104
The paths are carefully layed out to balance the impedance from the input pad to the
sampling switches. The analog signal pads are placed on the left and bottom sides and the
digital signal pads are placed on the top and right sides. The routing of digital signals
such as clocks and data outputs are carefully designed to avoid line crossing and coupling
with analog signals, and they are isolated or shielded from analog signals if the line
crossing cannot be avoided. The analog signal paths are shielded from any other signals
by other metal layers connected to a ground.
In mixed-signal design, it is important to minimize the impact of noise coupling
from the digital circuitry to the sensitive analog circuitry via the conmion substrate. The
most effective way to reduce substrate noise is to create a low-impedance path from the
p+ substrate to ground. In this design, the following approaches are taken. Separate
supplies are used for digital (DVDD and DVSS) and analog (AVDD and AVSS) signals.
Because an N-well process is used, the digital and analog PMOS transistors were isolated
by separate wells. The NMOS transistors, however, interact via the common, low-
resistance p+ substrate. The noise travels almost exclusively in the p+ region because of
the low resistance. To prevent substrate noise coupling, each analog and digital block is
surrounded by a grounded guard rings and is also isolated from the others by DUF
connected to a ground, VSS. In the prototype, a separate substrate pin VSS was used to
set the substrate potential. Contacts between VSS and the substrate were made liberally in
the digital areas to provide a low-impedance path to ground for substrate noise. AVSS,
DVSS, and VSS are disjoint on-chip; however, they can be connected together off-chip.
105
The prototype of the chip has 48 pins. The pins in the analog portion are on the
right and bottom sides, and those in the digital portion are on the left and up sides. This
pin arrangement results in easy layout for the PCB design and testing.
106
CHAPTER 7
EXPERIMENTAL RESULTS
FoIIowing the design and fabrication of the prototype, the sigma-delta modulator
analog-to-digital converter was tested for dynamic linear range. Reliability
characterization, however, was not performed. The die photograph of the prototype is
shown in Figure 7.1. The chip is packaged in a 64-pin package.
//rnnnuvw Figure 7.1. Die photograph of the prototype.
107
7.1 Test setup
The basic setup for the testing is shown in Figure 7.2. A sinusoidal signal Vs is
generated by an ATS-2 audio test system (Audio Precision) and applied to the test board.
The common-mode voltage of the test signal going into the chip is set by a voltage
reference. This voltage is set at half of the supply voltage and is bypassed to the board
ground with a capacitor.
Signal Generator (ATS-2)
N^
Clock generator (Agilient 33220A) -e
Power Supply
(h ^
Iz Chip under Test
7Y
References
Mixed Signal Oscilloscope (Agilient 54641D)
XZ Computer
Figure 7.2. Testing set up.
The reference voltages are generated by extemal voltage sources connected to the
chip. Each one is bypassed to the board ground with a luF capacitor. A 50% duty-cycle
clock that serves as the extemal clock input for the chip is generated by an Aglient
33220A pulse generator. The maximum clock frequency is 20Mz. AII the digital output
codes are stored by the mixed signal oscilloscope (Agilent 5464ID) and are down-loaded
108
to a computer where the digital cancellation and filtering is done in software. Then the
FFT is performed to obtain the power spectral density, and the signal-to-noise ratio is
calculated.
The power supplies are decoupled to their corresponding ground, as close to the
chip as physically possible; 0.1 iF ceramic capacitors are used. It is worthwhile to point
out that the power supplies and the corresponding ground pins are co-Iocated on the chip
to simplify the layout of the decoupling capacitors and provide the shortest possible PCB
trace length. The supplies for clock driver, digital and output buffers are separate to avoid
modulating the clock signal with digital switching noise. AII supplies are separated from
the analog power supply. The master current to generate the bias current for all analog
circuitry is generated extemally.
A two-layer printed circuit board is used. The chip under test is in a 64-pin socket.
7.2 Dvnamic linear range
The dynamic range and noise performance of the converter can be characterized
by a signal-to-noise-plus distortion ratio (SNDR) measurement. The SNDR is defined as
the ratio of the signal power to all other noise and harmonic power in the digital output
stream. The dynamic range is defined as the difference between the largest signal and the
smallest signal (in dB) that can be detected in the presence of noise. The peak SNDR is
the highest achievable SNDR for a given converter. In the testing, for the sake of the
available facility, the clock frequency is set to be 20MHz (designed for 40MHz) and the
signal frequency is 50kHz. Figure 7.3 shows the typical power spectral density of the
109
analog-to-digital converter with input signal amplitude of-3dB respects to reference
voltage. The measured SNDR is 74.3dB at 0SR=16. The distortion and higher order
harmonics are not noticeable. The measurement results are summarized in Table 7.1.
•100
-150
/•(Hz)
Figure 7.3. Power spectral density of input signal level at -3dB.
110
Table 7.1. Summary of testing results
^ ^ SNDR
Signal level^^
-3dB
-6dB
-20dB
-40dB
-60dB
0SR=16
74.3 dB
71.5 dB
56.9 dB
37.7 dB
18.2 dB
OSR=32
81.6 dB
78.4 dB
64.2 dB
45.1 dB
24.8 dB
7.3 Discussion
The measurement results showed a maximum SNDR of 74.3 dB which is much
below the design target and system simulation results. Several factors might degrade the
performance in the testing and implementation.
1. As can be seen from Figure 7.3, the power spectral density is flattened in the low
frequency range (lOKHz to l.OMHz). Theoretically, a third-order shaping function is
expected. It is suggested that the input signal is not clean and contains noise, the first
stage has leakage due to pole and gain errors of the first integrator, or there is noise
coupling on the chip or PCB board.
111
-100
•150
m Figure 7.4. Power spectrum density of first stage output when inputs are shorted to the PCB board.
However, the experimental results when the inputs of the chip are shorted on the
PCB board showed clearly the second-order spectral shaping profile for the first stage
(Figure 7.4). The noise level in the low-frequency range is less than that of Figure 7.3
where the input signal is fed from the signal generator. The relatively high noise floor and
the flattened spectral density in the low-frequency range suggest that the input signal is
coupled with noise. It cannot be mled out that the logical switching noise of the output is
coupled back to the input signal.
2. The testing results also showed that the last stage contributes little (if any) to the
dynamic range. The outputs from the pipelined quantizer and the whole system were
112
compared; the results suggested that the last stage (first-order modulator with 5-bit flash
ADC) contributed little to the SNDR improvement. This also suggested that the pipelined
quantizer, has less resolution and the integrating linearity is not as good as designed.
Usually, op-amp gain, comparator offset, the clock timing mismatch and reference
voltage noise are the main sources for limiting the resolution and integrating linearity.
The designed op-amp gain is very high so that it exceeds the requirement used in the
system-level simulation, and it is the same as used in the first stage. The comparator
offsets has been carefully taken care of by the design and the layout. A redundant bit is
also used to minimize the effect of the comparator offset.
The clock timing skew and mismatching due to parasitics are also limiting factors
for the pipeline quantizer, especially when the sampling clock falling edge comes just
after the comparator latch's rising edge. The sampled signal will be contaminated by the
switching noise. A good timing scheme is that the comparator latch happens just after the
sampling clock falling edge. This involves timing adjustment with delay lines and
parasitic extraction simulation that was lacking in the layout phase.
113
CHAPTER 8
CONCLUSIONS
A multi-stage muhi-bit sigma-delta modulator with interstage gain scaling has
been designed and implemented in a 0.6 |im CMOS process. It employs a second-order
single-bit modulator in the main stage followed by an 8-bit quantizer (pipeline structure).
The second-stage consists of a first-order single-bit modulator followed by a 5-bit
quantizer. Gain is applied between those two stages to scale the signal level to the
reference level. System and circuit level simulations show that it achieves high speed and
high resolution. The detailed design considerations in CMOS implementation have also
been analyzed and discussed. The prototype has been fabricated in a 0.6 |i,m CMOS
process with 3.3V power supply. Experiments at testing of the prototype have also been
performed.
It has been demonstrated in the system level simulation that the proposed
modulator has the potential to achieve high speed and high resolution in analog-to-digital
conversion. However, the experimental results of the prototype showed lower
performance than designed for. Several factors and issues hmiting the achievable high
performance are discussed. Further improvements are needed in the implementation.
114
REFERENCES
1. Van De Plassche, R., Integrated analog-to-digital and digital-to-analog converters. Kluwer Academic Publishers, Norwell, MA, 1994.
2. Candy, J. C. and Temes, G. C. (Ed.): Oversampling delta-sigma data converters: theory, design, and simulation. lEEEPress, New York, 1992.
3. Norsworthy, S. R., Schreier, R., and Temes, G. C. (Ed.): Delta-sigma data converters. lEEE Press, New York, 1997.
4. Aziz, P. M., Sorensen, H. V. and Van Der Spiegel, J. "An Overview of sigma-delta converters," lEEE Signal Processing Magazine, pp. 61-84, 1996.
5. Sevenhans, T, and Chang, Z.Y., " A/D and D/A conversion for telecommunication," lEEE Circuits & Devices Magazine, pp. 33-42, 1998.
6. Razavi, B., Principles ofdata conversion system design. lEEE Press, New York, 1995.
7. Culter, C. C , " Transmission systems employing quantization," 1960 U.S. patent No. 2,927,962 (filed 1954).
8. Inose, H., Yasuda,Y., and Murakami,J., "A telemetering system code moduIation-A-2 modulation," IRE Trans.Space Elect. Telemetry, Vol. SET-8, pp. 204-209, 1962.
9. Friedman, V., "Oversampled data conversion techniques: the mix of sigma-delta modulation and DSP produces an explosion in the variety and complexity of a-d and d-a converters implemented in MOS technology," lEEE Circuits & Devices Magazine, pp. 39-46, 1990.
10. Candy, J. C , " A use of double integration in sigma-delta modulation," lEEE Trans. Commun., Vol. COM-33, pp. 269-258, 1985.
11. Uchimura, K., Hayashi, T., Kimura, T., and Iwata, A., "Oversampling a-to-d and d-to-a converters with multistage noise shaping modulators," lEEE Trans. Acoust., SpeecK Signal Processing, Vol. AASP-36, pp. 1899-1905, 1988.
12. Chao, K.C, Nadeem, S., Lee, W. and Sodini, C , "A higher order topology for interpolative modulators for oversampling A/D converters," lEEE Trans. Circuits and Systems, Vol., CAS-37, pp. 309-318, 1990.
115
13. Cataltepe, T., Kramer, A.R., Larson, L.E., Temes, G.C and Walden, R.H., " Digitally corrected multi-bit AE data converters," lEEE Intemational Symposium on Circuíts and Systems, pp. 647-650, 1989.
14. Fattaruso, J.W., Kiriaki, S., de Wit, M., and Warwar, G., "Self-calibration techniques for a second-order multi-bit sigma-delta modulator," lEEE loumal of Solid-State Circuits, Vol. 28, pp. 1216-1223, 1993.
15. Baird, R.T. and Fiez, T.S., " Improved AS DAC linearity using data weighted averaging," 1995 lEEE Inîemational Symposium on Circuits and Systems, pp.13-16, 1995.
16. Baird, R.T. and Fiez, T.S., " Linearity enhancement of multibit S-A A/D and D/A converters using data weighted averaging," lEEE Trans. on Circuits and Systems II Vol. 42, pp.753-762, 1995.
17. Cini, D., Samori, C , and Lacaita, A.L., " Double-index averaging: A novel technique for dynamic element matching in A-Z A/D converters," lEEE Trans. on Circuits and Systems, Vol. 46, pp. 353-358, 1999.
18. I^ung, B.H., and Sutarja, S., " Multi-bit A-2 A/D converter incorporating a novel class of dynamic element matching," lEEE Trans. on Circuits and Systems, Vol.39, pp. 35-51, 1992.
19. Chen, F., and Leung, B.H., "A high resolution multibit sigma-delta modulator with individual level averaging," lEEE Joumal of Solid-State Circuits, Vol. 30, pp. 453-460, 1995.
20. Leslie, T.C and Singh, B., " An improved sigma-delta modulator architecture," 1990 lEEE Intemational Symposium on Circuits andSystems, pp. 372-375, 1990
21. Brandt, B.P. and Wooley, B.A., "A 50-MHz multi-bit sigma-delta modulator for 12-b 2-MHz A/D conversion," lEEE Joumal of Solid-State Circuits, Vol. 26, pp. 1746-1756, 1991.
22. Hairapetian, A. and Temes, G. C,'" A dual-quantization multi-bit sigma-delta A/D converter," 1994 lEEE Intemational Symposium on Circuits and Systems, pp. 437-440, 1994.
23. Kinyua, M. K. and Chao, K. S., "High resolution multi-bit sigma-delta modulator architecture," Proceedings ofthe 39 Midwest Symposium on Circuits and Systems, 1997.
116
24. Brooks, T. L., Robertson, D. H., Kelly, D. F., Muro, D. and Harston, S. W., "A cascaded sigma-delta pipeline AÆ) converter with 1.25 MHz signal bandwidth and 89 dB SNR," lEEEJoumal of Solid-State Circuits, Vol. 32, pp.I896-1907, 1997.
25. Chandrasekaran, R. & Chao, K.S., "Pipelined sigma-delta modulators with interstage scalmg," Proceedings ofthe 41'' Midwest symposium on Circuits and Systems, 1999.
26. Fang, L. and Chao, K.S., "A multi-bit 2-A modulator with DAC error cancellation," Proceedings of 1999 lEEE Intemational Symposium on Intelligent Signal Processing and Communication Systems, pp. 355-358, 1999.
27. Fang, L. and Chao, K.S., "A multi-bit sigma-deka modulator with interstage feedback," Proceedings ofl998 lEEE Intemational Symposium on Circuits and Systems, pp. 583-586, 1998.
28. Nagaraj, K., Singhal, K., Viswanathan, T. R. and Vlach, J., "Reduction of finite-gain effect in switched-capacitor filters," Electronic Letters, Vol. 21, pp. 644-645, 1985.
29. Nagaraj, K., Viswanathan, T. R., Singhal, K. and Vlach, J., "Switched-capacitor circuits with reduced sensitivity to amplifier gain," lEEE Transactions on Circuit and System, Vol. 34, pp. 571-574, 1987.
30. Huang, K., Maloberti, F. and Temes, G. C , "Switched-capacitor integrators with low finite-gain sensitivity," Electronic Letters, Vol. 21, pp.1156-1157, 1985.
31. Larson, L. E. and Temes, G. C , "Switched-capacitor building blocks with reduced sensitivity to finite amphfiergain, bandwidth, and offset voltage," Proc. lEEE Int. Symp. Circuits Syst., pp. 334-338, 1987.
32. Enz, C C and Temes, G. C , ' ' Circuit techniques for reduction of the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization," Proceedings ofthe lEEE, Vol. 84, pp.1584-1614, 1996.
33. Hurst, P. J., I^vinson, R. A. and Block, D. J.,"A switched-capacitor delta-sigma modulator with reduced sensitivity to op-amp gain," lEEE Joumal ofSolid State Circuits, Vol. 28, pp. 691-696, 1993.
34. Fang, L and Chao, K.S., "A gain-compensated switched capacitor integrator," Proceedings ofthe 4(f Midwest Symposium on Circuits and Systems, pp. 229-232, 1998.
35. Yang, Y., Schreier, R., Temes, G.C and Kiaei, S., " On-hne adaptive digital error correction of dual-quantization delta-sigma modulators," Electronics Letters, vol. 28, pp.1511-1513, 1992.
117
36. Wiesbauer, A. and Temes, G.C., "On-line digital compensation of analog circuit imperfections for cascaded AZ modulators," lEEE CAS Region 8 Workshop on analog and mixed IC Design: proceedings, pp. 92-97, University of Pavia, Pavia, Italy, pp. 13-14, September 1996.
37. Marques, A.M., Peluso, V., Steyaet, M.S.J. and Sansen, W., " A 15-b resolution 2-MHz Nyquist rate A-S ADC in 1-um CMOS technology," lEEE Joumal ofSolid Staîe Circuits, Vol. 33, pp.1065-1075, 1998.
38. Geets, Y., Marques, A.M., Steyaet, M.S.J. and Sansen, W., "A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications," lEEE Joumal ofSolidState Circuits, Vol., 34, pp. 927-936, 1999.
39. Medeiro, F., P'erez-Verdu', B., and Rodri'guez-Va'zquez, A., " A 13-bit, 2.2-MS/s, 55-mW multi-bit cascade A-2 modulator in CMOS 0.7-um single-poly technology," lEEEJoumal ofSolidState Circuits, Vol., 34, pp. 927-936, 1999.
40. Hauser, M.W. and Broderson, R.W., " Circuit and technology considerations for MOS delta-sigma A/D converters," Proceedings ofthe 1986 lEEE Intemational Solid-State Circuits Symposium, pp. 1310-1315, 1986.
41. Ahuja, B.K, "An improved frequency compensation technique for CMOS operational amplifier," lEEE Joumal of Solid Sîate Circuits, Vol. 18, pp.629-633, 1983.
42. Abo, A. M., "Design for reliability of low-voltage switched-capacitor circuits", Ph.D. dissertation, University of Califomia, Berkeley, 1999.
43. Ribner, D.B., and Copeland, M.A., " Design techniques for cascoded CMOS Op amps with improved PSRR and common-mode input range," lEEE Joumal ofSolid State Circuits, Vol. 19, pp. 919-924, 1984.
44. Ferguson, P., Ganesan, Jr. A., and Adams, R., " An 18b 20 kHz dual DS A/D converter," ISSCC Dig. Tech. Papers, pp. 68-69, 1991.
45. Martin, K., "Improved circuits for the realization of switched-capacitor filters," lEEE Trans. Circuits and Systems, Vol. 27, pp. 237-244, 1980.
46. Temes, G.C., " Finite amplifier gain and bandwidth effects in switched-capacitor mtevs," lEEE Joumal ofSolid State Circuits, Vol.l5, pp. 358-361, 1980.
47. Fisher, G., and Moschytz, G., "On the frequency limitations of SC filters," lEEE Joumal ofSolidState Circuits, Vol., 19, pp. 510-518, 1984.
49. Soenen, E.G., and Geiger, R.L., " An architecture and an algorithm for fully digital correction of monolithic pipelined ADC's," lEEE Transactions on Circuits and Systems, Vol. 42, pp. 143-153, 1995.
50. Laker, K., and Sansen, W., Design ofanalog inîegrated circuits and systems. McGraw-HiIl, New York, 1994.
51. Gray, P.R., and Meyer, R.G., Analysis and design ofanalog integrated circuits. Third edition, John Wiley & Sons, Inc, New York, 1993.
119
APPENDIX A
SWITCHED CAPACITOR INTEGRATOR
Two types of integrators, inverting and non-inverting integrators, are typically
used in the implementation of a sigma-delta modulators. A non-inverting switched
capacitor integrator configuration is shown in Figure A.l. The circuit is operated with a
non-overlapped two-phase clock, (t)l and ^2 (1 and 2). Phases Id and 2d are delayed ^\
and (|)2 respectively. Capacitor Cs is the sampling capacitor, Cp is the integrating
capacitor and Cj is the input capacitance of the op-amp. In the actual implementation, the
op-amp is in fully differential form.
V'o
Figure A. 1. Half circuit of the switched-capacitor integrator.
As seen from Figure A.l, the circuit consists of an op-amp, switches and
1 capacitors. Although the ideal transfer function is either or r , it cannot be
\-z-' \-z-'
realized in practice because of capacitor mismatch, finite gain, and the bandwidth of the
op-amp.
120
A.l Operational amplifier finite gain and bandwidth effect
The effect of the finite gain and finite bandwidth of the op-amp is derived in this
section. The settling time of the op-amp is determined by the bandwidth of the op-amp. It
is very important for high frequency operation. The incomplete setthng will cause pole
error as well as gain error. For simplicity, a single pole system is assumed such that
— A p
A{s) = ^—^ where p^ is the open-Ioop pole location. s + p,
Following the approach similar to [46] [47] the transfer function with finite gain
and bandwidth can be derived. Assuming that the on-resistance of the switch is small
enough, hence the effect of the RC time constant is negligible, the response of the op-
V (s) — A p amp can be described as —— = ^— . Hence in the time domain
V,{s) s-\-p,
V,(0 = 4 v „ ( 0 - - ^ ^ (A.)
\ \P^ dt
The transfer function of the switched capacitor integrator is derived by the
following procedure.
(1) During sampling phase (t)i, the sampling capacitor, Cs, is charged to Vi{n - - ) ,
therefore at the end of 01, t = {n — )T , we have
ô c , ( « - y ) = C , W ( « - y ) . (A.2)
The integrator output Vo(t) can be derived by the conservation equation to yield