A Fully Polynomial Time Approximation Scheme for Timing Driven Minimum Cost Buffer Insertion Shiyan Hu, Zhuo Li, Charles Alpert Dept of Electrical.

Jan 19, 2018

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Technology generation (  m ) Delay (psec) Transistor/Gate delay Interconnect delay Interconnect Delay Dominates

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A Fully Polynomial Time Approximation Scheme for Timing Driven Minimum Cost Buffer Insertion Shiyan Hu*, Zhuo Li**, Charles Alpert** *Dept of Electrical.

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A Fully Polynomial Time Approximation Scheme for Timing Driven Minimum Cost Buffer Insertion Shiyan Hu, Zhuo Li, Charles Alpert Dept of Electrical.