© Digital Integrated Circuits 2nd Devices Introduction to CMOS Dr. Shiyan Hu Office: EERC 518 [email protected] Adapted and modified from Digital Integrated.

© Digital Integrated Circuits2nd Devices

Introduction toIntroduction toCMOSCMOS

Dr. Shiyan HuOffice: EERC [email protected]

Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

EE2174EE2174Digital Logic and LabDigital Logic and Lab


Goal of this chapterGoal of this chapter

Present intuitive understanding on CMOS Device Interconnect Inverter Combinational Gate


DeviceDevice


MOS Transistor Types and SymbolsMOS Transistor Types and SymbolsD

S

G

G

S

D

NMOS

PMOS

© Digital Integrated Circuits2nd Devices5

Circuit Under DesignCircuit Under Design

VDD VDD

VinVout

M1

M2

M3

M4

Vout2


Circuit on the ChipCircuit on the ChipA transistor


The MOS (Metal-Oxide-Semiconductor) The MOS (Metal-Oxide-Semiconductor) TransistorTransistor

Polysilicon Aluminum


Simple View of A TransistorSimple View of A Transistor

VGS VT

RonS D

A Switch!

|VGS|

An MOS Transistor


Silicon BasicsSilicon Basics Transistors are built on a silicon substrate Silicon forms crystal lattice with bonds to

four neighbors


Doped SiliconDoped Silicon Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity

extra electrons (doped Borons) – n-type missing electrons (doped Arsenic/Phosphorus)

more holes) – p-type

n-type p-type


NMOS TransistorNMOS Transistor

Diffusion


NMOS - IINMOS - II Refer to gate, source, drain and bulk

voltages as Vg,Vs,Vd,Vb, respectively. Vab=Va-Vb Device is symmetric. Drain and source are

distinguished electrically, i.e., Vd>Vs. P regions have acceptor (Boron) impurities,

i.e., many holes. N regions have donor (Arsenic/Phosphorus)

impurities, i.e., many electrons. N+ and P+ are heavily doped N and P

regions, respectively.


NMOS - IIINMOS - III Gate oxide are insulators, usually, silicon

dioxide. Gate voltage modulates current between

drain and source, how?


Enhancement NMOSEnhancement NMOS


Enhancement NMOS - IIEnhancement NMOS - II Does not conduct when Vgs=0, except that

there is leakage current. When Vgs is sufficiently large, electrons

are induced in the channel, i.e., the device conducts. This Vgs is called threshold voltage.


Enhancement NMOS IIIEnhancement NMOS III

Positively Charged

Negatively Charged


Enhancement NMOS - IVEnhancement NMOS - IV When Vgs is large enough, the upper part

of the channel changes to N-type due to enhancement of electrons in it. This is referred to as inversion, and the channel is called n-channel.

The voltage at which inversion occurs is called the Threshold Voltage (Vt).

A p-depletion layer have more holes than p-substrate since its electrons have been pushed into the inversion layer.

Does not conduct when Vgs<Vt (Cut-off).


Enhancement NMOS VEnhancement NMOS V


Enhancement NMOS - VIEnhancement NMOS - VI When Vgs>Vt, the inversion layer (n

channel) becomes thicker. The horizontal electrical field due to Vds

moves electrons from the source to the drain through the channel.

If Vds=0, the channel is formed but not conduct.


Case when Vds=0Case when Vds=0


Linear RegionLinear Region


Linear Region - IILinear Region - II When Vgs>Vt and Vgd>Vt, the inversion

layer increases in thickness and conduction increases.

The reason is that there are non-zero inversion layer at both source and drain (our previous analysis works for both Vgs and Vgd).This is called linear region.

Vgd>Vt means that Vgd=Vgs-Vds>=Vt, i.e., Vds<=Vgs-Vt

Vds>0 Ids depends on Vg, Vgs, Vds and Vt.


Saturation RegionSaturation Region


Saturation Region - IISaturation Region - II When Vgs>Vt and Vgd<Vt, we have non-

zero inversion layer at source but zero inversion layer at drain.

Inversion layer is said to be pinched off. This is called the saturation region.

Vgd<Vt means that Vgs-Vds<Vt, i.e., Vds>Vgs-Vt.

Electrons leaves the channel and moves to drain terminal through depletion region.


SummarySummary Three regions of conduction

Cut-off: 0<Vgs<Vt Linear: 0<Vds<Vgs-Vt Saturation: 0<Vgs-Vt<Vds

Vt depends on gate and insulator materials, thickness of insulators and so forth – process dependant factors, and Vsb and temperature – operational factors.


PMOSPMOS


PMOS - IIPMOS - II Dual of NMOS Three regions of conduction

Cut-off: 0>Vgs>Vt Linear: 0>Vds>Vgs-Vt Saturation: 0>Vgs-Vt>Vds

Current computation is the same as NMOS except that the polarities of all voltages and currents are reversed.

Mobility in PMOS is usually half of the mobility in NMOS due to process technology.


I-V characteristics (different Vt)I-V characteristics (different Vt)


I-V Characteristics III-V Characteristics II


WireWire


Modern InterconnectModern Interconnect

transmitters receivers


Modern Interconnect - IIModern Interconnect - II


0.18

Source: Gordon Moore, Chairman Emeritus, Intel Corp.

0

50

100

150

200

250

300

Technology generation (m)

Del

ay (

pse

c)

Transistor/Gate delay

Interconnect delay

0.8 0.5 0.250.25

0.150.35

Interconnect Delay Dominates Interconnect Delay Dominates


CapacitorCapacitor

A capacitor is a device that can store an electric charge by applying a voltage

The capacitance is measured by the ratio of the charge stored to the applied voltage

Capacitance is measured in Farads


33D Parasitic CapacitanceD Parasitic Capacitance

Given a set of conductors, compute the capacitance between all pairs of conductors.

-

-

--

-

- -+

+

++

+C=Q/V

1V


Simplified ModelSimplified Model

Area capacitance (Parallel plate): area overlap between adjacent layers/substrate

Fringing/coupling capacitance: between side-walls on the

same layer between side-wall and

adjacent layers/substrate

m2m2 m2

m1

m3


The Parallel Plate Model (Area Capacitance)The Parallel Plate Model (Area Capacitance)

Dielectric

Substrate

L

W

H

tdi

Electrical-field lines

Current flow

WLt

cdi

di

Capacitance is proportional to the overlap between the conductors and inversely proportional to their separation


Wire CapacitanceWire Capacitance

More difficult due to multiple layers, different dielectric

m2m2 m2

m1

m3

=3.9

=8.0

=4.0

=4.1

multipledielectric


Simple Estimation MethodsSimple Estimation Methods

C = Ca*(overlap area)

+Cc*(length of parallel run)

+Cf*(perimeter) Coefficients Ca, Cc and Cf are given by

the fab Cadence Dracula Fast but inaccurate


Accurate Methods In IndustryAccurate Methods In Industry

Finite difference/finite element method Most accurate, slowest Raphael

Boundary element method FastCap, Hicap


Wire ResistanceWire Resistance

Basic formula R=(/h)(l/w)

: resistivity h: thickness, fixed for a given technology and layer

number l: conductor length w: conductor width

hl

w


Analysis of Simple RC CircuitAnalysis of Simple RC Circuit

)()()(

)())(()(

)()()(

tvtvdt

tdvRC

dt

tdvC

dt

tCvdti

tvtvtiR

T

T

state variable

Inputwaveform

± v(t)CR

vT(t)

i(t)


Analysis of Simple RC CircuitAnalysis of Simple RC Circuit

Step-input response:

match initial state:

output response for step-input:

v0

v0u(t)

v0(1-e-t/RC)u(t)

)()()(

0 tuvtvdt

tdvRC

)()( 0 tuvKetv RCt

)()1()( 0 tuevtv RCt

0 0)( 0)0( 00 vKtuvKv


0.69RC0.69RC

v(t) = v0(1 - e-t/RC) -- waveform

under step input v0u(t)

v(t)=0.5v0 t = 0.69RC i.e., delay = 0.69RC (50% delay)

v(t)=0.1v0 t = 0.1RC

v(t)=0.9v0 t = 2.3RC i.e., rise time = 2.2RC (if defined as time from 10% to 90% of Vdd)

Elmore Delay TD = 0.69 RC


Elmore DelayElmore Delay

Delay

1. 50%-50% point delay

2. Delay=0.69RC


DelayDelay


Elmore Delay - IIIElmore Delay - III

What is the delay of a wire?


Elmore Delay – IVElmore Delay – IV

Assume: Wire modeled by N equal-length segments

For large values of N:

Precisely, should be 0.69RC/2


Elmore Delay - VElmore Delay - V

49

n1 n2

C/2 R C/2

n1 n2

R=unit wire resistance*lengthC=unit wire capacitance*length


RC Tree DelayRC Tree Delay

50

2 7

2

2

1 1 3.53.5

Unit wire cap=1, unit wire res=1

4

2

7

4

2*(1+3.5+3.5+2+2)=24 24+7*3.5=48.5

24+4*2=32

RC Tree Delay=max{32,48.5}=48.5 Precisely, 0.69*48.5


InverterInverter


Circuit SymbolsCircuit Symbols


The CMOS InverterThe CMOS Inverter

Vin=Vdd,Vout=0Vin=0,Vout=Vdd

V in Vout

CL

VDD

S

D

D

S


Its Layout ViewIts Layout View


Pass-TransistorsPass-Transistors Need a circuit element which acts as a switch When the control signal CLK is high, Vout=Vin When the control signal CLK is low, Vout is open circuited We can use NMOS or PMOS to implement it. For PMOS device, the

polarity of CLK is reversed.

NMOS based

PMOS based


NMOS Pass TransistorsNMOS Pass Transistors

Initially Vout=0. input=drain, output=source When CLK=0, then Vgs=0. NMOS cut-off When CLK=Vdd,

If Vin=Vdd (Vout=0 initially), Vgs>Vt, Vgs-Vt=Vdd-Vt<=Vds=Vdd, NMOS is in saturation region as a transient response and CL is charged.

When Vout reaches Vdd-Vt, Vgs=Vdd-(Vdd-Vt)=Vt. NMOS cut-off. However, if Vout drops below Vdd-Vt, NMOS will be turned on

again since Vgs>Vt. Thus, NMOS transmits Vdd value but drops it by Vt.


NMOS Pass Transistors - IINMOS Pass Transistors - II

If Vin=0 (and CLK=Vdd), source=input, drain=output If Vout=Vdd-Vt (note that it is the maximum

value for Vout for the transistor to be on), Vgs=Vdd>Vt, Vds=Vdd-Vt=Vgs-Vt

The NMOS is on the boundary of linear region and saturation region

CL is discharged As Vout approaches 0, the NMOS is linear region. Thus, Vout is

completely discharged. When Vout=0, Vds=0 and Ids=0, thus, the discharge is done. NMOS pass transistor transmits a 0 voltage without any

degradation


PMOS Pass TransistorsPMOS Pass Transistors

Similar to NMOS pass transistor Assume that initially Vout=0 When CLK=Vdd, PMOS cut-off When CLK=0,

If Vin=Vdd, PMOS transmits a Vdd value without degradation If Vin=0, PMOS transmits a 0 value with degradation, Vout=|Vt|


Transmission GateTransmission Gate An NMOS transmits a 0 value without degradation while transmits a

Vdd value with degradation A PMOS transmits a Vdd value without degradation while transmits a 0

value with degradation Use both in parallel, then can transmit both 0 and Vdd well. CLK=0, both transistors cut-off CLK=Vdd, both transistors are on. When Vin=Vdd, NMOS cut-off when

Vout=Vdd-Vtn, but PMOS will drag Vout to Vdd. When Vin=0, PMOS cut-off when Vout=|Vtp|, but NMOS will drag Vout to 0.


Power DissipationPower Dissipation


Where Does Power Go in CMOS?Where Does Power Go in CMOS?

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors


Dynamic Power DissipationDynamic Power Dissipation

Power = CL * Vdd2 * f

Need to reduce CL, Vdd, and f to reduce power.

Vin Vout

CL

Vdd

Not a function of transistor sizes


Dynamic PowerDynamic Power

Dynamic power is due to charging/discharging load capacitor CL

In charging, CL is loaded with a charge CL Vdd which requires the energy of QVdd= CL Vdd2, and all the energy will be dissipated when discharging is done. Total power = CL Vdd2

If this is performed with frequency f, clearly, total power = CL Vdd2 f


Dynamic Power- IIDynamic Power- II

If the waveform is not periodic, denote by P the probability of switching for the signal

The dynamic power is the most important power source It is quadratically dependant on Vdd It is proportional to the number of switching. We can slow down the

clock not on the timing critical path to save power. It is not dependent of the transistor itself but the load of the transistor.


LeakageLeakage

Vout

Vdd

Sub-ThresholdCurrent

Drain JunctionLeakage

Sub-Threshold Current Dominant FactorSub-threshold current one of most compelling issuesin low-energy circuit design.


Subthreshold Leakage ComponentSubthreshold Leakage Component


Principles for Power ReductionPrinciples for Power Reduction

Prime choice: Reduce voltage Recent years have seen an acceleration in

supply voltage reduction Design at very low voltages still open

question (0.5V) Reduce switching activity Reduce physical capacitance


Combinational GateCombinational Gate


CMOS Combinational CircuitsCMOS Combinational Circuits Implementation of logic gates and other structures using

CMOS technology. Basic element: transistor 2 types of transistors:

n-channel (nMOS) and p-channel (pMOS) Type depends on the semiconductor materials used to implement

the transistor. We want to model transistor behavior at the logic level in order to

study the behavior of CMOS circuits view pMOS and nMOS transistors as swithes.


Networks of SwitchesNetworks of Switches

Use switches to create networks that represent CMOS logic circuits.

To implement a function F, create a network s.t. there is a path through the network whenever F=1 and no path when F=0.

Two basic structures Transistors in Series Transistors in Parallel


Transistors in Series/ParallelTransistors in Series/Parallel

nMOS in ParallelnMOS in Series

X

Y

a

b

X:X

Y:Y

a

b

pMOS in Series

X

Y

a

b

X:X’

Y:Y’

a

b

Path between points a and b exists if both X and Y are 1 X•Y

Path between points a and b exists if both X and Y are 0 X’•Y’

Path between points a and b exists if either X or Y are 1 X+Y

X Y

b

a

X:X Y:Y

b

a

pMOS in Parallel

X Y

b

a

X:X Y:Y

b

a Path between points a and b exists if either X or Y are 0 X’+Y’


Networks of Switches (cont.)Networks of Switches (cont.)

In general:1. nMOS in series is used to implement AND logic

2. pMOS in series is used to implement NOR logic

3. nMOS in parallel is used to implement OR logic

4. pMOS in parallel is used to implement NAND logic

Observe that: 1 is the complement of 4, and vice-versa 2 is the complement of 3, and vice-versa


Fully Complementary CMOS NetworksFully Complementary CMOS NetworksBasic GatesBasic Gates


Fully Complementary CMOSFully Complementary CMOSComplex GatesComplex Gates

Given a function F:

1. First take the complement of F to form F’

2. Implement F’ as an nMOS net and connect it to GRD (pull-down net) and F.

3. Find dual of F’, implement it as a pMOS net and connect it to +V (pull-up net) and F.

4. Connect switch inputs.


Fully Complementary CMOS NetworksFully Complementary CMOS NetworksComplex Gates - ExampleComplex Gates - Example

F’ = A’B’+A’C=A’(B’+C)

F = (A+B)(A+C’)

© Digital Integrated Circuits 2nd Devices Introduction to CMOS Dr. Shiyan Hu Office: EERC 518 [email protected] Adapted and modified from Digital Integrated.

Documents

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devices enhancement

devices circuit

devices goal

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