A DC–DC Converter Based on the Three-State Switching Cell for High Current and Voltage Step-Down Applications

398 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013

A DC–DC Converter Based on the Three-StateSwitching Cell for High Current and Voltage

Step-Down ApplicationsJuan Paulo Robles Balestero, Fernando Lessa Tofoli, Grover Victor Torrico-Bascope, Member, IEEE,

and Falcondes Jose Mendes de Seixas

Abstract—This paper presents a pulsewidth modulation dc–dcnonisolated buck converter using the three-state switching cell,constituted by two active switches, two diodes, and two coupledinductors. Only part of the load power is processed by the activeswitches, reducing the peak current through the switches to halfof the load current, as higher power levels can then be achievedby the proposed topology. The volume of reactive elements, i.e., in-ductors and capacitors, is also decreased since the ripple frequencyof the output voltage is twice the switching frequency. Due to theintrinsic characteristics of the topology, total losses are distributedamong all semiconductors. Another advantage of this converter isthe reduced region for discontinuous conduction mode when com-pared to the conventional buck converter or, in other words, theoperation range in continuous conduction mode is increased, asdemonstrated by the static gain plot. The theoretical approach isdetailed through qualitative and quantitative analyses by the ap-plication of the three-state switching cell to the buck converteroperating in nonoverlapping mode (D < 0.5). Besides, the math-ematical analysis and development of an experimental prototyperated at 1 kW are carried out. The main experimental results arepresented and adequately discussed to clearly identify its claimedadvantages.

Index Terms—Buck converter, dc–dc converters, three-stateswitching cell (3SSC).

I. INTRODUCTION

PULSEWIDTH modulation (PWM) dc–dc converters arewidely employed in numerous applications, e.g., audio am-

plifiers [1], uninterruptible power supplies [2], fuel cell poweredsystems [3], and fork lift vehicles [4], although many other ones

Manuscript received February 14, 2012; revised March 29, 2012; acceptedApril 24, 2012. Date of current version September 11, 2012. This work was sup-ported by the National Council for Scientific and Technological Development,Coordenacao de Aperfeicoamento de Pessoal de Nıvel Superior, Fundacao deAmparo a Pesquisa do estado de Minas Gerais, and the Fundacao de Amparo aPesquisa do Estado de Sao Paulo. Recommended for publication by AssociateEditor K. Ngo.

J. P. R. Balestero is with the Federal Institute of Education, Scienceand Technology of Santa Catarina, Santa Catarina 89813-000, Brazil (e-mail:[email protected]).

F. L. Tofoli is with the Department of Electrical Engineering, FederalUniversity of Sao Joao del-Rei, Sao Joao del-Rei 36307-352, Brazil (e-mail:[email protected]).

G. V. Torrico-Bascope is with the Eltek Energy AB, Stockhom 191 24,Sweden (e-mail: [email protected]).

F. J. M. de Seixas is with the Department of Electrical Engineering,University Estadual Paulista, Sao Paulo 18618-970, Brazil (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2197419

can be easily found. Conventional hard switching converterswith a single active switch such as buck, boost, buck–boost, Cuk,single-ended primary-inductance converter (SEPIC), and Zetatypically present low power density, while attempts to furtherminimize the size of filter elements lead to increased switchinglosses, compromising the efficiency of the converters.

In order to overcome such limitation, several soft switchingapproaches have been introduced in the literature. Soft switchingis supposed to reduce the overlap between voltage and currentduring the commutation, and can be classified in either activeor passive methods, as one must choose between the aforemen-tioned snubbers for a given application.

Active methods can reduce the switching losses by using aux-iliary switches. Unfortunately, an auxiliary switch increases thecomplexity of both power and control circuits. Synchroniza-tion problems between control signals of the switches duringtransient also complicate the control strategy. Circuit cost is in-creased and reliability is affected by using active snubbers [5].

A passive lossless snubber can effectively restrict switchinglosses and electromagnetic interference (EMI) noise using noactive components and no power dissipative components. No ad-ditional control is needed and no circulating energy is generated.Circuit structure is as simple as RCD (resistor–capacitor–diode)snubbers while circuit efficiency is as high as active snubbersand resonant converters [6], [7]. Low cost, high performance,and high reliability are the distinct advantages of a passive loss-less snubber [8]. However, soft switching may not be achievedfor the entire load range, and besides the accurate design of theresonant tank is not a trivial task, even what is also valid whenactive snubbers are considered [9].

Significant effort has then been made to improve the charac-teristics of the traditional nonisolated dc–dc converters in thelast few years. For instance, the study of a dc–dc buck con-verter with three-level buck clamping, zero voltage switching(ZVS), active clamping, and constant-frequency PWM is pro-posed in [10]. A family of converters is also derived, whichcombines the advantages of reduced voltage across the switchesusing a three-level commutation cell, and decreased switchinglosses obtained from a soft switching technique.

As the power rating increases, it is often required to asso-ciate converters in series or in parallel. By using interleavingtechniques in high current applications, the currents through theswitches become just fractions of the input current [11]. Inter-leaving effectively doubles the switching frequency and alsopartially cancels the input and output ripples, as the size of

0885-8993/$31.00 © 2012 IEEE

BALESTERO et al.: DC–DC CONVERTER BASED ON THE THREE-STATE SWITCHING CELL 399

the energy storage inductors and differential-mode EMI filter inresulting implementations can be reduced [12].

In the last few years, many converters based on the three-state switching cell (3SSC) have been proposed. The cell can beobtained by the association of two two-state PWM cells (2SSC)interconnected to a center tap autotransformer, from which novelconverters can be derived. General advantages over conventionaltopologies can be achieved, e.g., the inductor is designed fortwice the switching frequency, with consequent reduction of sizeand weight; the current through the switches is half of the inputcurrent; part of the input power is delivered to the load by thetransformer instead of the main switches, consequently reducingconduction and commutation losses; lower cost switches can beused.

Many dc–dc converters based on the 3SSC have been intro-duced in the last few years [13]–[18]. However, the aforemen-tioned works are basically concerned with high voltage gainboost-based topologies dedicated to dc voltage step-up appli-cations. Literature does not present further detailed studies re-garding the remaining dc–dc nonisolated topologies using the3SSC.

Within this context, this paper proposes the complete studyof the dc–dc converter based on the 3SSC. Initially, some the-oretical background on the 2SSC and the 3SSC is presented,leading to the conception of the improved buck converter us-ing the so-called cell type B. Then, the converter operationin nonoverlapping mode (NOM) is described, where the maincharacteristics of the topology are discussed. An experimentalprototype is then implemented, while the detailed discussionof experimental results is supposed to validate the theoreticalassumptions and also demonstrate the merit of the proposal.

II. CONCEPTION OF THE 3SSC AND THE PROPOSED

BUCK CONVERTER

The canonical switching cell is an approach that allows us toobtain and classify the classical dc–dc converters, from whichsome families of converters can be derived [19]. Buck, boost,and buck–boost converters, which are second-order systems, aswell as Cuk, SEPIC, and Zeta, which are fourth-other systems,have a single switching cell that is part of their respective powerstages. Literature has also shown appreciable effort to improvethe characteristics of the original structures, even though thenovel resulting topologies are more complex approaches withhigher component count.

The aforementioned switching cell is composed of three ter-minals, which are active, passive, and common. Its behavior isbased on the complementary operation of two switches con-nected by the common terminal. In other words, one switch isturned ON while the remaining one remains turned OFF, andvice versa. Therefore, this arrangement can be called 2SSC.

With the aim of achieving higher power density, switchingfrequency is usually increased, with consequent reduction ofsize and volume of reactive elements. Consequently, it leads tothe increase of both switching losses and the volume of heatsinks. This practice, therefore, compromises the very reductionof physical dimensions in static power converters.

The aforementioned losses must then be reduced, and softswitching circuits using the resonance phenomenon have beenwidely proposed as a possible solution. By using well-knowntechniques such as ZVS and zero current switching, the perfor-mance of converters can be improved. However, even thoughswitching losses are mitigated or eliminated, conduction lossesare still of major concern and may even increase depending onthe adopted snubber.

With the aim to further reduce voltage and/or current stress,the association of semiconductors or even converters in series orin parallel has been thoroughly investigated. Other topologiescan also be obtained, such as multilevel converters [20].

It is also possible to increase the efficiency by the use ofthe 3SSC, which has been employed in recent publications [21]and is originally derived from the dc–dc push–pull converter. Inorder to obtain the cell type B, let us consider the classical push–pull topology shown in Fig. 1, which is formed by switches S1and S2 , two rectifier diodes D1 and D2 in the secondary side,and a high-frequency transformer. The circuit corresponds to adc–ac–dc conversion system. If the central tap transformer isconsidered ideal with unity turns ratio, the primary and sec-ondary windings can be replaced by the respective magnetizinginductances, which are coupled and constitute an autotrans-former. The negative terminal of the output stage representedby Vo , which was formerly connected to the central tap of thetransformer, is then connected to the negative pole of the inputvoltage source to generate a boost topology, as seen in Fig. 1(c).Otherwise, if connected to the positive pole, a buck–boost con-verter is derived. The cell type B can then be applied to thedc–dc buck converter substituting the 2SSC, while the resultingtopology is presented in Fig. 2.

It can be seen that the 3SSC is formed by two controlledswitches S1 and S2 , two diodes D1 and D2 , one autotransformerT1‖T2 , and one inductor L. Even though the resulting cell seemsmore complex with higher component count than the conven-tional 2SSC, the advantages over its counterpart will be clearlydemonstrated in this study. For instance, the use of the 3SSCmay lead to the need of switches with reduced current rating,which is desirable in step-down high-current applications.

Considering that the operation of the switch and the diodeof a same leg is complementary, two modes regarding themain switches can be obtained for the proposed topology. Ifthe duty cycle D is higher than 0.5, overlapping mode (OM)occurs, where two switches remain turned ON at the sametime. Otherwise, if D < 0.5, the converter operates in NOM,while only one switch remains turned ON in a given operatingstage.

The proposed approach can be seen as the integration of theinterleaving technique and the 3SSC. The following advanta-geous characteristics can be then addressed to the introducedtopology:

1) Reduced size, weight, and volume of magnetics, which aredesigned for twice the switching frequency analogouslyto the interleaved buck converter.

2) The current stress through each main switch is equal tohalf of the total output current, allowing the use of semi-conductors with lower current ratings.

400 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013

Fig. 1. 3SSC type B.

Fig. 2. Buck converter based on the 3SSC.

3) Losses are distributed among the semiconductors, leadingto better heat distribution and consequently more efficientuse of the heat sinks.

4) Part of the input power, i.e., 50%, is directly transferredto the load through the diodes and the coupled inductors(autotransformers), and not through the main switches.As a consequence, conduction and switching losses arereduced. This is the main difference between the func-tionality of this approach and that of the interleaved bucktopology.

5) The use of the 3SSC allows the parallel connection ofswitches and, therefore, inexpensive power devices anddrives can be used.

6) Energy is transferred from the source to the load duringmost part of the switching period, which is a distinct char-acteristic of the proposed converter, since in other buck-type converters, it only occurs during half of the switchingperiod. As a consequence, reduction of current peaks andalso conduction losses are expected.

7) The drive circuit of the main switches becomes lesscomplex because they are connected to the same refer-ence node, what does not occur in the interleaved buckconverter.

For the detailed description of the dc–dc buck converter usingthe 3SSC in NOM, the following assumptions are made:

1) the converter operates in steady state;

BALESTERO et al.: DC–DC CONVERTER BASED ON THE THREE-STATE SWITCHING CELL 401

Fig. 3. Operating stages of the proposed converter in NOM-CCM. (a) First stage. (b) Second stage. (c) Third stage. (d) Fourth stage.

2) switching frequency is constant and PWM is employed todrive the switches;

3) the gating signals of the switches are 180◦ displaced;4) the turns ratio of the autotransformer is unity;5) the magnetizing current is much lower than the load

current;6) all semiconductor and passive elements are ideal.

A. Operation in NOM and Continuous Conduction Mode(CCM) (D < 0.5)

The converter operation can be defined according to fouroperating stages as shown in Fig. 3. The respective main theo-retical waveforms are presented in Fig. 4, where each one of thevariables is defined as follows:

1) Vg (S1) , Vg (S2)—gating signals applied to switches S1 andS2 , respectively;

2) IL —current through inductor L, while the maximum andminimum values assumed by this quantity are IM and Im ,respectively;

3) IS1—current through switch S1 ;4) ID 1—current through diode D1 ;5) IV o—current through the output stage, which is the sum

of the currents through the output capacitor IC o and theload Io ;

6) VS1—voltage across switch S1 ;7) VD 1—voltage across diode D1 ;8) VL —voltage across inductor L.

Fig. 4. Main theoretical waveforms for NOM-CCM.

402 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013

First stage [t0 , t1] [see Fig. 3(a)]: Initially, switch S1 isturned ON, while switch S2 is turned OFF. The current throughthe inductor is divided in two parts. The first one flows throughT1 and D2 with energy being delivered to the load. The secondone flows through T2 and S1 . Current sharing is maintainedsince the number of turns for T1 and T2 is the same. The currentthrough L increases linearly. Windings T1 and T2 have the sameimpedance, and the voltages across them are equal to half of theinput voltage Vi . This stage finishes when S1 is turned OFF.

Second stage [t1 , t2] [see Fig. 3(b)]: Switch S1 is turnedOFF, while switch S2 remains OFF. The voltage across inductorL is inverted. Diode D1 is forward biased while D2 remainsconducting. The energy stored in L during the previous stage isthen transferred to the load. The current flows through T1‖T2 ,according to the given polarity, what causes the magnetic flow inthe core to be null. The current returns to the source analogouslyto the previous stage. This stage finishes when S2 is turned ON.

Third stage [t2 , t3] [see Fig. 3(c)]: Due to symmetry of thecircuit, this stage is similar to the first one, although switch S2 isturned ON instead and S1 remains turned OFF. Diode D1 keepsconducting and D2 is reverse biased.

Fourth stage [t3 , t4] [see Fig. 3(d)]: This stage is similar tothe second one, as the same equivalent circuit and operatingconditions are valid in this case.

1) Output Characteristic of the Converter: The static gainexpressions for the converter operating in CCM, discontinuousconduction mode (DCM), and critical conduction mode (CRM)are given by (1), (2), and (3), respectively. The procedure usedto obtain such expressions is the same as that employed in [21]and will not be described here in detail.

Expression (1) clearly shows that the static gain for the pro-posed converter in CCM is the same as that of the conventionalbuck converter

GCCM NOM =V0

Vi= D (1)

GDCM NOM =12· D2

γ + D2 (2)

GCRM NOM =14± 1

4·(√

1 − 16γ)

(3)

where

γ =2LIo

ViTs(4)

andIo—output current [A];Ts—switching period [s];D—duty cycle.

From expressions (1)–(3), it is possible to determine the staticgain of the proposed converter operating at D < 0.5, as theobtained curves are presented in Fig. 5.

Analogously to the conventional buck converter, the outputvoltage is a function of the load current in DCM, and this op-erating region must be avoided. It is worth to mention that themaximum static gain in CRM occurs at γ = 0.0625 and D =0.25 for the proposed converter. Considering the classic buckconverter, the maximum gain in CRM is verified when γ = 0.25

Fig. 5. Comparison between static gain curves of the conventional and pro-posed buck converters.

Fig. 6. Ripple current through the inductor in NOM.

and D = 0.5. In practical terms, it means that the CCM regionis wider for the proposed converter. That is, for a given operat-ing point, the necessary inductance becomes one fourth of thatrequired for the classical buck converter.

2) Filter Elements: The ripple current through the inductor(ΔIL ) is given as

ΔIL =Ts (1 − 2D) D

2LVi. (5)

Expression (5) can be normalized so that the ripple current isobtained as

β =L · ΔIL

TsVi=

(1 − 2D) D

2. (6)

Expression (6) is plotted in Fig. 6, where one can see that themaximum ripple current occurs at D = 0.25 and β = 0.0625.

BALESTERO et al.: DC–DC CONVERTER BASED ON THE THREE-STATE SWITCHING CELL 403

TABLE IDESIGN SPECIFICATIONS

Parameter Value Input voltage Vi=200 VInductor current ripple (20% of the input current)

IL=3.33 A

Switching frequency fs=30 kHzRated output power Po=1 kW Output voltage Vo=60 V Output voltage ripple Vo=0.6 V

By choosing arbitrarily the ripple current, the inductance canbe determined as

L =(1 − 2D) DTsVi

2ΔIL= β

TsVi

2ΔIL. (7)

Considering the maximum ripple current which representsthe worst case, the inductance can be obtained by

L =TsVi

16ΔIL. (8)

The critical inductance, whose value assures operation inCCM, is given by

Lcrit = γViTs

4Io. (9)

The output capacitor can be determined as

Co =ΔIL

4πfsΔVo(10)

whereΔVo is the output voltage ripple [V] andfs is the switching frequency [Hz].

III. DESIGN PROCEDURE

A design example of the proposed 3SSC buck converter,which is supposed to operate in NOM, is presented as follows.The specifications are listed in Table I and were used in theimplementation of an experimental prototype. Some importantcalculations are performed in order to show the loss mechanism.It is also worth to mention that both conduction and commuta-tion losses are estimated under rated load condition.

A. Preliminary Calculation

Considering the operation in CCM, the static gain is

G = D =60200

= 0.3. (11)

The output current is

Io =Po

Vo=

100060

= 16.667A. (12)

B. Inductor

The inductance is given by (7) as

L =(1 − 2 × 0.3) × 0.3 × 200 × 33.33 × 10−6

2 × 3.33= 120 μH.

(13)

The rms and peak currents through the inductor are given by(14) and (15), respectively

IL(rms) =

√

I2o +

[V 2

i T 2s D2(2D − 1)2

48L2

]= 16.69A (14)

IL(pk) = I0 +ViTs(1 − 2D)D

4L= 18.33A (15)

The core loss in the inductor can be obtained from

PLb(core) = ΔB2.4 (KH fL + KE f 2

L

)Ve = 0.098W (16)

where ΔB = 0.04 is the magnetic flux variation, KH = 4 ×10−5 is the hysteresis loss coefficient, fL = 2 × fs = 60 kHzis the operating frequency of the inductor, KE = 4 × 10−10 isthe eddy-current loss coefficient, and Ve = 42.5 cm3 is the corevolume.

The copper loss in the inductor is given by

PL(copper) =ρ · lLt · NL · I2

L(rms)

nL · Sf= 0.976W (17)

where ρ = 2.078 ×10−6 Ω·m is the copper resistivity at 70 ◦C,lLt = 11.6 cm is the average length of one turn, NL = 25 is thenumber of turns of the inductor, nL = 15 is the number of wiresin parallel, and Sf = 0.003221 cm is the cross-sectional area ofcopper wire AWG23.

C. Autotransformer

The maximum voltage across the windings is

VT 1 =Vi

2= 100V (18)

The rms and peak currents through transformer T1 are givenby (19) and (20), respectively

IT (rms) =12

√

I2o +

[V 2

i T 2s D2(2D − 1)2

48L2

]= 8.35A (19)

IT (pk) =Io

2+

ViTs(1 − 2D)D8L

= 9.17A. (20)

The core loss in the autotransformer can be obtained from

PT (core) = ΔB2.4 (KH fT + KE f 2

T

)Ve = 0.94W (21)

where ΔB = 0.15 is the magnetic flux variation, KH = 4 ×10−5

is the hysteresis loss coefficient, fT = 2 × fs = 60 kHz is theoperating frequency of the transformer, KE = 4 × 10−10 is theeddy-current loss coefficient, and Ve = 42.5 cm3 is the corevolume.

The copper loss in the windings of the transformer is givenby

PT (copper) =2ρlT tNT I2

T (rms)

nT Sf= 0.94W (22)

where ρ = 2.078 ×10−6 Ω·m is the copper resistivity at 70 ◦C,lT t = 11.6 cm is the average length of one turn, NT = 14 is thenumber of turns of the 1:1 autotransformer, nT = 5 is the number

404 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013

of wires in parallel, Sf = 0.005176 cm is the cross-sectional areaof copper wire AWG20.

D. Main Switches

The threshold voltage across one main switch is

VS1 = Vi = 200V. (23)

The average current IS1(avg) and the rms current IS1(rms)through the switch are given by (24) and (25), respectively

IS1(avg) =12× IO × D = 2.5A (24)

IS1(rms) =

√√√√D

4·[

I2o +

V 2i T 2

s D2 (2D − 1)2

48L2

]

= 4.57A.

(25)MOSFET 5015VBR manufactured by APT was then chosen

as the main switch, whose characteristics are drain to sourcevoltage VDS = 500 V, diode forward voltage VS (F ) = 1.3 V,drain current ID = 32 A, on resistance RDS(on) = 0.15 Ω, risetime tr = 14 ns, and fall time tf = 11 ns.

The conduction loss regarding each main switch is

PS1(cond.) =VS1(F ) · IS1(avg) + RDS(on) · I2S1(rms) = 6.383W

(26)The switching loss during turn ON and turn OFF for a single

switch is

PS1(sw) =fs

2(tr + tf )IS1(avg)VS1 = 0.188W. (27)

E. Main Diodes

The reverse voltage across one diode isVD1 = Vi = 200V. (28)

The average current ID 1(avg) , the rms current ID 1(rms) , andthe peak current ID 1(pk) through the diode are given by (29),(30), and (31), respectively

ID1(avg) =IO

2(1 − D) = 5.83A (29)

ID1(rms) =12

√√√√(1 − D)·

[

I2o +

V 2i T 2

s D(D − 1

2

)2

12L2

]

=6.984A

(30)

ID1(pk) =Io

2+

ViTs(1 − 2D)D8L

= 9.17A. (31)

Ultrafast diode RHRP840 was then chosen, whose charac-teristics are reverse voltage VD (rev .) = 400 V, forward voltageVD (F ) = 1.7 V, average forward current IF = 8 A, and reverserecovery time trr = 30 ns.

Estimating the intrinsic resistance of the diode from the curvesgiven in the datasheet as RD = 50 mΩ, conduction loss regardingeach diode becomes

PD1 = VD1(F )ID1(avg) + RD1I2D1(rms) = 12.35W. (32)

Fig. 7. Comparison between the theoretical efficiency curves for the conven-tional buck and 3SSC-based buck converter.

Switching losses regarding the diodes are given as

PS1(sw) =12

(VD (F )P − VD (F )

)ID1(avg)trisefs

+ VD1Qrrfs = 0.3366W (33)

where VD (F )P = 2.1 V is the maximum value assumed by theforward voltage, trise = 18 ns is the rise time of the currentthrough the diode, and Qrr = 56 nC is the amount of chargestored in the intrinsic capacitance of the diode.

F. Theoretical Comparison With Other Buck-Based Topologies

The proposed converter can be compared with similar ap-proaches from the theoretical point of view, such as the clas-sical buck converter. Since the current stress through the mainswitches is reduced analogously to the interleaved buck con-verter, this topology will also be considered in the analysis.

The aforementioned converters were then properly designedaccording to the specifications in Table I. The same semicon-ductors chosen for the 3SSC-based buck converter were used toestablish a fair comparison. Losses in semiconductors and mag-netic elements were then estimated by using the methodologydescribed in Section III-A–III-E, considering the output powerranging from 100 W to 1 kW. The theoretical efficiency curvesfor the converters are shown in Fig. 7, where it can be seen thathigh efficiency results for the proposed converter over the entireload range, what is basically due to the significant reduction ofthe current stress through the semiconductors and the use of the3SSC.

The performance of the interleaved buck converter is similarto that of the proposed topology, basically due to parallel oper-ation of the semiconductors. Considering the circuit in Fig. 2,it can be seen that the drive circuitry for switches S1 and S2does not demand isolation because their source terminals areboth connected to the same reference node, what is an advan-tage over the interleaved topology. Besides, current sharing isof great concern in interleaving converters [22], [23], what isassured in the 3SSC buck converter due to the autotransformerwithout the use of special control schemes.

It is also worth to establish a fair comparison with similarapproaches that exist in the literature. For instance, the workproposed in [24] introduces an interleaved buck converter with

BALESTERO et al.: DC–DC CONVERTER BASED ON THE THREE-STATE SWITCHING CELL 405

Fig. 8. Voltage (CH2) and current (CH3) waveforms for switch S1 .

coupled inductors in a same magnetic core. A small capacitoris also introduced to obtain a turn-off snubber, while switchinglosses are minimized and conduction losses are increased dueto additional amount of circulating reactive energy. Besides,furthermore, soft switching for the entire load range is difficultto obtain when dealing with passive snubbers [25].

A synchronous dc–dc buck converter with interleaved mul-tiphase and integrated coupled inductors is studied in [26].Of course, the aforementioned topology employs two switchesper phase and may not be competitive in terms of componentcount and robustness with the conventional interleaved con-verter. However, the coupled inductors cannot be treated as twoindividual inductors because of the coupling effect, and the mu-tual inductance between the windings will affect the converteroperation. This inconvenience is not verified in the proposedtopology.

IV. EXPERIMENTAL RESULTS

An experimental prototype was then implemented accordingto the previous session. Fig. 8 presents the voltage and currentwaveforms regarding switch S1 , which are similar to those onesfor switch S2 . An RCD snubber could be employed to alleviatethe voltage peak across the switch, although it may reduce theefficiency.

Fig. 9 shows the voltages across switches S1 and S2 , as wellas the currents through inductor L and switch S2 . It becomesevident that the switching frequency is half of the ripple currentfrequency, what leads to the reduction of magnetic elements.

Fig. 10 represents the voltages across D1 (CH1) and D2(CH2), and also the currents through D1 (CH3) and D2 (CH4).It can be seen that overlapping occurs for the diodes during thesecond and fourth operating modes, as predicted in Fig. 3(b) and(d), respectively. However, it must be mentioned that the mainswitches do not remain turned ON simultaneously.

Fig. 11 shows the voltages across D1 and S1 , and also theirrespective currents. It becomes evident that the operation of suchsemiconductor elements is complementary.

Fig. 9. Voltages across switches S1 (CH1) and S2 (CH2), current throughinductor L (CH3), and current through switch S2 (CH4).

Fig. 10. Voltages across D1 and D2 (CH1 and CH2, respectively) and currentsthrough D1 and D2 (CH3 and CH4, respectively).

Fig. 11. Voltages across D1 and S1 (CH1 and CH2, respectively) and currentsthrough D1 and S1 (CH3 and CH4, respectively).

406 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013

Fig. 12. Static gain as a function of the output current.

Fig. 13. Efficiency as a function of the output power.

Fig. 12 presents the variation of the static gain plotted as afunction of the output current. Experimental results seem to bevery close to those predicted in the theoretical analysis.

The experimental prototype was evaluated over a wide loadrange and the efficiency curve of the converter operating at30 kHz is presented in Fig. 13. Even though the efficiency curvedoes not match the one shown in Fig. 7 exactly, the profile ofboth plots is similar. That is, the use of the 3SSC leads to highefficiency, which is higher than 94% practically over the entireoutput power range, demonstrating the merit of the proposedconverter. This is not observed in typical buck topologies thatare not based on the 3SSC. Energy transfer from the source tothe load occurs during almost the entire switching period forthe 3SSC topology. On the other hand, in the conventional buckconverter, it does only occur during part of the switching period,namely when the main switch is OFF and the output capacitor ischarged. It certainly contributes for the reduction of the currentpeak in the switches causing efficiency to increase.

V. CONCLUSION

A dc–dc buck converter based on the 3SSC has been pre-sented. When the 3SSC is employed, the current is distributedamong the semiconductors. Furthermore, only part of the energyfrom the input source flows through the active switches, whilethe remaining part is directly transferred to the load withoutbeing processed by these switches, i.e., this energy is delivered

to the load through passive components, such as the diodes andthe transformer windings.

Despite the increase in the number of semiconductors, thecurrent levels on these devices are reduced, enabling the useof inexpensive switches and simplified command circuits be-cause the isolated drive is not required like in the interleavedbuck converter. In front of these characteristics, its use is rec-ommended for high-power high-current applications where thetraditional approach may be inadequate, while good currentsharing is achieved.

In addition, the overall losses are distributed among all semi-conductors, reducing the heat sink efforts. The reactive compo-nents operate with twice the switching frequency, with signifi-cant reduction in weight and volume of such components.

Considering the operation in NOM (D < 0.5) and the sameratings, the following characteristics can be addressed with the3SSC-based converter if compared with the conventional bucktopology:

1) increased number of semiconductor elements;2) the operating area in CCM is wider;3) the ripple current through the inductor is reduced, as well

as the currents through the switches;4) reactive elements are designed for twice the switching

frequency, causing the required critical inductance to besmaller, for instance;

5) only 50% of the power is delivered to the load through themain switches due to the magnetic coupling between thetransformer windings.

Besides, an important advantage of the proposed converteroperating in OM (D > 0.5) is the continuous nature of the inputcurrent, which is inherently discontinuous in the conventionalbuck converter, what may lead to the use of an input filter forsome applications.

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Juan Paulo Robles Balestero was born on Febru-ary 20, 1978, in Jales, Brazil. He received the B.Sc.and M.Sc. degrees in electrical engineering from theState University of Sao Paulo, Ilha Solteira, Brazil,in 2004 and 2006, respectively.

He is currently a Professor with the Federal Insti-tute of Education, Science and Technology of SantaCatarina, Chapeco, Brazil. His research interests in-clude dc–dc converters and converter topologies.

Fernando Lessa Tofoli was born on March 11, 1976,in Sao Paulo, Brazil. He received the B.Sc., M.Sc.,and Ph.D. degrees in electrical engineering from theFederal University of Uberlandia, Uberlandia, Brazil,in 1999, 2002, and 2005, respectively.

He is currently a Professor with the FederalUniversity of Sao Joao del-Rei, Sao Joao del-Rei, Brazil. His research interests include power-quality-related issues, high-power factor rectifiers,and soft-switching techniques applied to static powerconverters.

Grover Victor Torrico-Bascope (M’04) receivedthe B.Sc. degree in electrical engineering from SanSimon University, Cochabamba, Bolivia, in 1993,and the M.Sc. and doctorate degrees in electricalengineering from the Federal University of SantaCatarina, Florianopolis, Brazil, in 1996 and 2001,respectively.

From 2001 to 2002, he was an Advisor with Emer-son Energy System, Brazil, where he developed ac/dcthree-phase rectifiers. In 2003, he was a Senior De-sign Engineer with Emerson Network Power Com-

pany, Ltd., Stockholm, Sweden. From 2004 to 2009, he was a Senior Engineerin Power Electronics Designs with the R&D Group, Eltek Valere AB, Sweden,where he developed ac/dc three-phase and single-phase highly efficient recti-fiers and dc/dc multioutput supplies to the telecom industry. Since July 2009,he has been a Senior Design Engineer with GTB Power Electronics Researchand Technology AB, Kista, Sweden, where he is currently a Consultant andis offering new high-efficiency (HE) circuit topologies to the power electronicindustry. He has published more than 20 technical papers and is the holder oftwo patents. His main research areas are in industrial power electronics andcreating new platforms with HE topologies for high-power and green energyapplications.

Falcondes Jose Mendes de Seixas was born in Jales,SP, Brazil in 1965. He received the B.S. degree inelectrical engineering from the Engineering Schoolof Lins, Lins, Brazil, in 1988 and the M.S. and Ph.D.degrees in electrical engineering from the FederalUniversity of Santa Catarina, Florianpolis, Brazil, in1993 and 2001, respectively.

He is currently an Assistant Professor at the De-partment of Electrical Engineering, Universidade Es-tadual Paulista (UNESP), Ilha Solteira, Brazil. Hisresearch interests include power factor correction,

switching mode power supplies, and multipulse transformer applications.