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A Comprehensive Look A Comprehensive Look at at VLSI Fault Diagnosis VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002
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A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

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Page 1: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

A Comprehensive Look at A Comprehensive Look at VLSI Fault DiagnosisVLSI Fault Diagnosis

David B. LavoDissertation Defense

July 19, 2002

Page 2: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

OutlineOutline

• Background & Philosophy

• Three-Stage Fault Diagnosis

• IDDQ Fault Diagnosis

• Small Fault Dictionaries

• Conclusions and Future Work

Page 3: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Format of This TalkFormat of This Talk

• Prior art is introduced throughout

• Innovations are presented as:– Problem to be solved– My approach

• Brief exposition:– Background and prior art– Particulars and importance of innovations

Page 4: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Format ExampleFormat Example

• Problem: This presentation is too long– 6 conference papers, 5 years of work,

73 slides

• Solution: TalkKompress® technology– Rapid delivery– High gloss finish– Drill-down capability

Page 5: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

VLSI Test (In One Slide)VLSI Test (In One Slide)

1

0

1

1

0

1

0

0

0

1

1

1

1

1

0

0

Fail!

Fail!Test

Pattern(Vector)

TestResponse

Fault Signature:1: 5, 6

Test No.FailingOutputs

IDDQ Test:Pass: Low CurrentFail: High Current

Page 6: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

VLSI Fault Diagnosis VLSI Fault Diagnosis (in One Slide)(in One Slide)

Tests ObservedBehavior

Defective Circuit

Diagnosis Diagnosis AlgorithmPhysical Analysis

Location or

Fault

Page 7: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Traditional Fault DiagnosisTraditional Fault Diagnosis

Tests

Defective Circuit

Fault Simulator

010001010100010101010 …

Behavior Signature

010100110000101010100 …

101000100001011101100 …

010100010100011101100 …

000111000101010011110 …

Candidate Signatures

Diagnosis Algorithm

Comparison & Conclusion

Page 8: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Fault ModelsFault Models

• A fault model is an abstraction of a type of defect behavior

• A fault instance is the application of a model to a circuit wire, node, gate, etc.

• Used to create and evaluate test sets

• For diagnosis, they can be used to simulate and predict faulty behaviors

Page 9: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Stuck-at Fault ModelStuck-at Fault Model

• The most-used fault model (by far)

• Simple to simulate

• Effective for testing, fault grading, and diagnosis of some defects

• Many fault scenarios are not well represented by the stuck-at model

0/10/1

1

Node A stuck-at 1:

(Fault-free/faulty logic values)

A

B

Page 10: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

• Shorts are a common defect type in CMOS

• Different bridging fault models have varying accuracy and precision, from simplistic to very sophisticated

Bridging Fault ModelBridging Fault Model

0

1

1

1

0

1/0

X

Y

Nodes X and Y bridged:

Node X forces Y to a value of 0

Page 11: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Statement of PhilosophyStatement of Philosophy

• Defect model isn’t known beforehand: A single-model algorithm will not be robust

• Fault models are necessary: Fault models provide precision and guidance for physical failure analysis

• Fault models are unreliable: Expecting defect behavior to correspond exactly with model assumptions and predictions can cause diagnoses to fail

• Diagnosis is messy: Any data item can be corrupt; don’t make an irreversible decision based on a single piece of information

• Be practical: Be wary of expensive solutions, and use all available data

Page 12: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

OutlineOutline

• Background & Philosophy

• Three-Stage Fault Diagnosis

• IDDQ Fault Diagnosis

• Small Fault Dictionaries

• Conclusions and Future Work

Page 13: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Three-Stage Fault DiagnosisThree-Stage Fault Diagnosis

• Three stages of increasing precision

• First: Model-independent diagnosis for complex and multiple defects

• Second: Determine likely fault models and likely physical areas for analysis

• Third: Diagnosis using multiple specific fault models

Page 14: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

First Stage Fault DiagnosisFirst Stage Fault Diagnosis

• Problem: Size of the diagnosis problem– Entire circuit is implicated– Any fault model can be considered

• Solution: iSTAT algorithm– Model-independent– Computationally simple– Implicates a subset of the circuit nodes– Per-Test approach

Page 15: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Per-Test Fault DiagnosisPer-Test Fault Diagnosis

• Prior art:– Waicukauski & Lindbloom (D&T‘89)– POIROT algorithm (Intel, ITC’00)– SLAT algorithm (IBM, ITC’01)

• Basic Idea:– A complex defect will, on some tests, behave

exactly like a stuck-at fault– The stuck-at faults so implicated tell you

something about the defect

Page 16: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Per-Test Fault DiagnosisPer-Test Fault Diagnosis

?

Test 1: {1, 2, 3}

Test 2: {3, 4, 5}

Test 3: {1, 2, 5}

1: 1,2,32: 3,4,53: 1,2,5

1: 1,2,3 Fault A

Final diagnosis: {A, B}

Fault X(Best single match)

2: 3,4,5 Fault B3: 1,2,5 no match

Traditional Diagnosis:

Per-Test Diagnosis: * Tests 1 & 2 are simple failing tests implicate faults

* Test 3 is a complex failing test

no implication

*

**

Page 17: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Improving Per-Test DiagnosisImproving Per-Test Diagnosis

• The problem with the per-test approach is the number of implicated faults

• Also, most per-test algorithms can’t handle complex failures or passing tests

• The iSTAT algorithm solves these problems by treating each test result as evidence

• Matching faults share per-test evidence

Page 18: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Dempster-ShafferDempster-Shaffer

AD

AB

A

BD

B

BA B C Ø

D B Ø

D

B

Ø

CD

BC B

D

C Ø

A B C Ø

AD

B

B B

{B} is a minimal covering

{A,D} is an alternative covering

0 1

T1:

0 1

T2:

Acceptable coverings (complete & non-redundant):

{B}, {A,D}, {C,D}

Page 19: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Creating & Scoring MultipletsCreating & Scoring Multiplets

• A multiplet is a set of faults that cover all failing tests

• Multiplets and scores are created by DS method– Non-complete combinations are dropped– Redundant combinations are dropped

Page 20: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Matching Passing TestsMatching Passing Tests

• Lack of failures can indicate:– Unsensitized faults– Interference of propagation of fault effects

• Considering passing tests is important for resolution:

Asa1 Csa1

• Passing test evidence is split among correct predictors, but with high p(Ø)

Output fault failures swamp input faults!

Page 21: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Matching Complex FailuresMatching Complex Failures• Complex failures can indicate:

– Interference of fault-effect propagation

– Multiple faults

• iSTAT uses a conservative approach:

• iSTAT splits evidence among matching multiplets, uses somewhat higher p(Ø)

Match

Non-Match

Page 22: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Experimental ResultsExperimental Results

• Simulated defects in industrial design

• Different defect types:– Single and multiple stuck-ats, bridges– Multiple faults on one net, gate, and path

• Compared to SLAT algorithm:– Ave. SLAT diagnosis size: 10.75 multiplets– Ave. iSTAT diagnosis size: 2.75 multiplets

Page 23: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Experimental ResultsExperimental Results

• Industrial circuit from TI

• 14 bridge defects introduced by focused ion beam (FIB)

• Comparison to leading industrial diagnosis tool (Fastscan - W&L):– Fastscan: 2 full success, 9 partial, 3 failures– iSTAT: 5 full success, 9 partial, 0 failures

Page 24: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Second Stage Fault DiagnosisSecond Stage Fault Diagnosis

• Problem: Multiplets are hard to use– A collection of seemingly-unrelated faults– Don’t relate to any common defect

mechanisms

• Solution: Implicate plausible fault models and localize fault sets– Suggest possible defect mechanisms– Implicate physical or logical circuit areas

Page 25: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

The Value of Fault ModelsThe Value of Fault Models

• Relate to known defect mechanisms:– Shorts to power or ground– Signal-to-signal shorts– Opens or breaks

• Increases diagnostic precision– Physical FA knows what to look for– Can compare simulation to behavior

Page 26: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Plausibility MetricsPlausibility Metrics

• Search for correlations between faults• What do the faults in a multiplet have in

common?– Common gate, wire, path

• What is the upper probability limit that a multiplet represents a common fault?– Bridges, transition faults, gate faults

• First-order estimates: how reasonable to pursue fault model(s)

Page 27: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Proximity MetricsProximity Metrics

• How close/related are the faults in a multiplet?– Physical distance between implicated nodes– Bounding box of implicated wires– Logical distance between node faults

• May be most the important metric, since physical FA is so limited

Page 28: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Experimental ResultsExperimental Results

• Same 20 simulated defects from before

• 6 possible multiplet classifications:– Single stuck-at, 2-line bridging fault– Common node, net, gate, and path

• 10 are perfect match to defect

• 5 match stuck-at: test dependent

• 5 are multiple defects & low correlations

Page 29: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Third Stage Fault DiagnosisThird Stage Fault Diagnosis

• Problem: Need multiple fault models– Prior art algorithms all target 1 fault model– What happens if defect doesn’t match?

• Solution: Mixed-model fault diagnosis– Apply an arbitrary number of fault models– Pick the best candidate, regardless of model– More models means more precision and

more robustness

Page 30: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Probabilistic ScoringProbabilistic Scoring

• The scoring method used by most algorithms is unique to the fault model

• If multiple fault model diagnosis is to work, the scoring must be comparable across fault models

• The most intuitive method is probabilistic: What is the most likely candidate, regardless of model?

Page 31: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Standard Scoring ExampleStandard Scoring Example

Bridge Candidates:1. Bridge 12 @ 572. Bridge 21 @ 2053. Bridge 12 @ 114

Stuck-at Candidates:1. Node 12 sa 02. Node 205 sa 13. Node 19 sa 1

100.98.9096.90.8286.78.72

92n 70m81n 60m71n 72m

Page 32: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Probabilistic Scoring ExampleProbabilistic Scoring Example

Fault Candidates:1. Bridge 12 @ 572. Node 12 sa 02. Bridge 21 @ 2053. Bridge 12 @ 1144. Node 205 sa 15. Node 19 sa 1

0.3780.3010.2270.0820.0110.001

Page 33: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Probabilistic Fault DiagnosisProbabilistic Fault Diagnosis

• Precedents:– Sheppard & Simpson (VTS’96):

Comprehensive system-level diagnosis– Henderson & Soden (ITC’97): Probabilistic

physical failure analysis– Thibeault (VTS’97): Max. likelihood estimation

for IDDQ diagnosis

• Probability becomes the common component for diagnosis and FA

Page 34: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Bayes Decision TheoryBayes Decision Theory

• Rate candidates by max p(Ci | B):

– Ci: Candidate i fault signature (suspect description or explanation)

– B: Behavior fault signature (evidence or phenomenon)

• Bayes Rule:

iii

iii

pp

ppp

)|()(

)|()()|(

CBC

CBCBC

Page 35: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Conditional ProbabilityConditional Probability

• Assuming that all per-vector (pass/fail) predictions are independent:

p(B|Ci) = p(bk|ck)

• What is the probability that an individual prediction is correct?

• These rates of prediction error must be supplied for each fault model

Page 36: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Diagnosis is Inherently Diagnosis is Inherently Probabilistic!Probabilistic!

• Prediction error rates are required but unknown: not enough statistics

• But, diagnosis systems specify error rates all the time, only implicitly:– How much error is ok?– How important is one type of error vs.

another?

• Turn judgements into explicit parameters!

Page 37: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Three-Model Diagnosis Three-Model Diagnosis SystemSystem

• Use stuck-at candidates to diagnose shorts to VDD/GND, or “charged” opens

• Use inexpensive bridging fault candidates for signal-line shorts

• Use node faults for transition defects and dominance bridges

• Probabilistic scoring system differentiates and ranks all candidates

Page 38: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Industrial ExperimentIndustrial Experiment

• Hewlett-Packard ASIC

• Defects inserted by Focused Ion Beam: 12 total shorts to power or ground, 9 signal shorts, 4 open (break) defects

• Only a pass/fail stuck-at dictionary used

• No IFA or realistic bridging faultlist was available

Page 39: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

ResultsResults

• Stuck-at results: 9 successes, 1 partial (bridge ranked highest), 2 ambiguous (>100 equiv. candidates)

• Bridging results: 6 successes, 3 partial

• Open results: 3 successes (stuck-at candidates), 1 failure (top candidates were stuck-at of unknown relation to open site)

Page 40: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Experimental DetailExperimental Detail

FIB short

Strong inverter

Weak inverter

Top candidate is stuck-at fault on this node.

Page 41: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

OutlineOutline

• Background & Philosophy

• Three-Stage Fault Diagnosis

• IDDQ Fault Diagnosis

• Small Fault Dictionaries

• Conclusions and Future Work

Page 42: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

IIDDQDDQ Testing Testing

• IDDQ testing measures quiescent current to infer the presence of defects

• IDDQ fault diagnosis has the advantage of not relying on propagation through logic

• But, how much quiescent current indicates a defect?

• Modern chips are inherently noisy

Page 43: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

IIDDQDDQ Diagnosis Diagnosis

• Problem: How to conduct diagnosis when failure is ambiguous?

• Solution: Probabilistic IDDQ diagnosis

• Prior Art:– Aitken, Chakravarty & Liu - require definite

pass/fail measures– SEMATECH experiment - repeatedly

adjust pass/fail thresholds

Page 44: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Threshold SettingThreshold Setting

0

20

40

60

80

100

120

140

160

180

0 50 100 150 200

Page 45: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Threshold Setting (cont.)Threshold Setting (cont.)

• There are many possible valid thresholds for diagnosis

• SEMATECH method: repeatedly adjust threshold until an exact match is found in the fault dictionary

Page 46: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Threshold Setting, SEMATECHThreshold Setting, SEMATECH

0

20

40

60

80

100

120

140

160

180

0 50 100 150 200

Exact match

No match

No match

No match

No match

Page 47: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Improving the MethodsImproving the Methods

• First, use probabilistic diagnosis to eliminate the need for exact matches

• Second, automate the setting of pass-fail thresholds

Page 48: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

+ p(passing IDDQ|obs. IDDQ)p(passing IDDQ|pred. fail) = p(failing IDDQ|obs. IDDQ)p(failing IDDQ|pred. fail)

• If low current is predicted:

• If a high current state is predicted for a vector:

= p(passing IDDQ|obs. IDDQ)

Conditional Probability (cont.) Conditional Probability (cont.)

p(b|c) = p(observed IDDQ | predicted fail) 1

0= p(failing IDDQ|obs. IDDQ)

= p(failing IDDQ|obs. IDDQ)p(failing IDDQ|pred. fail) + p(passing IDDQ|obs. IDDQ)p(passing IDDQ|pred. fail)

1

0

Page 49: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Threshold ScenariosThreshold Scenarios

• Different diagnostic situations mandate different ways of setting thresholds

• A predetermined threshold may be available

• More or less information may be available about expected IDDQ values

Page 50: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Scenario 1: Perfect KnowledgeScenario 1: Perfect Knowledge

• If a threshold has been established for test, it may be used for diagnosis

• The simplest approach is to assume this threshold cleanly divides passing from failing IDDQ values

• This approach lacks robustness

Page 51: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Perfect Knowledge ClusteringPerfect Knowledge Clustering

0

20

40

60

80

100

120

140

160

180

0 50 100 150 200

p(de

fect

)1 0

Page 52: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

0

20

40

60

80

100

120

140

160

180

0 50 100 150 200

p(de

fect

)1 0

Perfect Knowledge, ImprovedPerfect Knowledge, Improved

Page 53: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Scenario #2: Statistical Scenario #2: Statistical KnowledgeKnowledge

• The IDDQ of the part may be statistically characterized before testing & diagnosis

• A technique by Maxwell, et al. (ITC99) uses the ratio of max to min IDDQ to establish a 3 acceptance limit

• Expected (good circuit) distribution can be used as the probability of no defect

Page 54: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

p(no

def

ect)

0

20

40

60

80

100

120

140

160

180

0 50 100 150 200

Statistical KnowledgeStatistical Knowledge

Page 55: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Scenario #3: Zero KnowledgeScenario #3: Zero Knowledge

• Use Gattiker-Maly current signatures to identify IDDQ signature clusters

• Each cluster associated with a defect-induced current path

• Intra-cluster variations normally distributed• Lowest cluster defines

p(obs. value | pass), other clusters define p(obs. value | fail)

Page 56: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Zero Knowledge ClusteringZero Knowledge Clustering

0

50

100

150

200

0 20 40 60 80 100

Vector Order

IDD

Q (

uA

)

Page 57: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Experimental ResultsExperimental Results

• We re-ran the SEMATECH experiments on 16 parts with thorough FA

• In 15 of 16 cases our method was able to automatically assign thresholds for successful diagnoses

• In the remaining case, the SEMATECH diagnosis was a failure; our diagnosis resulted in a partial success

Page 58: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

OutlineOutline

• Background & Philosophy

• Three-Stage Fault Diagnosis

• IDDQ Fault Diagnosis

• Small Fault Dictionaries

• Conclusions and Future Work

Page 59: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Small Fault DictionariesSmall Fault Dictionaries

• Problem: Full fault dictionaries are prohibitively large– Good diagnostic resolution– Pass-fail format is smaller, but less

resolution

• Solution: Output-compaction and clustered dictionaries

Page 60: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

The Full-Response DictionaryThe Full-Response Dictionary• For each fault ( f ), store the response

to each test vector ( v )

• One bit per vector, pass ( 0 ) or fail ( 1 )

• For each vector, store the expected output response ( o )

• Total storage requirement: f v o bits

Page 61: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

The Pass-Fail DictionaryThe Pass-Fail Dictionary

• For each fault, store only the test vector responses

• One bit per vector, pass ( 0 ) or fail ( 1 )

• Total storage requirement: f v bits

• Much smaller than full-response, and often practical for even very large circuits

Page 62: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Pass-Fail vs. Full-ResponsePass-Fail vs. Full-ResponseCircuit Full-Resp.

FaultsRanked #1

Full-Resp.Bits

Pass-FailFaults

Ranked #1

Pass-FailBits

C432 2.29 191,142 2.80 27,306C499 1.17 901,120 1.17 28,160C880 1.61 1,512,864 1.66 56,032C1355 1.67 2,936,192 1.71 91,756

C1908 1.82 2,966,700 1.99 118,668

C2670 2.24 18,141,184 3.04 283,456

C3540 2.03 8,963,724 2.10 407,442

C5315 1.89 73,878,966 2.07 600,642

C6288 1.33 7,207,680 1.40 225,240

C7552 1.63 131,224,800 2.12 1,226,400

Ind-A 2.74 232.84 Gb 5.49 15.52 Mb

Ind-B 2.33 929.42 Gb 2.91 46.37 Mb

Ind-C 2.51 297.86 Gb 51.0 21.27 Mb

Ind-D 1.91 9.08 Gb 2.86 333,822

Page 63: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Dictionary EncodingsDictionary Encodings• To reduce dictionary size, researchers

have looked at:– What data is included– How the data is organized– How the data is stored or encoded

• Pass-fail, drop-on-k address the first issue

• Boppana Hartanto Fuchs (VTS96) addressed the second

• Data compression addresses the third

Page 64: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

What About Data What About Data Compression?Compression?

• However the data is chosen and encoded, it can still be compressed afterward (zip, etc.)

• But, compressed dictionaries must be uncompressed for use!

• We are (mainly) concerned here with what data is included, not how it is encoded

• Can we create “compressed” fault signatures that are usable as-is?

Page 65: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

OC001110001

Output-Compacted SignaturesOutput-Compacted Signatures

V1 V2 V3 V4 V5 V6 V7 V8 V9O1 0 0 0 0 0 0 0 0 0O2 0 0 0 0 0 0 0 0 0O3 1 1 0 0 0 0 0 0 1O4 1 1 0 0 0 0 1 0 1O5 0 0 0 0 0 0 0 0 1O6 0 0 0 0 0 0 0 0 0O7 0 0 0 0 0 0 0 0 0O8 0 0 0 0 0 0 0 0 0O9 0 1 0 0 0 0 0 0 1

PF 1 1 0 0 0 0 1 0 1

OR

OR

Page 66: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Reconstructing a Full SignatureReconstructing a Full SignatureV1 V2 V3 V4 V5 V6 V7 V8 V9 OC

O1 0 0 0 0 0 0 0 0 0 0O2 0 0 0 0 0 0 0 0 0 0O3 1 1 0 0 0 0 0 0 1 1O4 1 1 0 0 0 0 1 0 1 1O5 0 0 0 0 0 0 0 0 1 1O6 0 0 0 0 0 0 0 0 0 0O7 0 0 0 0 0 0 0 0 0 0O8 0 0 0 0 0 0 0 0 0 0O9 0 1 0 0 0 0 0 0 1 1PF 1 1 0 0 0 0 1 0 1

V1 V2 V3 V4 V5 V6 V7 V8 V9 OCO1 0 0 0 0 0 0 0 0 0 0O2 0 0 0 0 0 0 0 0 0 0O3 1 1 0 0 0 0 0 0 1 1O4 1 1 0 0 0 0 1 0 1 1O5 0 0 0 0 0 0 0 0 1 1O6 0 0 0 0 0 0 0 0 0 0O7 0 0 0 0 0 0 0 0 0 0O8 0 0 0 0 0 0 0 0 0 0O9 0 1 0 0 0 0 0 0 1 1PF 1 1 0 0 0 0 1 0 1

V1 V2 V3 V4 V5 V6 V7 V8 V9 OCO1 0 0 0 0 0 0 0 0 0 0O2 0 0 0 0 0 0 0 0 0 0O3 1 1 0 0 0 0 0 0 1 1O4 1 1 0 0 0 0 1 0 1 1O5 0 0 0 0 0 0 0 0 1 1O6 0 0 0 0 0 0 0 0 0 0O7 0 0 0 0 0 0 0 0 0 0O8 0 0 0 0 0 0 0 0 0 0O9 0 1 0 0 0 0 0 0 1 1PF 1 1 0 0 0 0 1 0 1

V1 V2 V3 V4 V5 V6 V7 V8 V9 OCO1 0 0 0 0 0 0 0 0 0 0O2 0 0 0 0 0 0 0 0 0 0O3 1 1 0 0 0 0 0 0 1 1O4 1 1 0 0 0 0 1 0 1 1O5 0 0 0 0 0 0 0 0 1 1O6 0 0 0 0 0 0 0 0 0 0O7 0 0 0 0 0 0 0 0 0 0O8 0 0 0 0 0 0 0 0 0 0O9 0 1 0 0 0 0 0 0 1 1PF 1 1 0 0 0 0 1 0 1

Page 67: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Results with Output SignaturesResults with Output SignaturesCircuit Full-Resp.

FaultsRanked #1

Pass-FailFaults

Ranked #1

Pass-Fail +Output Sig.

FaultsRanked #1

C432 2.29 2.80 2.32C499 1.17 1.17 1.17C880 1.61 1.66 1.61C1355 1.67 1.71 1.69C1908 1.82 1.99 1.82C2670 2.24 3.04 2.24C3540 2.03 2.10 2.03C5315 1.89 2.07 1.89C6288 1.33 1.40 1.34C7552 1.63 2.12 1.63Ind-A 2.74 5.49 2.87Ind-B 2.33 2.91 2.34Ind-C 2.51 51.0 2.51Ind-D 1.91 2.86 1.91

Page 68: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Clustering Output SignaturesClustering Output Signatures• Relations between faults can lead to

identical output signatures, but also nearly identical signatures

• Similar signatures can be collapsed into a single signature if some loss is ok

• Data loss equals precision loss at diagnosis• A probabilistic (inexact) matching algorithm

assures no loss of accuracy

Page 69: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Clustered Output SignaturesClustered Output Signatures

Clustered Output Signature:11001

Output Signature:0010101000000000000010011

Page 70: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Results - Clustered SignaturesResults - Clustered Signatures(1000 bits/output signature)(1000 bits/output signature)

Circuit Outputs Full-Resp.Faults

Ranked #1

Pass-FailFaults

Ranked #1

Pass-Fail+Output Sig.

FaultsRanked #1

Pass-Fail+Output Sig.Clustered

FaultsRanked #1

Ind-A 15,000 2.74 5.49 2.87 2.87

Ind-B 20,042 2.33 2.91 2.34 2.34

Ind-C 14,003 2.51 51.0 2.51 6.21

Ind-D 27,193 1.91 2.86 1.91 2.03

Page 71: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

OutlineOutline

• Background & Philosophy

• Three-Stage Fault Diagnosis

• IDDQ Fault Diagnosis

• Small Fault Dictionaries

• Conclusions and Future Work

Page 72: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

ConclusionsConclusions

• Fault diagnosis is inherently probabilistic– Based on human judgement, not statistics– Data and problem are messy and

unpredictable

• It can be made practical by certain techniques and iteration

• It can be as precise as desired

Page 73: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Future WorkFuture Work

• Address delay-inducing defects– Failures are not static but

temporal & sensitive to various conditions

– Increasingly important

• Expand on physical correlation of faults– Handle very complex defects– Physical diagnosis?

• More experiments on production fails

Page 74: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Analysis of Multiple FaultsAnalysis of Multiple Faults

• A multiplet may represent multiple faults

• Low plausibility scores over all fault classes may imply multiple faults

• Select for high-correlation subsets:– Fault class cardinality (n-choose-2 for

bridges)– High proximity correlation

Page 75: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Output Signature Dictionary SizesOutput Signature Dictionary SizesCircuit Full-Resp.

BitsPass-Fail

BitsPass-Fail +Output Sig.

BitsC432 191,142 27,306 29,637C499 901,120 28,260 42,240C880 1,512,864 56,032 70,720C1355 2,936,192 91,756 117,740C1908 2,966,700 118,668 135,718C2670 18,141,184 283,456 371,520C3540 8,963,724 407,442 441,014C5315 73,878,966 600,642 926,100C6288 7,207,680 225,240 345,368C7552 131,224,800 1,226,400 1,585,920Ind-A 232.84 Gb 15.52 Mb 309.51 MbInd-B 929.42 Gb 46.37 Mb 420.24 MbInd-C 297.86 Gb 21.27 Mb 319.13 MbInd-D 9.08 Gb 333,822 66.11 Mb

Page 76: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Storing Output Signatures OnceStoring Output Signatures Once• “Related” faults often propagate failures to the

same set of outputs:– Faults on the same net– Faults in the same functional block– Faults logically close to outputs

• This results in a lot of redundancy in output signatures

• We can save space by only storing a particular signature once and then indexing

Page 77: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Circuit Full-Resp.Bits

Pass-FailBits

Pass-Fail +Output Sig.

Raw Bits

Pass-Fail +Output Sig.Unique Bits

C432 191,142 27,306 29,637 29,591C499 901,120 28,260 42,240 41,784C880 1,512,864 56,032 70,720 64,191C1355 2,936,192 91,756 117,740 112,696C1908 2,966,700 118,668 135,718 132,756C2670 18,141,184 283,456 371,520 307,456C3540 8,963,724 407,442 441,014 429,074C5315 73,878,966 600,642 926,100 710,496C6288 7,207,680 225,240 345,368 268,242C7552 131,224,800 1,226,400 1,585,920 1,322,702Ind-A 232.84 Gb 15.52 Mb 309.51 Mb 96.06 MbInd-B 929.42 Gb 46.37 Mb 420.24 Mb 159.51 MbInd-C 297.86 Gb 21.27 Mb 319.13 Mb 55.46 MbInd-D 9.08 Gb 333,822 66.11 Mb 17.27 Mb

Only Unique Output SigsOnly Unique Output Sigs

Page 78: A Comprehensive Look at VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002.

Low-Resolution DiagnosisLow-Resolution Diagnosis

• Clustering outputs to an arbitrary number of bits suggests a direction for diagnosis

• Reduce dictionaries to an arbitrarily small size, especially for very large circuits

• The resolution will depend upon data size

• Use small dictionaries for initial gross diagnosis

• Iterate through larger and more detailed dictionaries