1 A 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection Somnath Kundu 1 , Bongjin Kim 1,2 , Chris H. Kim 1 1 Dept. of ECE, University of Minnesota, Minneapolis, MN 2 Rambus Inc., Sunnyvale, CA
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1
A 0.2-to-1.45GHz Subsampling
Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur
Cancellation and In-Situ Timing Mismatch Detection
Somnath Kundu1, Bongjin Kim1,2, Chris H. Kim1
1Dept. of ECE, University of Minnesota, Minneapolis, MN2Rambus Inc., Sunnyvale, CA
2
Outline
• Background: PLL vs. MDLL
• Reference Spur Cancellation
• In-situ Reference Spur Detection
• 65nm Test Chip Architecture
• Measurement Results
• Conclusion
3
PLL based Clock Generation
• VCO phase noise is filtered by PLL loop
bandwidth
• Maximum PLL bandwidth is roughly fREF/10
4
Multiplying DLL (MDLL) based PLL
• VCO phases are periodically replaced by
reference phases
• Main advantage: Phase noise suppression
above the PLL bandwidth
Ref: S. Ye, et al., JSSC’2000
5
Reference Spur Issue in MDLL
• Mismatch in phase detection and reference
injection path causes reference spur
• Divider delay and phase detector (PD) fixed
offset are significant source of mismatch
PD
Multiplexed
Ring VCO
Divider
REF
OUTDIV
ΔT1
ΔT2
ΔT1: PD offset
ΔT2: Divider delay
REF
OUT
DIV
ΔT=ΔT1+ΔT2
2T
T+ΔT T-ΔT
ΔT
fOUT +fREF-fREF
spurspurOutput
Spectrum
6
Outline
• Background: PLL vs. MDLL
• Reference Spur Cancellation
• In-situ Reference Spur Detection
• 65nm Test Chip Architecture
• Measurement Results
• Conclusion
7
Reference and DCO Phase Realignment
PD
Divider
REF
OUTDIV
DTC
ΔT
REF'
• Additional reference delay in phase detection
path cancels spur
• Challenge: Delay should be adjusted and
tracked precisely
8
Reference and DCO Phase Realignment
• Phase detector for reference and DCO phase
realignment should have no inherent phase
offset
9
Zero-offset Aperture Phase Detector
• Latch based PD has ideally
zero phase offset
10
Outline
• Background: PLL vs. MDLL
• Reference Spur Cancellation
• In-situ Reference Spur Detection
• 65nm Test Chip Architecture
• Measurement Results
• Conclusion
11
Drawback in Off-chip Measurement
• Requires high frequency probes or packages,
off-chip drivers and connectors
• Each of these components introduces
inaccuracy in the measurement
12
Error Rate Calculation
D Q
CK
Prog. delay
(Tp)
CKOUT
Error Rate =Avg(TOUT)
TCK
• Error pulse generated when programmable
delay is larger than clock period
TCK1
TpTCK1
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Error Rate Calculation
• Skew between two error rate plot is the time
period difference
TCK1
TpTCK1
TpTCK2
TCK2
ΔT
ΔT
D Q
CK
Prog. delay
(Tp)
CKOUT
Error Rate =Avg(TOUT)
TCK
14
Timing Mismatch Detection from Error Rate Calculation
• S0 selects 1st clk period, S1 selects 2nd, and so on
• Error rate is calculated for each selection
15
Timing Mismatch Detection from Error Rate Calculation