9/16/04 UCB EECS150 D. Culler Fa0 4 1 EECS 150 - Components and Design Techniques for Digital Systems Lec 06 – Minimizing Boolean Logic 9/16-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler http://www-inst.eecs.berkeley.edu/~cs150
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9/16/04UCB EECS150 D. Culler Fa04 1 EECS 150 - Components and Design Techniques for Digital Systems Lec 06 – Minimizing Boolean Logic 9/16-04 David Culler.
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9/16/04 UCB EECS150 D. Culler Fa04 1
EECS 150 - Components and Design Techniques for Digital Systems
Lec 06 – Minimizing Boolean Logic9/16-04
David CullerElectrical Engineering and Computer Sciences
Mapping from SOP to POS (or POS to SOP): Derive truth table then proceed.
One sum (or) term for each 0 in f:
f = (a+b+c)(a+b+c’)(a+b’+c)
f’ = (a+b’+c’)(a’+b+c)(a’+b+c’)
(a’+b’+c)(a+b+c’)
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A B C D W X Y Z0 0 0 0 0 0 0 10 0 0 1 0 0 1 00 0 1 0 0 0 1 10 0 1 1 0 1 0 00 1 0 0 0 1 0 10 1 0 1 0 1 1 00 1 1 0 0 1 1 10 1 1 1 1 0 0 01 0 0 0 1 0 0 11 0 0 1 0 0 0 01 0 1 0 X X X X1 0 1 1 X X X X1 1 0 0 X X X X1 1 0 1 X X X X1 1 1 0 X X X X1 1 1 1 X X X X
off-set of W
these inputs patterns should never be encountered in practice – "don't care" about associated output values, can be exploitedin minimization
Incompletely specified functions
• Example: binary coded decimal increment by 1– BCD digits encode decimal digits 0 – 9 in bit patterns 0000 – 1001
don't care (DC) set of W
on-set of W
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Outline
• Review
• De Morgan’s to transform SofP into simple 2-level forms
• Uniting Law to reduce SofP
• N-cube perspective
• Announcements
• Karnaugh Maps
• Examples
• Reduction Algorithm
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Putting DeMorgan’s to work
DeMorgan’s Law:
(a + b)’ = a’ b’ (a b)’ = a’ + b’
a + b = (a’ b’)’ (a b) = (a’ + b’)’
push bubbles or introduce in pairs or remove pairs.
= =
==
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Transformation to Simple Gates
Sum of Products Involution: x = (x’)’
=
De Morgans
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Implementations of Two-level Logic
• Sum-of-products– AND gates to form product terms
(minterms)
– OR gate to form sum
• Product-of-sums– OR gates to form sum terms
(maxterms)
– AND gates to form product
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Two-level Logic using NAND Gates
• Replace minterm AND gates with NAND gates
• Place compensating inversion at inputs of OR gate
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Two-level Logic using NAND Gates (cont’d)
• OR gate with inverted inputs is a NAND gate– de Morgan's: A' + B' = (A • B)'
• Two-level NAND-NAND network– Inverted inputs are not counted
– In a typical circuit, inversion is done once and signal distributed
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Two-level Logic using NOR Gates
• Replace maxterm OR gates with NOR gates
• Place compensating inversion at inputs of AND gate
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Two-level Logic using NOR Gates (cont’d)• AND gate with inverted inputs is a NOR gate
– de Morgan's: A' • B' = (A + B)'
• Two-level NOR-NOR network– Inverted inputs are not counted
– In a typical circuit, inversion is done once and signal distributed
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A B F
0 0 1
0 1 0
1 0 1
1 1 0
B has the same value in both on-set rows– B remains
A has a different value in the two rows– A is eliminated
F = A'B'+AB' = (A'+A)B' = B'
The Uniting Theorem
• Key tool to simplification: A (B' + B) = A
• Essence of simplification of two-level logic– Find two element subsets of the ON-set where only one
variable changes its value – this single varying variable can be eliminated and a single product term used to represent both elements
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1-cubeX
0 1
Boolean cubes
• Visual technique for identifying when the uniting theorem can be applied
• n input variables = n-dimensional "cube“
• Neighbors “address” differs by one bit flip
2-cube
X
Y
11
00
01
10
3-cube
X
Y Z
000
111
1014-cube
W
X
YZ
0000
1111
1000
0111
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A B F
0 0 1
0 1 0
1 0 1
1 1 0
ON-set = solid nodesOFF-set = empty nodesDC-set = 'd nodes
two faces of size 0 (nodes) combine into a face of size 1(line)
A varies within face, B does notthis face represents the literal B'
Mapping truth tables onto Boolean cubes• Uniting theorem combines two "faces" of a cube