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USN 19CSE33
New Horizon college of Engineering, BangaloreAutonomous college affiliated to vru. Accredited by NAAC with ,A, craaeZ Nge
Makeup Examination Jan 2020
DIGITAL ELECTRONICSDuration: 3 hrs
1a)
b)
c)
2a)
b)
c)
3a)
b)
c)
Answer five full questions choosing one complete question from each module.Module 1
Drar'i' the timing waveform and Explain tC-555 Timer as Mono stable multivibrator.Explain the operation of crystal osciilator with neat circuit Diagram.
OR
Define clamper circuit. Explain Negative clamper with example.
Drar'r' the timing waveform and Explain IC-555 Timer as Astablemultivibrator.Explain the operation of n-channel EMOSFET with neat circuit Diagram.
Module 2
By using concept of QM Technique Sorve fo[orving function
R:f(k,l,m.n):Z m (1,3,4,5,6,9,LL,12,13,14)
Simplify the following function using K-Map method and implement using NoRGate R:f(w,x,y,z):n M ( 1, 3,8, 1 0, 1 Z,1g,L 4,LS) .
Develop a Verilog code for the circuit shown below.
OR4 a) Investigate the 8: I Mux block Diagram for the following function using MEV
Method by considering D as MEV.
Y:f(A, B, C, D):X m (0,2,3,4,5,8,9,L0,1I,L2,1,3,15)
b) Solve using K-Map Technique and implement using NAND gates.
Y:f(P,Q,R,S):X m (2,3,4,5,13,j.5) + Z D (g,9,10,11)
c) Develop a Verilog code for the circuit shown below.
Max. Marks: 100
6Lt
6Ll8L26L2
8
6
L2
L2
colcolcol
colcolcol
8 L3 CO2
7 L3 CO2
5 L2 COs
8 L3 CO2
7 L3 CO2
5 L2 COs
Page 1 of 2
and Characteristicsflip flop truth table:
19CSE33
co3co3
co6
co3co3
co6
co4co5co4
4 co4
6L2 co6co410 L3
10 L3 CO6
10 L3 CO4
10 L3 CO6
10 L3 CO4
A
ttc
C
6a)
b)
c)
7a)
b)
c)
5a)
b)
c)
8 a) Find the excitation tableequation for following
b)
c)
9a)
b)
10a)
b)
Module 3
Construct 4 bit Parallel Adder and Sub tractor circuit.Explain the operation of it. 8
Illustrate using PLA and PAL to implement the fallou ing output function. 7
X= AB+AE andY=AB+BC+AEDevelop a Verilog code for 2:4Decoder circuit. 5
OR
Construct 2 Bit Magnitude comparator circuit by using Truth table and Basic gates. IIllustrate 8:3 Encoder circuit *,ith neat circuit diagram. 7
Develop a Verilog code for 8:1 Mur. 5
Module -l
Give block diagram. truth table and excitation table of JK flip flop. 4
Write a Verilog code to implement Bidirectional 4 bit Shift register. 6
Design a circuit to implement D flip flop as JK flip flop and D flip flop as T flip flop. 10
OR
L3
L3
L2
L3
L3
L2
L1
L2
L3
L1x Y Q n+l0 0 a,0 1 0
I 0 Qn
1 1 1
Write a Verilog code to implement 6 bit su,itched tail counter.
Apply an input 1010 and explain the r.vorking of PIPO. SISO. SIPO with diagram andtruth table for each.
Module 5
Design Synchronous counter to generate the follow'ing sequence using D flip flop:4) t2) 3)2) 9)10)4Also, implement D flip flop using Verilog code.Design a sequence detector to detect ' l0l0l ' using Mealy model and T Flip Flop.
OR
Design a synchronous MOD- 9 down counter using T flip flops. Implement MOD- 9up counter using Verilog code.Design a sequence detector to detect '01 101 ' using Moore model. Use D-flip flopwhile designing.
Page 2 of 2
USN
)
LSi=-s\ /1eCSE34
New Horizon College of Engineering, BangaloreAutonomous College affiliated to VTU, Accredited by NAAC with 'A' Grade& NBA
Makeup Examination Jan 2020
DATA STRUCTURES USING C LANGUAGE
Duration:3 hrs Max. Marks: 100
Answer five full questions choosing one complete question from each module.
Module I1a)
b)
c)
2a)b)
c)
3a)
b)
4a)
b)
Write the algorithm of insertion sort
Compare malloc( ), calloc( ) and realloc( )
Formulate the steps to sort the following array of numbers
6 1, 1 09, I 49,1 I 1.34,2,24,1 1 9, 9, 234, 98, 1 000