8085 Material

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM 1

KUNAL S. THAKERKUNAL S. THAKERKUNAL S. THAKERKUNAL S. THAKER

v BASIC COMPUTER SYSTEM.BASIC COMPUTER SYSTEM.BASIC COMPUTER SYSTEM.BASIC COMPUTER SYSTEM. Ø A BASIC COMPUTER SYSTEM IS SHOWN AS UNDER,

[FIG1.1 A BASIC COMPUTER SYSTEM]

Ø I/O DEVICE :-

ü THEY CONNECT THE SYSTEM WITH REAL WORLD. ü INPUTS ARE AS KEY BOARD, MOUSE ETC. ü OUTPUTS ARE AS LCD, PRINTER ETC.

Ø CPU :- ü HERE IT WORKS AS AN MPU. ü IT HAS MICROPROCESSOR CONTAINING REGISTERS, ALU &

TIMING & CONTROL UNIT. Ø MEMORY :-

ü IT CONSISTS OF MIXTURE OF RAM & ROM. Ø BUS :-

ü IT IS A GROUP OF CONNECTING WIRES. ü IT CARRIES DATA, ADDRESS &/OR SIGNALS.

INPUT DEVICE

OUTPUTDEVICE

I/O PORTS

CPU MEMORY

DATA BUS

ADDRESS BUS

CONTROL BUS

CONTROL BUS



v BASIC STRUCTURE OF MICROPROCESSOR.BASIC STRUCTURE OF MICROPROCESSOR.BASIC STRUCTURE OF MICROPROCESSOR.BASIC STRUCTURE OF MICROPROCESSOR.

Ø IN GENERAL EACH & EVERY MICROPROCESSOR CONTAINS BASIC

BLOCKS ARE SHOWN IN FIGURE AS UNDER

[FIG. 1.2 BASIC STRUCTURE OF MICROPROCESSOR]

Ø REGISTERS :- ü USED TO STORE THE DATA. ü SIZE DEPENDS ON THE WIDTH OF DATA BUS. ü GIVEN UNIQUE NAME THAT CAN BE REFFERED IN

INSTRUCTION. Ø ALU :-

ü IT IS RESPONSIBLE FOR ALL ARITHMATIC & LOGICAL OPERATIONS.

ü ARITHMATIC LIKE ADDITION SUBTRACTION ETC. ü LOGICAL MEANS AND, OR, NOT, NOR, SHIFT ETC.

Ø CONTROL & TIMING UNIT :- ü PROVIDES NECESSARY TIMING & CONTROL SIGNALS TO

PERFORM VARIOUS INTERANAL & EXTERNAL OPERATIONS. ü CONTROLS ALL THE ACTIVITIES OF MICROPROCESSOR.

REGISTERS

ARITHMATIC & LOGICAL UNIT

CONTROL & TIMING UNIT

DATA BUS ADDRESS BUS

CONTROL BUS



Ø DATA BUS :- ü BIDIRECTIONAL. ü RESPONSIBLE FOR DATA X’FER BETWEEN PROCESSOR &

MEMORY OR PERIPHERAL DEVICES. Ø ADDRESS BUS :-

ü UNIDIRACTIONAL. ü CARRY AN ADRRESS OF MEMORY LOCATION OR THE PORT

NO. OF I/O DEVICES. Ø CONTROL BUS :-

ü CONSISTS OF VARIOUS SIGNAL LINES. ü LINE CARRIES SYNCHRONIZATION SIGNALS FOR

APPROPRIATE TIMING. ü LINE CARRIES CONTROL SIGNALS TO HANDLE ALL THE

OPERATIONS PERFACTLY.

v MEMORY ORGANIZATION.MEMORY ORGANIZATION.MEMORY ORGANIZATION.MEMORY ORGANIZATION.

Ø IT PROVIDES NECESSARY STOREGE FOR PROGRAM & DATA. Ø IT CAN BE DIVIDED INTO TWO CATEGORIES :-

MEMORY

Ø PRIMARY MEMORY :- ü RAM & ROM FORM THE PRIMARY MEMORY.

Ø SECONDARY MEMORY :- ü HARD DISK, FLOPPY DISK FORM THE SECONDARY MEMORY.

PRIMARY SECONDARY



Ø PRIMARY MEMORY :- ü RAM :-

Random Access Memory. IT CAN BE READ &/OR WRITE BOTH.

ü ROM :- Read Only Memory. IT CAN BE ONLY READ.

RAM ROM RANDOM ACCESS MEMORY READ ONLY MEMORY

CAN BE READ &/OR WRITE. CAN BE ONLY READ.

VOLATILE :- IF POWER IS SWITCHED OFF THE CONTENT OF RAM IS LOST.

NON VALATILE :- CONTENT OF ROM CAN BE RETAINED IF POWER IS SWITCHED OFF.

CAN BE USED AS A TEMPORARY STORAGE.

USED AS A PERMANENT STORAGE.

[FIG. 1.3 ORGANIZATION OF MEMORY]

0 1 2 3 4 5 6 7

0 1 2 3 4 5 6 7

NO. OF HOUSE PER STREET = M=8

NO. OF STREET IN A SOCIETY

N =7

M -1

1/B 2/C 3/D 4/E

5/F 6/G

0/A

N - 1



Ø A TYPICAL ORGANIZATION OF MEMORY MAY BE VIEWED AS A HOUSING SOCIETY HAVING 7 STREETS (N-1=6, 0TO 6) & 8 HOUSES (M-1=7, 0 TO 7) IN EACH STREET.

Ø EACH HOUSE HAS A PARTICULAR ADDRESS.THERE ARE SO MANY WAYS TO BUILT UP THE ADDRESS.

Ø FOR EXAMPLE :

STREET NO HOUSE NO. FINAL ADDRESS OF HOUSE

1 1 11

1 2 12

1 = 10 1 = 10 1010

3 = 30 7 = 70 3070

A 001 A001

F 007 F007

Ø HOUSE NO. 1 IN 1ST STREET CAN BE ADDRESSED IN TWO DIGITS AS 11 BUT THE SAME HOUSE CAN BE ADDRESSED IN 4 DIGITS AS 1010; SAME AS 3RD STREET CAN BE SHOWN AS 30 & HOUSE NO. 7 CAN BE AS 70 SO FINAL ADDRESS IS 3070.

Ø THE ADDRESS PATERN DEPENDS ON THE BUILDER WHETHER HE WANTS TO KEEP 2 DIGIT OR 4 DIGIT IN A SINGLE ADDRESS.

Ø 11 & 1010 SHOWS THE SAME HOUSE ONLY DIFFERENCE IS OF NO. OF DIGIT.



v ADADADADDRESS RANGE.DRESS RANGE.DRESS RANGE.DRESS RANGE. Ø RANGE MEANS UPPER BOUNDARY & LOWER BOUNDARY. Ø LARGEST NUMBER MAKES THE UPPER BOUNDARY. Ø SMALLEST NUMBER MAKES THE LOWER BOUNDARY. Ø LARGEST & SMALLEST NO. DEPEND ON THE NUMBER SYSTEM.

SR NUMBER SYSTEM BASE SMALLEST NO. LARGEST NO.

1 BINARY 2 0 1

2 OCTAL 8 0 7

3 DECIMAL 10 0 9

4 HEXADECIMAL 16 0 F(15)

Ø FOR A SINGLE DIGIT, RANGE IN DEC. NUM. SYS. = 0 TO 9. Ø FOR TWO DIGITS, RANGE IN DEC. NUM. SYS. = 00 TO 99. Ø FOR TWO DIGITS, RANGE IN OCT. NUM. SYS. = 00 TO 77. Ø FOR 4 DIGITS, RANGE IN BIN. NUM. SYS. = 0000 TO 1111. (0 TO F) Ø FOR 16 DIGITS, RANGE IN BIN. NUM. SYS.

Ø MICROPROCESSOR CONTAIN 16 BITS ADDRESS LINE. MEANS THESE 16 DIGITS MAKES THE ADDRESS.

Ø FOR A BINARY NUM. SYSTEM IF WE WANT TO FIND THE ADDRESS RANGE THEN PUT SMALLEST NO. OF BIN. NUM. SYS. (0) FOR LOWER RANGE & LARGEST NO. (1) FOR UPPER RANGE AT 16 DIGITS. WHICH IS SHOWN ABOVE.

8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1

SMALLEST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 HEX

LARGEST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF HEX



v MMMMEMORY READEMORY READEMORY READEMORY READ/WRITE/WRITE/WRITE/WRITE OPERATION.OPERATION.OPERATION.OPERATION. Ø WE WILL UNDERSTAND THIS TOPIC BY TAKING AN EXAMPLE OF

MONEY TRANSFER……………..

[FIG. 1.4 SCHEMATIC OF MONEY X’FER TO UNDERSTAND MEMORY READ]

MAGAN LIMBDI

CHHAGAN RAJKOT

CHANDU RAJKOT

MAGAN IS A CHNDU’S FRIEND

CHHAGAN IS A MAGAN’S FRIEND

CHANDU DON’T KNOW WHO IS CHHAGAN

KNOW

KNOW

DON’TKNOW

1. MAGAN GIVES ADDRESS OF CHHAGAN TO CHANDU.

2. MAGAN CALLS CHHAGAN THAT CHANDU IS COMING FOR MONEY.

3. CHHAGAN CHECK THE POCKET & PLACE THE MONEY IN A COVER.

4. THAT COVER IS THAEN REACHED TO MAGAN.



Ø Ø Ø Ø Ø Ø Ø Ø Ø Ø Ø Ø Ø Ø Ø

[FIG. 1.5 MEMORY READ OPERATION]

Ø HOW MEMORY READ OPERATION IS DONE BY PROCESSOR CAN BE UNDERSTAND AS FOLLOWING……….. ü HERE 55H DATA IS STORED IN MEMORY AT 2010H LOCATION. ü MEMORY READ MEANS PROCESSOR READ THE CONTENT OF THAT

LOCATION.i.e. THAT DATA GOES INTO THE PROCESSOR. ü THE OPERATION IS DONE IN 4 STEPS AS FOLLOWING……….

1.) FIRST OF ALL WE HAVE TO KNOW THE PLACE WHERE THE DATA IS

STORED……………………………….. ADDRESS OF LOCATION.

2.) THEN PROCESSOR HAS TO TELL TO MEMORY THAT I WANT TO READ

YOU……………………………………….GENERATE CONTROL SIGNAL.

3.) NOW MEMORY DEVICE CHECK THE ADDRESS & READ THE DATA &

PLACE ON THE BUS………………….. READ ADDRESS & PLACE DATA.

4.)FINALLY PROCESSOR READS THE DATA FROM DATA BUS.

…………………………………………….. READ THE DATA.



[FIG. 1.6 MEMORY READ OPERATION] [FIG. 1.7 MEMORY WRITE OPERATION]

Ø STEPS IN MEMORY READ OPERATION :- ü µP SENDS ADRESS OF MEMORY LOCATION INTO MAR (FROM

WHERE DATA IS TO BE READ). ü AT THE SAME TIME, µP SENDS READ SIGNAL TO ACTIVATE

MEMORY. ü MEMORY READ THE CONTENT WHOSE ADDRESS IN

MAR(MEMORY ADDRESS REGISTER) & PLACE THE DATA INTO MBR.(MEMORY BUFFER REGISTER).

ü µP READS THE CONTENT OF MBR.

Ø STEPS IN MEMORY READ OPERATION :- ü µP SENDS ADRESS OF MEMORY LOCATION INTO MAR

(AT WHER DATA IS TO BE WRITE). ü µP SENDS DATA (WHICH IS TO BE WRITTEN) INTO MBR. ü AT THE SAME TIME, µP SENDS WRITE SIGNAL TO ACTIVATE

MEMORY. ü MEMORY STORES THE DATA FROM MBR AT THE ADDRESS

STORED IN MAR.

M A R

M B R

N * m RAM

ADD.BUS

DATA.BUS

M A R

M B R

N * m RAM

ADD.BUS

DATA.BUS



v MEMORY CHIPS.MEMORY CHIPS.MEMORY CHIPS.MEMORY CHIPS.

[FIG. 1.8 RAM & ROM CHIPS]

Ø RAM IS A READ\WRITE MEMORY SO IT CONTAINS RD & WR

TERMINALS. Ø ROM IS A ONLY READ MEMORY SO IT CONTAINS ONLY RD

TERMINALS. Ø ADDRESS & DATA LINES ARE CONNECTED WITH THE

MICROPROCESSOR. Ø ALL THE 8 DATA LINES ARE CONNECTED WITH THE PROCESSOR. Ø BUT ALL 16 ADDRESS LINES MAY OR MAY NOT BE CONNECTED. NO.

OF ADDRESS LINES DEPEND ON THE GIVEN MEMORY CAPACITY. Ø FINDING ADDRESS RANGE IS CALLED MEMORY MAPPING. Ø CS TERMINAL IS A CHIP SELECTION ACTIVATES THE CHIP.

CS WR RD

A0

A1

. RAM

.

.

AN-1

D0 - D7

CS RD

A0

A1

. ROM

.

.

AN-1

D0 - D7

ADDRESS LINES

ADDRESS LINES

DATA LINES DATA LINES



v MMMMEMORY MAP & ADDRESS LINE.EMORY MAP & ADDRESS LINE.EMORY MAP & ADDRESS LINE.EMORY MAP & ADDRESS LINE. Ø MEMORY MAPPING IS A PROCESS TO FIND THE ADDRESS RANGE

USED BY PROCESSOR TO ACCESS TOTAL AMOUNT OF MEMORY. Ø ADDRESS LINES ARE USED TO ACTIVATE CHIP. Ø THE CRITICAL QUESTIONS ARISE THAT 1.)HOW MANY ADDRESS LINES

ARE NEEDED IN CHIP SELECTION & 2.) HOW MANY LINES ARE USED IN ACCESSING MEMORY FOR A GIVEN MEMORY AMOUNT.

Ø THIS CALCULATION CAN BE EXPLAINED AS FOLLOWING…………..

STEP :- 1 FIND THE ADDRESS LINES FOR ACCESSING MEMORY.

EX. 4K RAM.

ü 4K = 1K X 4

= 210

x 22

= 214

MEANS 14 ADDRESS LINES (A0 TO A13) NEEDED FOR ACCESSING MEMORY.

ADDRESS LINES = TOTAL ADD. LINES TO FOR CHIP SELECTION ADDRESS LINE ACCESS MEMORY

=16 – 14

=2

MEANS 2 ADDRESS LINES(A14 TO A15) ARE NEEDED FOR CHIP SELECTION.

THIS IS AS SHOWN BELOW :

CHIP FOR MEMORY ACCESS

SELECTION

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0



[FIG. 1.9 CHIP SELECTION USING ADDRESS LINES]

Ø WE CAN SEE THAT ADDRESS LINES A0 TO A13 FROM PROCESSOR ARE USED TO ACCESS RAM.

Ø REMAINING LINES A14 & A15 ARE USED FOR CHIP SELECTION.

CS WR RD

A13

A12

A11

A10

A9

A8

A7 RAM

A6

A5

A4

A3

A2

A1

A0 D0 D7

A15

A14

A13

A12

A11

A10

A9

A8

8085 A7

A6

A5

A4

A3

A2

A1

A0

D0 D7

DATA LINES



Ø THERE ARE THREE TOPICS CONNECTED WITH THIS ONE. A. FINDING AMOUNT OF MEMORY FROM GIVEN ADDRESS LINES. B. FINDING ADDRESS LINE FROM GIVEN AMOUNT OF MEMORY. C. FINDING ADDRESS RANGE. STARTING & ENDING ADDRESS.

A.) FINDING AMOUNT OF MEMORY FROM GIVEN ADDRESS LINES.

Ø ADDRESS LINES CAN BE FOUND FROM AMOUNT OF MEMORY USING RELATION GIVEN AS :

2N = AMOUNT OF MEMORY (IN KILO bytes)

WHERE N= NO. OF ADDRESS LINES

EX.1 A PROCESSOR HAS 10 ADDRESS LINES. FIND THE AMOUNT OF MEMORY CAN BE ACCESSED.

Ø W.K.T. 2N

= AMOUNT OF MEMORY (Kb)

Ø 210

= 1024 Kb = 1Kb

EX.2 HOW MUCH MEMORY CAN BE ACCESSED BY A PROCESSOR HAVING 8 DATA LINES & 14 ADDRESS LINES ?

Ø HERE DATA BUS IS GIVEN BUT IT IS NOT IMPORTANT TO FIND AMOUNT OF MEMORY.

Ø W.K.T. 2N = AMOUNT OF MEMORY (Kb)

Ø 214

= 210 X 2

4

= 1 Kb X 16 = 16 Kb NOTE :- REMEMBER THAT THERE ISN’T ANY ROLE OF DATA BUS IN

CALCULATING OF AMOUNT OF MEMORY CAN BE ACCESSED BY

PROCESSOR

NOTE :-IT IS OBVIOUS THAT 210 = 1K & IS ALSO TRUE VICE VERSA.



B.) FINDING ADDRESS LINE FROM GIVEN AMOUNT OF MEMORY.

Ø HERE THE SAME EQUATION CAN BE USED TO FIND OUT ADDRESS LINES USED TO ACCESS MEMORY.

2N = AMOUNT OF MEMORY.

WHERE N = NO. OF ADDRESS LINES.

EX.1 IF 4K RAM IS INTERFACED WITH PROCESSOR THEN FIND THE NO. OF ADDRESS LINES OF PROCESSOR 1.) USED TO ACCESS THE MEMORY 2.) USED FOR CHIP SELECTION.

Ø W.K.T. 2N = AMOUNT OF MEMORY.

2N = 4K

= 1K X 4

= 210

X 22

= 214

Ø SO, N = 14, HENCE 14 ADDRESS LINES ARE REQUIRED TO ACCESS

MEMORY. Ø NOW REMEINING ADDRESS LINES ARE USED FOR CHIP SELECTION.

Ø MEANS [ TOTAL ADD. LINES – ADD. LINES TO ACCESS MEMORY ] Ø TOTAL ADD. LINES, 16 – 14, ADD. LINES TO ACCESS MEMORY. Ø HENCE 2 ADDRESS LINES ARE REQUIRED FOR CHIP SELECTION.

EX.2. HOW MUCH ADDRESS LINES ARE USED TO ACCESS 32K ROM ?

Ø W.K.T. 2N = AMOUNT OF MEMORY.

2N

= 32K = 1K X 32

= 210

X 25

2N

= 215

Ø HENCE N = 15 ADDRESS LINES ARE REQUIRED.



C.) FINDING ADDRESS RANGE FOR A GIVEN MEMORY AMOUNT .

EX.1. FIND ADDRESS RANGE FOR 4K RAM.

STEP 1:- FIND ADD. LINES 1.) DIRECT CONNECTED, 2.) CHIP SELECTION ?

4K = 1K X 4

= 210

X 22

= 212

Ø HENCE 12 ADD. LINES ARE USED TO ACCESS THE MEMORY. (A0 TO A11). Ø IT MEANS 4 ADD. LINES ARE USED FOR CHIP SELECTION. (A12 TO A15).

STEP 2 :- DIVIDE TOTAL ADD. LINES FROM ABOVE CALCULATION.

CHIP SELECTION DIRECT CONNECTED


STEP 3 :- TO FIND THE RANGE WE HAVE TO FIND STARTING & ENDING ADD.

Ø FOR STARTING ADD. GIVE VALUE 0 AT ALL ADD. LINES.

Ø FOR ENDING ADD. GIVE VALUE 1 AT ALL ADD. LINES. Ø CHIP SELECTION LINES REMAIN AS IT IS FOR STARTING & ENDING ADD..

A12 TO A15 REMAINS AT 0



START 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H

END 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FFFH

Ø SO. ADD. RANGE FOR 4K IS FROM 0000H TO 0FFFH.



EX.2. FIND ADDRESS RANGE FOR 32K RAM.


32K = 1K X 32

= 210

X 25

= 215

Ø HENCE 15 ADD. LINES ARE USED TO ACCESS THE MEMORY. (A0 TO A14). Ø IT MEANS 1 ADD. LINES ARE USED FOR CHIP SELECTION. (A15).


CS DIRECT CONNECTED




Ø FOR ENDING ADD. GIVE VALUE 1 AT ALL ADD. LINES.

Ø CHIP SELECTION LINES REMAIN AS IT IS FOR STARTING & ENDING ADD.

ONLY A15 REMAINS AT 0



START 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H

END 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7FFFH

Ø HENCE ADD. RANGE IS FROM 0000H TO 7FFFH.



EX.3. FIND ADDRESS RANGE FOR 1K ROM.


1K = 1K X 1

= 210

X 20

= 210

Ø HENCE 10 ADD. LINES ARE USED TO ACCESS THE MEMORY. (A0 TO A9). Ø IT MEANS 1 ADD. LINES ARE USED FOR CHIP SELECTION. (A11 TOA15).


CS DIRECT CONNECTED




Ø FOR ENDING ADD. GIVE VALUE 1 AT ALL ADD. LINES.

Ø CHIP SELECTION LINES REMAIN AS IT IS FOR STARTING & ENDING ADD.

SO A10 TO A15 REMAINS AT 0



START 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H

END 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 7FFFH

Ø HENCE ADD. RANGE IS FROM 0000H TO 03FFH.



Ø FIRST OF ALL WE WILL UNDERSTAND THAT WHY VALUE OF CHIP SELECTION BITS REMAIN AS IT IS ?

Ø CONSIDER A CASE OF 4K RAM FROM PAGE NO. 15, EX NO. 1.

[FIG. 1.10 LOW LOGIC REACHES AT CS TERMINAL OF MEMORY]


START 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H

END 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FFFH

CS WR RD

A11

A10

A9

A8

A7 RAM

A6

A5

A4

A3

A2

A1

A0 D0 D7

A15

A14

A13

A12

A11

A10

A9

A8

8085 A7

A6

A5

A4

A3

A2

A1

A0

D0 D7

0 0 0 0 1 1 1 1

0

0

0

0 1

0

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1

F

F

F

0



Ø HERE RAM HAS A TERMINAL NAMED CHIP SELECTION AT WHICH THE ADDRESS LINES ARE CONNECTED WHICH ARE NOT USED TO ACCESS MEMORY.

Ø CS IS AN ACTIVE LOW TERMINAL SO IT IS ACTIVITED ONLY IF LOW

LOGIC MEANS 0 IS APPLIED AT THAT TERMINAL. Ø THE MEMORY CHIP CAN BE ACTIVATED BY APPLYING 0 LOGIC AT

ADD. LINES, USED FOR CHIP SELECTION. Ø ADD. LINES FOR CS ARE GIVEN AS AN INPUT AT BUBBLED NAND

GATE & OUTPUT OF GATE IS GIVEN TO CS TERMINAL. Ø HOW LOE LOGIC REACHED AT CS TERMINAL OF MEMORY IS SHOWN

AS UNDER :-

[FIG. 1.11 HOW LOW LOGIC 0 REACHES AT CS TERMINAL]

Ø NOW COMING TO THE MAIN POINT THAT HOW THE START/END ADDRESS CAN BE FOUND FROM THE ANY ONE OF TWO.

Ø IF THE START ADDRESS IS GIVEN THEN END CAN BE FOUND & IF END IS GIVEN THEN START CAN BE FOUND.

Ø THIS CAN BE EXPLAINED AS FOLLOWING :

0 0 0 0

1 1 1 1

1 1 0

TO THE

CS



EX.1. IF END ADDRESS IS 7FFFh THEN FIND START ADDRESS FOR 4K RAM.

STEP 1. WRITE GIVEN HEX ADDRESS IN 16 BIT BINARY FORM.


START

END 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

7 F F F

STEP 2. FIND ADDRESS LINES USED FOR CHIP SELECTION.

MEMORY = 4K

= 1K X 4

= 210

X 22

= 212

Ø MEANS 12 ADDRESS LINES NEEDED TO ACCESS MEMORY & REMAINING 4 ARE NEEDE FOR CHIP SELECTION.

Ø A0 TO A11 TO ACCESS MEMORY & A12 TO A15 FOR CHIP SELECTION.

STEP 3. FING THE REQUIRED ADDRESS.

Ø PUT THE SAME BITS FOR CHIP SELECTION.

Ø IF START ADD. REQUIRED THEN PUT 0 AT REMAINING LINES.

Ø IF END ADD. REQUIRED THEN PUT 1 AT REMAINING LINES.


START 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 7000H

END 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7FFFH

Ø SO STARTING ADDRESS IS 7000H.



EX.2. IF START ADDRESS IS A000h THEN FIND END ADDRESS FOR 8K ROM.



START 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

END

A 0 0 0


MEMORY = 8K

= 1K X 8

= 210

X 23

= 213








START 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 A000H

END 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 BFFFH

Ø SO ENDING ADDRESS IS BFFFH.



EX.3. IF END ADDRESS IS F3FFh THEN FIND START ADDRESS FOR 1K RAM.



START

END 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1

F 3 F F


MEMORY = 1K

= 1K X 1

= 210

X 20

= 210








START 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 F300H

END 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 F3FFH

Ø SO STARTING ADDRESS IS F300H.



EX.4. IF START ADDRESS IS 4000h THEN FIND END ADDRESS FOR 16K ROM.



START 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

END

4 0 0 0


MEMORY = 16K

= 1K X 16

= 210

X 24

= 214








START 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4000H

END 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7FFFH

Ø SO ENDING ADDRESS IS 7FFFH.



v BUS ORGANISATION .BUS ORGANISATION .BUS ORGANISATION .BUS ORGANISATION .

Ø BUS MEANS A BASIC CONNECTING LINE. Ø PROCESSOR HAS TO COMMUNICATE WITH THE MEMORY &

INPUT/OUTPUT DEVICES. Ø THIS CAN BE DONE BY MEANS OF CONNECTING LINES

BETWEEN PROCESSOR & MEMROY/I/O DEVICES. Ø THESE LINES JUST TRANSFER THEBITS FROM PROCESSOR

TO MEMORY/IO DEVICES & VICE VERSA. Ø THE 8085 IS INTERFACED WITH OTHER DEVICES USING THREE

BUSES CALLED DATA, ADDRESS,CONTROL BUS.

[FIG. 1.12 BUS ORGANISATION OF 8085]



Ø DATA BUS :- ü IT IS A BIDIRECTONAL BUS. ü IT IS 8 BIT WIDE. ü RELATED WITH THE DATA X’FER. ü DATA X’FER IS DONE BETWEEN PROCESSOR &

MEMORY/PERIPHERAL DEVICES. Ø ADDRESS BUS :-

ü IT IS A UNIDIRECTIONAL BUS. ü IT IS 16 BIT WIDE. ü IT CARRIES ADDRESS OF MEMORY LOCATION. ü IT CARRIES ADDRESS OF THE I/O DEVICE OR MEMORY

LOCATION TO THE PROCESSOR. Ø CONTROL BUS :-

ü IT CONSISTS OF VARIOUS SIGNALS. ü THEY ARE SYNCHRONIZATION SIGNALS. ü THESE SIGNALS SYNCHRONIZ ALL OF THE OPERATIONS OF

THE PROCESSOR. ü FOR EACH & EVERY OPERATIOS PROCESSOR GENERATES

THE CONTROL SIGNALS.



v PIN OUT DIAGRAM OF 8085.PIN OUT DIAGRAM OF 8085.PIN OUT DIAGRAM OF 8085.PIN OUT DIAGRAM OF 8085. Ø IT IS A 40 – PIN (Dual In line Package) IC.

Vcc & Vss. ü Vcc IS CONNECTED TO THE +5V. ü Vss IS CONNECTED TO THE GROUND.

CLOCK PINS. ü A CRYSTAL IS CONNECTED BETWEEN X1 & X2 PINS TO GENERATE

INTERNAL CLOCK. ü CLKOUT IS USED TO PROVIDE THE SYSTEM CLOCK TO OTHER

DEVICES IN THE SYSTEM. RESET PINS.

ü WHEN RESETIN IS LOW PROCESSOR RESETS ITSELF. ü THROUGH RESETOUT PROCESSOR INFORMS TO OTHER IO DEVICES

THAT PROCESSOR IS BEING RESET. SERIAL COMMUNICATION PINS.

ü SID IS USED FOR SERIAL INPUT DATA. ü SOD IS USED FOR SERIAL OUT DATA.

INTERRUPT PINS. ü TRAP IS NON-MASKABLE & HAVING HIGHEST PRIORITY INTERRUPT. ü RST 7.5, RST 6.5, RST 5.5 ARE RESET & MASKABLE INTERRUPTS.

THEY CAN BE CONTROLLED BY EI, DI, RIM & SIM INSTRUCTIONS. ü INTR IS GENERAL PURPOSE & MASKABLE INTERRUPTS. IT CAN BE

CONTROLLED BY EI & DI INSTRUCTIONS. ü INTA IS ACKNOWLEDGE PIN & IS USED BY PROCESSOR TO REPLAY

THE INTERRUPT REQUEST. ADDRESS PINS.

ü 8085 HAS 16 ADDRESS PINS. A0 TO A15. ü LOWER PINS, A0 TO A7, ARE MULTIPLEXED WITH THE DATA PINS

MAKING AD0 TO AD7. ü HIGHER PINS, A8 TOA15, ARE INDIVIDUALS.

DATA PINS.



ü 8085 HAS 8 DATA PINS. ü THEY ARE MULTIPLEXED WITH THE LOWER ADDRESS PINS MAKING

AD0 TO AD7.

X1 1 40 Vcc

X2 2 39 HOLD

RESET OUT 3 38 HLDA

SOD 4 37 CLK (OUT)

SID 5 36 RESET IN

TRAP 6 35 READY

RST7.5 7 34 IO/M

RST6.5 8 33 S1

RST5.5 9 32 RD

INTR 10 31 WR

INTA 11 30 ALE

AD0 12 29 S0

AD1 13 28 A15

AD2 14 27 A14

AD3 15 26 A13

AD4 16 25 A12

AD5 17 24 A11

AD6 18 23 A10

AD7 19 22 A9

Vss 20 21 A8

[FIG. 1.13 PIN OUT DIAGRAM OF 8085]

DMA CONTROLLER PINS.



ü HOLD IS A REQUEST TO GRANT THE CONTROL OF BUSES OF PROCESSOR.

ü HLDA IS ACKNOWLEDGEMENT USED BY PROCESSOR TO GRANTING REQUEST.

STATUS SIGNALS. ü S0 & S1, THESE ARE USED TOGETHER WITH IO/M TO REPRESENT

THE DIFFERENT MACHINE CYCLE. ü FOR EX. IO/M S0 S1 MACHINE CYCLE

0 1 0 MEMORY WRITE 0 1 1 OPCODE FETCH 0 0 1 MEMORY READ

CONTROL SIGNALS. ü RD & WR ARE USED TO PERFORM READ & WRITE OPERATIONS. ü THEY ARE USED TOGETHER WITH THE IO/M & GENERATE THE MEMR,

MEMW, IOW, IOR SIGNALS. IO/M.

ü INPUT-OUTPUT/MEMORY. ü IT DIFFERENTIATE BETWEEN INPUT-OUTPUT & MEMORY

OPERATONS. ü WHEN HIGH, PROCESSOR PERFORMS I/O OPERATONS. ü WHEN LOW, PROCRSSOR PERFORMS MEMORY OPERATIONS.

READY. ü WHEN A PERIPHERAL DEVICE, INTERFACED WITH PROCESSOR, IS

SLOWER IN SPEED THAN THE PROCESSOR AT THAT TIME THE READY SIGNAL PLAYS THE ROLE.

ü WHEN IT IS HIGH, THE DEVICE IS READY TO PERFORM THE OPERATIONS.

ALE. ü ADDRESS LATCH ENABLE. ü WHEN IT IS HIGH, THE LOWER ADDRESS IS PRESENT ON THE

ADDRESS BUS. ü ALE GOES HIGH IN START OF EVERY MACHINE CYCLE.



v ARCHITECTURE OF 8085.ARCHITECTURE OF 8085.ARCHITECTURE OF 8085.ARCHITECTURE OF 8085.

[FIG. 1.14 ARCHITECTURE OF 8085]



Ø INTERRUPT SECTION. ü THERE ARE 5 INTERRUPTS IN 8085.

INTERRUPT PRIORITY ADDRESS TRAP 1 0024H RST 7.5 2 003CH RST 6.5 3 0034H RST 5.5 4 002CH INTR 5 -------

ü TRAP IS NON-MASKABLE WHILE OTHER ARE MASKABLE. ü WHEN INTERRUPT COMES ON ONE OF THE PIN, 8085 SUSPENDS

CURRENT ACTIVITY, SAVES THE STATUS. Ø SERIAL CONTROL SECTION.

ü THIS SECTION OF 8085 PROVIDES SERIAL INTERFACE . ü THIS CAN BE ACHIEVED BY SID & SOD PINS. ü DATA ENTERS 8085 THROUGH Serial Input Data PIN. ü DATA COMES OUT FROM 8085 THROUGH Serial Output Data.

Ø Acc. ü IT IS AN 8 BIT REGISTER. ü IT IS USED IN ALL ARITHMATIC & LOGICAL OPERATIONS. ü IT STORES THE RESULT AFTER OPERATIONS. ü IT IS USED TO DEAL WITH MEMORY DIRECTLY.

Ø ALU. ü ARITHMATIC & LOGICAL UNIT. ü IT CONTAINS LOGIC CIRCUITS WHICH IS RESPONSIBLE FOR ALL

TYPE OF ARITHMATIC & LOGICAL OPERATION. ü ALU RECEIVES DATA FROM Acc OR REGISTERS. ü THEN ALU PROCESSES ON THE DATA & STORES RESULT IN Acc. ü AT THAT TIME IT ALSO ACCESSES THE FLAG REGISTER.



Ø FLAG REGISTER. ü IT IS AN 8-BIT REGISTER CONTAINING 5 1-BIT FLAGS. ü IT SHOWS THE CONDITIONS OF THE RESULTS.

S Z ----- AC ----- P ----- CY

ü SIGN :- IF RESULT IS NEGATIVE THEN IT IS SET OTHERWISE RESET. ü ZERO :- IF RESULT IS ZERO THAN IT IS SET OTHERWISE RESET. ü Auxiliary Carry :- IN RESULT IF CARRY IS X’FERED FROM BIT D3 TO D4

THAN AC FLAG IS SET OTHERWISE RESET. ü PARITY :- IN RESULT IF NO. OF 1’S IS EVEN THEN IT IS SET

OTHERWISE RESET. ü CARRY :- IF A CARRY IS OUT FROM D7 BIT THEN IT IS SET

OTHERWISW RESET.

Ø INSTRUCTION REGISTER & DECODER. ü DURING THE OPCODE FETCH CYCLE, THE 8-BIT OPCODE OF AN

INSTRUCTION IS X’FERED FROM MEMORY TO THIS REGISTER. ü INSTRUCTION DECODER DECODES THIS OPCODE TO FIND THE

MEANING OF THE INSTRUCTION. Ø GENERAL PURPOSE REGISTERS.

ü THEY ARE USED TO STORE THE DATA. ü GENERALLY THEY ARE OF 8-BIT IN SIZE. B,C,D,E,H, & L ü FOR 16-BIT OPERATION THEY ARE USED TOGETHER MAKE A PAIR

LIKE BC,DE & HL. Ø PROGRAM COUNTER.

ü IT IS A 16-BIT REGISTER. ü IT STORES THE ADDRESS OF THE NEXT INSTRUCTION TO BE

FETCHED.



Ø STACK POINTER. ü IT IS A 16-BIT REGISTER. ü IT STORES THE ADDRESS OF TOP OF STACK.

Ø TIMING & CONTROL UNIT. ü IT CONTROLS ALL OF THE OPERATIONS OF PROCESSOR. ü IT GENERATES TIMING & CONTROLLING SIGNALS TO SYNCHRONIZE

OPERATIONS.

v DEMULTIPLEXING OF MULTIPLEXED ADD/DATA BUS DEMULTIPLEXING OF MULTIPLEXED ADD/DATA BUS DEMULTIPLEXING OF MULTIPLEXED ADD/DATA BUS DEMULTIPLEXING OF MULTIPLEXED ADD/DATA BUS .... Ø THE LOWER ADDRESS & DATA BUS IS MULTIPLEXED MAKING AD0 – AD7. Ø IT IS REQUIRED TO DEMULTIPLEX THE LOWER ADDRESS BUS AT EVERY

MACHINE CYCLE. Ø THIS CAN BE ACHIEVED BY ALE SIGNAL MAKING IT HIGH AT EVERY START

OF MACHINE CYCLE. Ø SO WHEN ALE IS LOW DATA IS PRESENT AT THOSE PINS. Ø A LATCH IS ALSO USED IN THIS OPERATION. Ø THIS CAN BE SHOWN AS FOLLOWING :

A15 A15

A8 A8

ALE

8085 A7 LATCH AD0 A0 AD7

D7

D0

[FIG. 1.15 DEMULTIPLEXING OF MULTIPLEXED ADD./DATA BUS]



v PROGRAM STATUS WOPROGRAM STATUS WOPROGRAM STATUS WOPROGRAM STATUS WORD.RD.RD.RD. Ø PSW IS A FLAG REGISTER CONTAINING 5 FLIPFLOPS. Ø THE STSTUS OF EACH FLIPFLOP DEPENDS ON THE RESULT OF

ARITHMATIC & LOGICAL OPERATIONS ONLY. Ø THE FLAGS ARE NOT AFFECTED BY DATA X’FER OPERATIONS. Ø FORMATE OF PSW IS AS SHOWN BELOW :

D7 D6 D5 D4 D3 D2 D1 D0

S Z ------ AC ----- P ----- CY

[FIG. 1.16 FLAG REGISTER OF 8085]

1.) SIGN FLAG.

ü IT INDICATES THE SIGN OF RESULT. ü SIGN CAN BE DECIDED FROM THE FIRST BIT OF THE RESULT. ü IF 1ST BIT = 1 THEN RESULT IS NEGATIVE, S BIT IS SET TO 1. ü IF 1ST BIT = 0 THEN RESULT IS POSITIVE, S BIT IS SET TO 0.

1

1 0 1 1 0 1 0 1

1 0 1 0 0 0 1 0

1) 0 1 0 1 0 1 1 1 S BIT = 0

ü THE BIT NO. D7 IS 0, INDICATING IN BOX, SO RESULT IS POSITIVE & SIGN FLAG IS RESET.

2.) ZERO FLAG.

ü IF RESULT AFTER OPERATION IS ZERO THEN Z FLAG IS SET TO 1.

1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1

1) 0 0 0 0 0 0 0 0 Z BIT = 1



3.) AUXILIARY CARRY FLAG.

ü THIS FLAG IS SET WHEN CARRY IS X’FERED FROM BIT D3 TO D4.

1 1 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0

1) 0 0 1 1 0 1 1 0 AC FLAG = 1

4.) PARITY FLAG.

ü PARITY MEANS NUMBER OF 1’S. ü IN RESULT IF NO. OF 1’S IS EVEN THEN FLAG IS SET TO 1. ü IF NO. OF 1’S IS ODD THEN FLAG IS SET TO 0.

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 1 0 1 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 0 0 0 0 0 0 1) 0 1 0 0 0 0 0 0 NO. OF 1 = 2, NO. OF 1 = 1, 2 IS EVEN NO. 1 IS ODD NO. SO P FLAG = 1 SO P FLAG = 0

5. CARRY FLAG.

ü IF CARRY IS OUT FROM D7 BIT THEN CARRY FLAG IS SET TO 1. 1 1 1 1 1 1 1

0 1 0 1 0 1 1 1 1 1 1 0 1 0 0 1 1) 0 1 0 0 0 0 0 0 CY FLAG = 1

ü HERE 1 IS OUT FROM D7 BIT, INDICATING IN A BOX, SO CARRY FLAG IS

SET TO 1.



v GENERATION OF CONTROL SIGNALS.GENERATION OF CONTROL SIGNALS.GENERATION OF CONTROL SIGNALS.GENERATION OF CONTROL SIGNALS. Ø PROCESSOR DONE BASICALLY 4 OPERATIONS AS LISTED BELOW :

ü MEMORY READ TO READ DATA FROM MEMORY. ü MEMORY WRITE TO WRITE DATA INTO MEMORY. ü I/O READ TO READ DATA FROM INPUT DEVICES. ü I/O WRITE TO WRITE DATA TO OUTPUT DEVICES.

Ø FOR MEMORY OPERATIONS I Ø FOR EACH & EVERY OPERATIONS PROCESSOR GENERATES CONTROL

SIGNALS AS FOLLOWING : ü FOR MEMORY READ MEMR. ü FOR MEMORY WRITE MEMW. ü FOR I/O READ IOR. ü FOR I/O WRITE IOW.

Ø PROCESSOR USES THREE PINS FOR THE PURPOSE : ü IO/M. ü RD. ü WR.

Ø WHETHER PROCESSOR DOES MEMORY OR I/O OPERATIONS CAN BE DECIDED FROM IO/M PIN. AS WELL AS READ OR WRITE OPERATION CAN BE SELECTED FROM THE INPUTS AT RD & WR PINS.

Ø HIGH LOGIC,1, AT IO/M PIN INITIATES I/O OPERATIONS. Ø LOW LOGIC,0, AT IO/M PIN INITIATES MEMORY OPERATIONS. Ø LOW LOGIC,0, AT RD PIN INITIATES READ OPERATIONS. Ø LOW LOGIC,0, AT WR PIN INITIATES WRITE OPERATIONS.

Ø THERE ARE TWO METHODS TO GENERATE THESE CONTROL SIGNALS. 1.) USING 3X8 DECODER. 2.) USING NAND GATE.



1,) GENERATION OF CONTROL SIGNALS USING 3X8 DECODER.

[FIG. 1.17 GENERATION OF CONTROL SIGNALS USING 3X8 DECODER.]

IO/M

RD

WR CONTROL

SIGNAL

0 0 1 MEMR

0 1 0 MEMW

1 0 1 IOR

1 1 0 IOW



2,) GENERATION OF CONTROL SIGNALS USING NAND GATE.

IO/M RD WR

MEMR

MEMW

IOR

IOW

[FIG. 1.18 GENERATION OF CONTROL SIGNALS USING NAND GATES.]

Ø COMBINATION OF IO/M(LOW) & RD(LOW) GENERATES MEMR SIGNAL. Ø COMBINATION OF IO/M(LOW) & WR(LOW) GENERATES MEMW SIGNAL. Ø COMBINATION OF IO/M(HIGH) & RD(LOW) GENERATES IOR SIGNAL. Ø COMBINATION OF IO/M(HIGH) & WR(LOW) GENERATES IOW SIGNAL.



Ø GENERATE MEMR FROM IO/M & RD USING 2 TO 4 DECODER.

IO/M

2X4 DECODER MEMR

RD

[FIG. 1.19 GENERATION OF MEMR FROM IO/M & RD USING 2X4 DECODER.]

Ø GENERATE IOR FROM IO/M & RD USING 2 TO 4 DECODER.

IO/M

2X4 DECODER IOR

RD

[FIG. 1.20 GENERATION OF IOR FROM IO/M & RD USING 2X4 DECODER.]



Ø GENERATE MEMW FROM IO/M & WR USING 2 TO 4 DECODER

IO/M

2X4 DECODER MEMW

WR

[FIG. 1.21 GENERATION OF MEMW FROM IO/M & WR USING 2X4 DECODER.]

Ø GENERATE IOW FROM IO/M & WR USING 2 TO 4 DECODER.

IO/M

2X4 DECODER IOW

WR

[FIG. 1.22 GENERATION OF IOW FROM IO/M & WR USING 2X4 DECODER.]



v THE MICROPROCETHE MICROPROCETHE MICROPROCETHE MICROPROCESSOR OPERATIONS.SSOR OPERATIONS.SSOR OPERATIONS.SSOR OPERATIONS. Ø BASICALLY A PROCESSOR

ü ACCEPTS DATA FROM INPUT DEVICES, ü PERFORMS TASKS BASED ON GIVEN INSTRUCTIONS, ü GIVE THE OUTPUT TO REAL WORLD.

Ø THE FUNCTIONS CAN BE CLASSIFIED INTO THREE CATEGORIES, 1.) MICROPROCESSOR INITIATED OPERATIONS. 2.) INTERNAL DATA MANIPULATION. 3.) PERIPHERAL INITIATED OPERATIONS.

Ø EACH OPERATION IS PERFORMED IN SYNCHRONIZATION WITH CLOCK PULSE CALLED T-STATE.

1.) MICROPROCESSOR INITIATED OPERATIONS.

Ø IT PERFORMS 4 BASIC OPERATIONS AS : ü MEMORY READ, ü MEMORY WRITE, ü IO READ, ü IO WRITE.

Ø TO PERFORM THESE OPERATIONS, PROCESSOR PERFORMS THREE STEPS AS :

ü TO IDENTIFY MEMORY LOCATION FOR MEMORY OPERATION & I/O DEVICES BY I/O PORT ADDRESS.

ü X’FER THE DATA. ü PROVIDE THE NECESSARY CONTROL SIGNALS.

Ø THIS CAN BE SHOWN BELOW IN THE FORM OF TIMING DIAGRAM. ü ALE GOES HIGH TO FETCH LOWER ADDRESS, ü AFTER THEN ALE GOES LOW & DATA IS PRESENT ON THE BUS, ü IT INITIATES CONTROL SIGNALS ACCORDING TO THE OPERATION, ü DATA IS X’FERED TO THE DATA BUS.



Ø TIMING DIAGRAM OF MEMORY READ CYCLE

[FIG. 1.23 TIMING DIAGRAM OF MEMORY READ CYCLE.]

T1 T2 T3

CLK

ALE

A15- A8

AD7-AD0

IO/M

RD

MEMR

HIGH – ORDER ADDRESS

LOW ORDER ADDRESS

DATA FROM MEMORY

M



Ø 3 T–STATES ARE REQUIRED TO COMPLETE A MEMORY READ CYCLE.

Ø DURING 1ST T-STATE:

ü ALE GOES HIGH,

ü 8085 PLACES THE HIGHER ADDRESS ON A8 TO A15,

ü 8085 PLACES THE LOWER ADDRESS ON AD0 TO AD7,

ü IO/M GETS LOW LOGIC TO INDICATE MEMORY OPERATION,

Ø DURING 2ND & 3RD T-STATE :

ü RD GOES LOW FOR READ OPERATION

ü 8085 GENERATES MEMR CONTROL SIGNAL.

ü THEREFORE MEMORY DEVICE PLACES THE CONTENT OF MEMORY ON DATA BUS.

Ø THIS IS THE WAY IN WHICH PROCESSOR READS THE MEMORY CONTENT.

Ø TIMING DIAGRAM OF MEMORY WRITE CYCLE.

Ø 3 T–STATES ARE REQUIRED TO COMPLETE A MEMORY WRITE CYCLE.

Ø DURING 1ST T-STATE:

ü ALE GOES HIGH,

ü 8085 PLACES THE HIGHER ADDRESS ON A8 TO A15,

ü 8085 PLACES THE LOWER ADDRESS ON AD0 TO AD7,

ü IO/M GETS LOW LOGIC TO INDICATE MEMORY OPERATION,

Ø DURING 2ND & 3RD T-STATE :

ü WR GOES LOW FOR WRITE OPERATION

ü 8085 GENERATES MEMW CONTROL SIGNAL.

ü THEREFORE MEMORY DEVICE READS THE CONTENT OF MEMORY FROM PROCESSOR.

Ø THIS IS THE WAY IN WHICH PROCESSOR WRITES INTO THE MEMORY.



[FIG. 1.24 TIMING DIAGRAM OF MEMORY WRITE CYCLE.]

HIGH – ORDER ADDRESS

CLK

ALE

A15- A8

AD7-AD0

IO/M

WR

MEMW

LOW ORDER ADDRESS

DATA FROM MPU

M

T1 T2 T3



2.) INTERNAL DATA MANIPULATION.

Ø DATA IS X’FERED TO THE PROCESSOR THROUGH MEMORY READ &/OR I/O READ OPERATIONS.

Ø THEN AFTER PROCESSOR PERFORMS OPERATIONS ON THIS DATA AS IN FOLLOWING SEQUENCE :

ü IT STORES THE 8 – BIT DATA,

ü DECODE THE DATA,

ü PERFORM THE ARITHMATIC & LOGICAL OPERATION ACCORDING TO THE INSTRUCTION,

ü STORE THE RESULT.

3.) EXTERNALLY INITIATED OPERATIONS :

Ø EXTERNAL DEVICES CAN INITIATE THE FOLLOWING OPERATIONS BY SENDING SIGNAL ON SPECIFIC PIN OF THE PROCESSOR :

ü RESET.

§ THIS OPERATION CAN BE INITIATED BY MAKING RESET IN SIGNAL LOW OF 8085.

§ WHEN RESET IS ACTIVATED, THE 8085 SUSPENDS ALL THE CURRENT ACTIVITIES.

§ IT STOPS ALL THE OPERATIONS & GOES AT THE STARTING OF THE PROGRAM & HENCE CLEAR THE PROGRAM COUNTER.

§ IT MEANS THE VALUE OF PC AFTER RESET IS PC = 0000H.

ü INTERRUPT.

§ THE EXTERNAL DEVICES CAN DISTURB THE 8085’S CURRENT OPERATIONS.

§ THE INTERRUPTION CAN BE CREATED BY SENDING SIGNAL ON ONE OF THE INTERRUPT PINS.



§ WHEN PERIPHERAL DEVICE SENDS INTERRUPT TO PROCESSOR :

• PROCESSOR SAVES CURRENT STATUS OF PC ON STACK

• CONTROLS (PC) ARE X ‘FERED TO THE DEVICE,

• DEVICE EXECUTES THE GROUP OF INSTRUCTUIONS CALLED INTERRUPT SERVICE ROUTINE (ISR),

• AFTER COMPLETING ISR, IT RESUMS NORMAL EXECUTION WHICH CONTENT IS SAVED ON STACK,

ü READY.

§ THIS IS USED TO SYNCHRONIZE THE OPERATION OF THE SLOWER DEVICE WITH THE PROCESSOR.

ü HOLD.

§ WHEN HOLD GOES HIGH, THE 8085 COMPLETES THE CURRENT CYCLE & LEAVES THE CONTROL OF BUSES IN ORDER TO ALLOW THE OTHER PERIPHERAL DEVICES.

v 8085 INTERRUPTS.8085 INTERRUPTS.8085 INTERRUPTS.8085 INTERRUPTS.

Ø THERE ARE FIVE INTERRUPTS IN 8085 :

ü TRAP - MASKABLE,

ü RST 7.5 - NON MASKABLE,



ü INTR - NON MASKABLE,

Ø WHEN INTERRUPT COMES ON ONE OF THE 8085 PINS :

ü 8085 SUSPENDS CURRENT ACTIVITY,

ü SAVES THE STATUS ON THE STACK,

ü JUMPS ON THE ADDRESS WHERE SPECIFIC ISR IS WRITTEN.



Ø PRIORITY :

ü ALL THE INTERRUPTS WORK ON THEIR PRIORITY WHICH IS DEFAULT IN PROCESSOR.

ü THEY ARE LISTED AS BELOW :

NAME OF INTERRUPT PRIORITY

TRAP 1

RST 7.5 2

RST 6.5 3

RST 5.5 4

INTR 5

Ø INTA :- INTERRUPT ACKNOWLEDGEMENT.

ü THIS IS ACTIVE LOW SIGNAL & GENERATED BY PROCESSOR IN THE RESPONSE OF THE INTERRUPT REQUEST.

Ø VECTOR ADDRESS :

ü WHEN INTERRUPT COMES ON ONE OF THE 8085 PIN, THE PC JUMPS TO SPECIFIC ADDRESS WHERE ISR (INTERRUPT SERVICE ROUTINE) IS WRITTEN.

ü THAT ADDRESS IS CALLED VECTOR ADDRESS. THAT ADDRESS IS AS GIVEN BELOW :

NAME OF INTERRUPT ADDRESS

TRAP 0024H

RST 7.5 003CH

RST 6.5 0034H

RST 5.5 002CH

INTR ADD. GIVEN BY EXT. INTERRUPT CONTROLLER



v QUESTIONS ASKED FOR 2 MARKS. 1.) GIVE THE MAJOR DIFFERENCE BETWEEN RAM & ROM.

Ø RAM CAN BE READ & WRITTEN WHILE ROM CAN ONLY BE READ NOT

WRITTEN.

Ø RAM IS A TEMPORARY STORAGE WHERE AS ROM IS A PERMANENT

STORAGE.

2.) WHAT HAPPENS WHEN INTERRUPT COMES ?

Ø PROCESSOR STOPS EXECUTION OF ALL CURRENT ACTIVITIES.

Ø PC GETS 0000H VALUE.

Ø PROCESSOR X’FERS THE CONTROLS TO THE PERIPHERALS.

3.) WHY DO WE REQUIRE TO DEMULTIPLEX MULTIPLEXED ADD/DATA BUS ?

Ø OPCODES & DATAA ARE STORED IN MEMORY HAVING 16 BIT ADDRESS, A8 TO A15 HIGHER ADDRESS & AD0 TO AD7 LOWER ADDRESS.

Ø AT EACH MACHINE CYCLE WE NEED A COMPLETE 16 BIT ADDRESS.

Ø A8 TO A15, MEANS HIGHER ADDRESS IS AVAILABLE INDIVIDUALLY AT PIN NO. 20 TO 28.

Ø BUT LOWER ADDRESS LINES ARE MULTIPLEXED WITH THE DATA BUS SO WE NEED TO DEMULTIPLEX THEM.

4.) WHAT DO YOU MEAN BY FETCH-DECODE-EXECUTE CYCLE ?

Ø EACH & EVERY INSTRUCTION HAS AN OPCODE WHICH IS STORED IN MEMORY.

Ø THE TIME REQUIRED TO FETCH THE OPCODE FROM MEMORY IS CALLED FETCH CYCLE.

Ø THE TIME REQUIRED TO DECODE THAT FETCHED OPCODE IS CALLED DECODE CYCLE.

Ø THE TIME REQUIRED TO EXECUTE THE DECODED OPCODE IS CALLED EXECUTE CYCLE.



5.) WHY ARE PC & SP 16 BIT IN 8085 ?

Ø PROGRAM COUNTER (PC) STORES THE ADDRESS OF THE NEXT INSTRUCTION TO BE FETCHED.

Ø STACK POINTER (SP) STORES THE ADDRESS OF THE TOP OF THE STACK.

Ø MEANS BOTH THE REGISTERS STORE THE16 BITS ADDRESS SO SIZE OF THOSE REGISTERS IS 16 BIT.

6.) WHAT IS STACK ? WHAT IS THE USE OF STACK POINTER ?

Ø STACK IS THE PART OF RAM, USED TO STORE TEMPORARY DATA.

Ø STACK POINTER STORES THE ADDRESS OF TOP OF STACK.

7.) WHY DOES ROM CHIP HAS ONLY RD ?

Ø ROM MEANS READ ONLY MEMORY. IT CAN ONLY BE READ NOT

WRITTEN SO IT HAS ONLY RD TERMINAL NOT WR.

8.) GIVE THE FORMATE OF FLAG REGISTER.

D7 D6 D5 D4 D3 D2 D1 D0

S Z ----- AC ----- P ----- CY

9.) WHAT HAPPENS WHEN 8085 RECIEVES THE RESET SIGNAL ?

Ø FIRST OF ALL, PROCESSOR SUSPENDS ALL THE CURRENT OPERATIONS.

Ø PROCESSOR CLEARS THE PROGRAM COUNTER i.e. PC STORES 0000H.

10.) GIVE THE IMPORTANCE OF READY SIGNAL.

Ø THIS SIGNAL IS USED TO SYNCHRONIZE THE OPERATION OF SLOWER DEVICES WITH THE PROCESSOR.

Ø WHEN READY GOES LOW, THE PROCESSOR GOES INTO WAIT STATE & REMAINS IDLE UNTIL READY GOES HIGH AGAIN.



11.) LIST THE PERIPHERAL INITIATED OPERATIONS.

Ø RESET, INTERRUPT, READY, HOLD.

12.) GIVE THE FUNCTIONS OF CONTROL SIGNALS : IO/M, RD, & WR.

Ø IO/M DECIDES WHETHER THE OPERATION IS IO TYPE OR MEMORY TYPE.

Ø RD SIGNAL ACTIVATES READ OPERATION.

Ø WR SIGNAL ACTIVATES WRITE PERATION.

Ø THE COMBINATION OF THESE THREE SIGNSLS GENERATES CONTROL SIGNSLS LIKE : MEMORY READ, MEMORY WRITE, IO READ & IO WRITE.

13.) LIST THE 8085 MACHINE CYCLES ALONG WITH STATUS SIGNAL VALUES.

MACHINE CYCLE IO/M S1 S0

MEMORY WRITE 0 0 1

IO WRITE 1 0 1

MEMORY READ 0 1 0

IO READ 1 1 0

OPCODE FETCH 0 1 1

INTERRUPT ACKNOWLEDGE 1 1 1

HALT * 0 0

HOLD * X X

RESET * X X

14.) GIVE THE FUNCTION OF PROGRAM COUNTER.

Ø PC STORES THE 16 BIT ADDRESS OF THE NEXT INSTRUCTION TO BE FETCHED.

15.) GIVE THE FUNCTION OF ALE PIN OF 8085.

Ø ALE IS USED TO FETCH THE LOWER 8-BIT ADDRESS FROM MULTIPLEXED ADDRESS & DATA BUS.



16.) GIVE THE FUNCTIONS OF HOLD & HLDA PINS OF 8085.

Ø THESE SIGNALS ARE USED WITH DMA CONTROLLER.

Ø DMA CONTROLLER USES HOLD TO SEND THE REQUEST FOR GRANTING THE CONTROL OF BUSES TO PROCESSOR.

Ø HLDA IS USED BY PROCESSOR TO ACKNOWLEDGE THE GRANTING OF REQUEST.

17.) HOW DO YOU DETERMINE THE MAXIMUM MEMORY THAT CAN BE ACCESSED BY A PROCESSOR ?

Ø AMOUNT OF MEMORY CAN BE FOUND BY TAKING THE ADDRESS LINES POWER OF THE 2.

Ø AMOUNT OF MEMORY = 2ADDRESS LINES

(OCTOBER/NOVEMBER-2001)

18.) DIFFERENTIATE ACTIVE HIGH & ACTIVE LOW LOGIC.

Ø ACTIVE HIGH LOGIC MEANS PIN IS ACTIVATED WHEN 1 LOGIC IS APPLIED AT THAT PIN IS CALLED ACTIVE HIGH LOGIC.

Ø ACTIVE LOW LOGIC MEANS PIN IS ACTIVATED WHEN 0 LOGIC IS APPLIED AT THAT PIN IS CALLED ACTIVE LOW LOGIC.

19.) ENUMERATE INTERRUPT PINS OF 8085 PROCESSOR.

NAME OF PIN PIN NUMBER

TRAP 6

RST 7.5 7

RST 6.5 8

RST 5.5 9

INTR 10

INTA 11



20.) DRAW DIAGRAM TO GENERATE MEMR FROM IO/M & RD USING 2X4 DECODER.

IO/M 2 X 4

MEMR

RD DECODER

21.) DIFFERENTIATE LATCH & BUFFER.

Ø LATCH IS ONE TYPE OF MEMORY WHICH REMEMBERS THE LAST STATE.

Ø BUFFER IS USED TO INCREASE THE STRENGTH OF THE INPUT SIGNAL.

22.) WHAT IS TRI-STATE ?

Ø THE DEVICE HAVING THREE STATES NAMED ‘0’, ‘1’, & ‘Z’.

Ø Z MEANS HIGH IMPEDANCE.

23.) WHAT IS T-STATE ?

Ø T-STATE IS A SUB DIVISION OF A MACHINE CYCLE.

Ø A MACHINE CYCLE CONSISTS NUMBER OF T-STATES AS PER OPERATION.

I/P CONTROL

C O/P

0 0 Z

1

0 1 0

1 1 1

I/P

C

O/P



24.) STARTING ADDRESS OF MEMORY OF 1 Kb IS 7000H THEN WHAT IS ENDING ADDRESS OF THAT MEMORY ?

Ø CALCULATION OF ADDRESS LINES :- ADDRESS LINES TO ACCESS MEMORY = 1KB = 1K X 1

= 210

X 20

=210


A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS

0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 7000H

0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 73FFH

Ø ENDING ADDRESS IS 73FFH.

25.)ONE PROCESSOR IS HAVING 8-BIT DATA BUS & 12-BIT ADDRESS BUS. CALCULATE MAXIMUM ADDRESSING CAPACITY OF THAT PROCESSOR.

Ø MAXIMUM ADDRESSING CAPACITY DEPENDS UPON NO. OF ADDRESS BUS NOT ON DATA BUS, SO IT IS NO MATTER THAT HOW MANY DATA BUS IS GIVEN.

Ø MAXIMUM ADDRESSING CAPACITY = 2NO. OF ADDRESS BUS

= 212

=210 X 22 =1K X 4 =4Kbyte

Ø MAXIMUM ADDRESSING CAPACITY OF THE PROCESSOR IS 4K. 26.) WHAT IS MULTIPLEXING ? WHY IT IS NEEDED IN PROCESSOR FOR ADDRESS DATA.

Ø MULTIPLEXING MEANS MORE THAN ONE QUANTITY CAN BE PRESENT ON A SINGLE WIRE.

Ø HERE ADDRESS & DATA ARE AVAILABLE AT PIN AD0 TO AD7 CALLED MULTIPLEXED ADDRESS DATA BUS.

Ø IT IS USED TO SAVE THE NUMBER OF PINS TO MAKE THE CHIP SMALLER IN AREA.



27.) GIVE THE FUNCTION OF STACK.

Ø STACK IS THE AREA OF A RAM.

Ø IT IS USED TO STORE THE DATA TEMPORARY.

(OCTOBER/NOVEMBER – 2003)

28.) DEFINE MACHINE CYCLE & INSTRUCTION CYCLE.

Ø THE TIME REQUIRED TO COMPLETE A SINGLE OPERATION IS CALLED A MACHINE CYCLE.

Ø THE TIME REQUIRED TO COMPLETE THE EXECUTION OF AN INSTRICTION IS CALLED INSTRUCTION CYCLE.

29.) DRAW FLAG REGISTER INDICATING ALL FLAGS SYMBOL & EXPLAIN FUNCTION OF AC.

D7 D6 D5 D4 D3 D2 D1 D0 S Z ----- AC ----- P ----- CY

SIGN ZERO AUXILIARY CARRY PARITY CARRY

Ø AC FLAG IS SET WHEN CARRY IS X’FFERED ROM BIT D3 TO D4.

30.) WHAT IS THE FUNCTION OF READY PIN.

Ø SEE THE ANSWER OF QUESTION NO. 10.

31.) IF ANY ARBITRARY PROCESSOR HAS 12-BIT ADDRESS LINE & 8-BIT DATA LINE. FIND OUT ADDRESSING CAPABILITY OF THAT PROCESSOR.


32.) DIFFERENTIATE ACTIVE HIGH & ACTIVE LOW LOGIC. Ø SEE THE ANSWER OF QUESTION NO. 18.



MAY/JUNE – 2004

33.) WHAT IS PROGRAM COUNTER ? WHAT IS SIZE OF PC IN 8085

PROCESSOR ?

Ø PC STORES THE 16 BIT ADDRESS OF THE NEXT INSTRUCTION TO BE FETCHED.

Ø THE SIZE OF THE PC IS 16 BIT.

34.) WHAT IS THE FUNCTION OF ALE SIGNAL IN 8085 PROCESSOR.

Ø ALE IS USED TO FETCH THE LOWER 8-BIT ADDRESS FROM MULTIPLEXED ADDRESS & DATA BUS, WHEN IT IS HIGH.

APRIL/MAY – 2005

35.) WHAT IS ALE ? GIVE ITS FUNCTIONALITY.


36.) GIVE IMPORTANCE OF AC FLAG IN 8085.


37.) GIVE THE FUNCTION OF SP & PC.

Ø SP STORES THE 16-BIT ADDRESS OF TOP OF THE STACK.

Ø PC STORES THE 16-BIT ADDRESS OF THE NEXT INSTRUCTION TO BE FETCHED.

38.) DRAW THE CIRCUIT TO GENERATE IOR, IOW, MEMR & MEMW FROM RD, WR & IO/M USING 3X8 DECODER.

8085 DECODER MEMW

IO/M A MEMR

RD B

WR C IOW

IOR



39.) WHAT IS THE DIFFERENCE BETWEEN OPCODE FETCH & MEMORY READ CYCLE ?

Ø IN OPCODE FETCH CYCLE OPCODE OF AN INSTRUCTION IS FETCHED FROM MEMORY. IT IS A CODE OF AN INSTRUCTION STORED IN MEMORY. IT COCSISTS OF 4 T-STATES.

Ø DURING MEMORY READ CYCLE DATA IS BEING FETCHED FROM THE MEMORY. IT CONSISTS OF 3 T-STATES.

40.) WHAT IS THE FUNCTION OF READY PIN OF 8085. Ø SEE THE ANSWER OF QUESTION NO. 10.

APRIL/MAY – 2006

41.) THE VECTOR ADDRESS OF TRAP IS 0024H.

42.) SID & SOD PINS OF 8085 ARE USED FOR SERIAL I/O.

43.) IF STARTING ADDRESS OF 8K RAM IS 8000H, THEN ENDING ADDRESS IS 9FFFH. 44.) THE REGISTER ALWAYES POINTING TO THE LOCATION OF NEXT INSTRUCTION TO BE FETCHED IS PROGRAM COUNTER. JUNE/JULY – 2008 45.) GIVE SIGNIFICANCE OF ALE.

Ø SEE THE ANSWER OF Q.15. 46.) WHAT IS STACK? WHAT IS FUNCTION OF SP?

Ø SEE THE ANSWER OF Q.27. & Q.37. 48.) GIVE THE FULL FORM OF PSW. DRAW STRUCTURE OF IT.

Ø Program Status World. Ø FOR STRUCTURE, SEE THE ANSWER OF Q.29.

49.) LIST THE FUNCTION OF CONTROL SIGNALS IO/M, RD, & WR. Ø THEY ARE USED TO GENERATE THE CONTROL SIGNALS AS :

ü MEMR FROM IO/M & RD. ü MEMW FROM IO/M & WR. ü IOR FROM IO/M & RD. ü IOW FROM IO/M & WR.



50.) LIST THE INTERRUPT PINS. Ø TRAP, RST 7.5, RST 6.5, RST 5.5, INTR, & INTA.

51.) GIVE THE FUNCTION OF HOLD & HLDA PINS OF 8085. Ø SEE THE ANSWER OF Q.16.

52.) DIFFERENTIATE BETWEEN MASKABLE & NON MASKABLE INTERRUPTS. Ø THE EXECUTION OF MASKABLE INTERRUPTS CAN BE STOPPED BY

MEANS OF EITHER BY SOFTWARE OF BY HARDWARE. Ø BUT THE EXECUTION OF NON MASKABLE INTERRUPTS CAN NOT BE

STOPPED BY ANY HOW. (OCTOBER/NOVEMBER-2008)

53.) DRAW FLAG REGISTRY OF 8085. EXPLAIN ANY ONE.

Ø SEE THE ANSWER OF Q.29.

54.) EXPLAIN FUNCTION OF ALE PIN IN BRIEF.

Ø SEE THE ANSWER OF Q.15. & Q.34.

55.) WHAT IS THE VALUE OF PROGRAM COUNTER AT THE TOME OF RESET?

Ø 0000H.

56.) DRAW THE CIRCUIT TO GENERATE IOR & IOW FROM RD, WR & IO/M.

Ø SEE THE ANSWER OF Q.38.

v QUESTION ASKED FOR 5 MARKS. OCTOBER/NOVEMBER - 2001

1.) DRAW & EXPLAIN BLOCK DIAGRAM OF ARCHITECTURE OF 8085 MICROPROCESSOR WITH NEAT SKETCH.

2.) DRAW DIAGRAM FOR DEMULTIPLEXING OF ADDRESS & DATA BUS. EXPLAIN IT.



MAY/JUNE - 2002

3.) Q.1.

4.) DRAW STRUCTURE OF FLAG REGISTER & EXPLAIN EACH FLAG.

5.) Q.2.

6.) TABULATE ALL TYPES OF M/C ALONG WITH RD, WR, IO/M, S1 & S0. EXPALIN IMPORTANCE OF STATUS SIGNALS.

7.) DRAW & EXPLAIN REGISTER FILE IN 8085. ENUMARATE GENERAL PURPOSE REGISTERS & SPECIAL PURPOSE REGISTERS & GIVE ITS SPECIALITY.

8.) MEMORY MAPPING IN 8085 BASED SYSTEM.

OCTOBER/NOVEMBER - 2002

9.) Q.1.

10.) EXPLAIN INTERRUPT SYSTEM OF 8085 IN DETAIL.

11.) DRAW THE CIRCUIT TO GENERATE IOR, IOW, MEMR & MEMW FROM RD, WR & IO/M USING 3X8 DECODER.

12.) Q.4.

13.) FUNCTION OF PROGRAM COUNTER & STACK POINTER.

MAY/JUNE - 2003

14.) Q.1.

15.) Q.4.

16.) Q.7.


17.) Q.1.

18.) Q.11.

19.) Q.13.



MAY/JUNE - 2004

20.) Q.1.

21.) Q.11.

22.) Q.10.


23.) EXPLIAN 8 – BIT & 16 – BIT REGISTERS IN 8085 PROCESSOR.

24.) Q.2.

MAY/JUNE - 2005

25.) Q.1.

26.) Q.4.

27.) Q.2.


28.) Q.1.

29.) Q.10.

30.) Q.4.

31.) Q.11.

APRIL/MAY - 2006

32.) Q.4.

33.) WHAT IS BUS ? EXPLIAN BUS ORGANIZATION IN 8085 WITH DIAGRAM.

34.) WHAT IS DMA ? EXPLAIN DMA IN 8085 USING PINS HOLD & HLDA.

35.) Q.2.

NOVEMBER 2006

36.) Q.1.

37.) Q.10.

38.) Q.4.



39.) EXPLAIN MEMORY WRITE OPERATION WITH THE HELP OF TIMING DIAGRAM.

40.) Q.11.

MAY/JUNE - 2007

41.) Q.1.

42.) EXPLAIN BASIC MICROCPMPUTER SYSTEM.

43.) EXPLAIN IN BRIEF, ALL PINS OF 8085 PROCESSOR, WHICH ARE RELATED TO INTERRUPT OPERATION.

44.) EXPLAIN REGISTER STRUCTURE OF 8085. (SAME AS Q.23.)


45.) Q.1. & Q.4.

46.) Q.2.

47.) Q.11. (USING NAND GATE)

JUNE/JULY - 2008

48.) Q.23.

49.) Q.4.

NOVEMBER/DECEMBER - 2008

50.) Q.1.

8085 Material

Documents

d4 ac d3

internal data

finding address

divide total

peripheral

active low

basic computer

finding address