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July 3, 2022 Martijn v/d Horst, [email protected] TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst [email protected] Parallel Implementation of IIR Filters
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5 August, 2014 Martijn v/d Horst, [email protected] TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst [email protected].

Mar 31, 2015

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Page 1: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

1

Martijn v/d [email protected]

Parallel Implementation of IIR Filters

Page 2: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

2

Outline

• IIR Filters• Implementation Methods

– Look Ahead– Block-State– Incremental Block-State– Extra buffer

• Comparison• All-pass Filters• Conclusion and Future Work

Page 3: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

3

IIR Filters

InputOutput

Page 4: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

4

Describing Filters

• Transfer Function:

22

11

22

110

1)(

zbzb

zazaazH

• Difference Equation:

)2()1()2()1()()( 21210 nybnybnuanuanuany

)()()(

)()()1(

ndunxcny

nbunAxnxT

0202101

21

0

1

01adbaabaac

bbb

A

T

• State space form:

Page 5: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

5

Implementation

We want:• Sample rates exceeding processing rates• This means parallel inputs and outputs, also

called block implementations• Implementations which scale well

Page 6: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

6

Clustered Look Ahead

• Increase the size of the recursive loop• The order of the filter increases• Might become unstable

nn-2 n-1 nn-P-1 n-P

P

Page 7: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

7

Scattered Look Ahead

• Increase the size of the recursive loop• The order of the filter increases• Remains stable• Can be implemented with P parallel filters• Non-recursive part can be decomposed

nn-2 n-1 nn-2P n-P

PP

Page 8: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

8

Block-State

The state space form can be rewritten into a state space form using input and output vectors:

)()()(

)()()1(

ndunxcny

nbunAxnxT

)()()(

)()())1((

nPuDnPxCnPy

nPuBnPxAPnx

PPPP

PPP

jibAc

jid

ji

D

Ac

Ac

c

C

bbAbAB

jiTijP

PT

T

T

P

PPP

1

1

21

0

...

...

Page 9: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

9

Block-State Architecture

PA PC

PD

PB

Input

OutputState

P

P

P

P

N N

Page 10: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

10

State update

Page 11: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

11

Block-State

PA PC

PD

PB

P

P

P

P

N N

Page 12: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

12

I

Incremental Block-State

PA IC

ID

PB

I

P

N N

I

IA

IB

I

IC

ID

I

I

IA

IB

I

IC

ID

I

I

IA

IB

JI

JIC

JID

JI

I

I

I

JI

N NN

Page 13: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

13

• Transform a Mealey into a Moore Machine

• Filter order increases by one• P - 1 multipliers saved for Block-State• P - P div I multipliers saved for Incremental

Block-State

Extra buffer

State

Output

State

Output

Page 14: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

14

Comparison

Efficiency: The number of multipliers used by an implementation compared to the theoretical optimum number.

A single input, single output implementation of an IIR filter of order N requires 2 N + 1 multipliers.

Therefore the theoretical optimum for an implementation handling P simultaneous inputs and outputs is P (2 N + 1) multipliers.

Page 15: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

15

Efficiencies

2040

6080

100

P20

40

60

80

100

N

00.250.5

0.75

1

2040

6080

100

P

2040

6080

100

P20

40

60

80

100

N

00.250.5

0.75

1

2040

6080

100

P

2040

6080

100

P20

40

60

80

100

N

00.250.5

0.75

1

2040

6080

100

P

2040

6080

100

P20

40

60

80

100

N

00.250.5

0.75

1

2040

6080

100

P

ScatteredLook ahead

Block-state

IncrementalBlock-state

IncrementalBlock-statewith extrabuffer

Page 16: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

16

20 40 60 80 100

0.2

0.4

0.6

0.8

1

20 40 60 80 100

0.2

0.4

0.6

0.8

1

20 40 60 80 100

0.2

0.4

0.6

0.8

1

20 40 60 80 100

0.2

0.4

0.6

0.8

1

Efficiencies

ScatteredLook ahead

Block-state

IncrementalBlock-state

IncrementalBlock-statewith extrabuffer

N=8 N=16

N=32 N=64

Page 17: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

17

All-pass Filters

22

11

21*1

*2

1)(

zczc

zzcczH

• Also called phase shifters

• Theoretical optimum is P N

Page 18: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

18

Conclusion

• Efficient block implementations for IIR filters exist

• These implementations can be used for all-pass filters

• Theoretically there is room for improvement in implementing all-pass filters

Page 19: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

19

Future Work

• Finding more efficient all-pass implementations

• Adaptive Equalizers• Other signal processing algorithms

Page 20: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

20

Questions?

Page 21: 5 August, 2014 Martijn v/d Horst, M.G.v.d.Horst@tue.nl TU/e Computer Science, System Architecture and Networking 1 Martijn v/d Horst M.G.v.d.Horst@tue.nl.

April 11, 2023 Martijn v/d Horst, [email protected]/e Computer Science, System Architecture and Networking

21

Farewell Thang