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Transcript
INDEX
1. INTRODUCTION
2. MICROCONTROLLER
2.1 A Brief History of 8051
2.2 Description of 89C52 Microcontroller
2.3 Block Diagram of Microcontroller
2.4 Pin Configurations
2.5 Timers
2.6 Interrupts
2.7 Special function registers:
2.8 Memory Organization
3. POWER SUPPLY
3.1 Description
3.2 Block Diagram
3.3 Circuit Diagram
3.4 IC Voltage Regulators
4. ULN 2003
4.1 Pin Connection
4.2 Description
5. LCD
5.2 Description
5.1 Pin Connection
8. KEIL SOFTWARE
8.1 Software Description
9. CIRCUIT DIAGRAM
10. SOURCE CODING
11. CONCLUSION
BIBLIOGRAPHY
REFERENCES
ABSTRACT
This Project “SOUND DETECTION SYSTEM” is used to detect the sound using
condenser mic and send this information to microcontroller from there information
is send to the buzzer to indicate sound detected.
An instrument that converts the energy of sound waves into electrical currents is a
microphone. When a person speaks into a microphone, sound waves strike a
flexible diaphragm and cause it to vibrate in the pattern of the sound waves. The
diaphragm is connected to an electric circuit in such a way that the movement of
the diaphragm causes a corresponding change in the circuit, causing an electric
current to flow. The strength of the current is proportional to the pressure applied
to the diaphragm. A telephone mouthpiece is a familiar example of a microphone.
Microphones are also used in hearing aids, public-address systems, and in radio
and television broadcasting. (See also Radio; Telephone.)
Using this condenser mic we can indicate sound detected and also control device.
SOUND DETECTING SYSTEM:
HARDWARE COMPONENTS:
MIC
AMPLIFIER
TIMER
MICRO CONTROLLER
BUZZER
1. 8052 MICROCONTROLLER.
2. Condenser mic.
3. Buzzer.
4. Transformer
5. Regulators
SIMULATION:
TOOL:KEIL MICROVISION
LANGUAGE: EMBEDDED ‘C’
2. MICROCONTROLLER
2.1 A Brief History of 8051
In 1981, Intel Corporation introduced an 8 bit microcontroller called
8051. This microcontroller had 128 bytes of RAM, 4K bytes of chip ROM, two
timers, one serial port, and four ports all on a single chip. At the time it was
also referred as “A SYSTEM ON A CHIP”
The 8051 is an 8-bit processor meaning that the CPU can work
only on 8 bits data at a time. Data larger than 8 bits has to be broken into 8
bits pieces to be processed by the CPU. The 8051 has a total of four I\O ports
each 8 bit wide.
There are many versions of 8051 with different speeds and amount of
on-chip ROM and they are all compatible with the original 8051. This means
that if you write a program for one it will run on any of them.
The 8051 is an original member of the 8051 family. There are two
other members in the 8051 family of microcontrollers. They are 8052 and
8031. All the three microcontrollers will have the same internal architecture,
but they differ in the following aspects.
8031 has 128 bytes of RAM, two timers and 6 interrupts.
89C51 has 4KB ROM, 128 bytes of RAM, two timers and
6 interrupts.
89C52 has 8KB ROM, 128 bytes of RAM, three timers
and 8 interrupts.
Of the three microcontrollers, 89C51 is the most preferable.
Microcontroller supports both serial and parallel communication.
In the concerned project 89C52 microcontroller is used. Here
microcontroller used is AT89C52, which is manufactured by ATMEL
laboratories.
2.2 Description of 89C52 Microcontroller
The AT89C52 provides the following standard features: 8Kbytes of
Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, six-vector
two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89C52 is designed with static logic for
operation down to zero frequency and supports two software selectable
power saving modes. The Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue functioning. The
Power down Mode saves the RAM contents but freezes the oscillator,
disabling all other chip functions until the next hardware reset.
By combining a versatile 8-bit CPU with Flash on a monolithic chip, the
AT89C52 is a powerful microcomputer which provides a highly flexible and
cost effective solution to many embedded control applications.
Features of Microcontroller (89S52)
Compatible with MCS-51 Products
8 Kbytes of In-System Reprogrammable Flash Memory
Endurance: 1,000 Write/Erase Cycles
Fully Static Operation: 0 Hz to 24 MHz
Three-Level Program Memory Lock
256 x 8-Bit Internal RAM
32 Programmable I/O Lines
Three 16-Bit Timer/Counters
Eight vector two level Interrupt Sources
Programmable Serial Channel
Low Power Idle and Power Down Modes
In addition, the AT89C52 is designed with static logic for operation down
to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters,
serial port and interrupt system to continue functioning. The Power down
Mode saves the RAM contents but freezes the oscillator disabling all other
chip functions until the next hardware reset.
2.3 Block Diagram of Microcontroller
Figure 2.1 Block Diagram Of 89C52
2.4 Pin Configurations
Figure 2.2 Pin Diagram of 89C52
Pin Description
VCC
Pin 40 provides Supply voltage to the chip. The voltage source is +5v
GND.
Pin 20 is the grounded
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port from pin 32 to 39. As
an output port each pin can sink eight TTL inputs. When 1s are written to
port 0 pins, the pins can be used as high-impedance inputs. Port 0 may also
be configured to be the multiplexed low-order address/data bus during
accesses to external program and data memory. In this mode P0 has internal
pull-ups.
Port 0 also receives the code bytes during Flash programming, and
outputs the code bytes during program verification. External pull-ups are
required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups from pin 1
to 8. The Port 1 output buffers can sink/source four TTL inputs. When 1s are
written to Port 1 pins they are pulled high by the internal pull-ups and can be
used as inputs. As inputs, Port 1 pins that are externally being pulled low will
source current (IIL) because of the internal pull-ups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2
external count input (P1.0/T2) and the timer/counter 2 trigger input
(P1.1/T2EX), respectively, as shown in following table.
Port 1 also receives the low-order address bytes during Flash
programming and program verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups from pin 21
to 28. The Port 2 output buffers can sink / source four TTL inputs. When 1s
are written to Port 2 pins they are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally being pulled
low will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that uses
16-bit addresses (MOVX @ DPTR). In this application it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that
uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2
Special Function Register. Port 2 also receives the high-order address bits
and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups from pin 10
to 17. The Port 3 output buffers can sink / source four TTL inputs. When 1s
are written to Port 3 pins they are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (IIL) because of the pull-ups.
Port 3 also serves the functions of various special features of the
AT89C52 as listed below:
Table 2.1 Special Features of port3
Port 3 also receives some control signals for Flash programming and
programming verification.
RST
Pin 9 is the Reset input. It is active high. Upon applying a high pulse to
this pin, the microcontroller will reset and terminate all activities. A high on
this pin for two machine cycles while the oscillator is running resets the
device.
ALE/PROG
Address Latch is an output pin and is active high. Address Latch Enable
output pulse for latching the low byte of the address during accesses to
external memory. This pin is also the program pulse input (PROG) during
Flash programming. In normal operation ALE is emitted at a constant rate
of 1/6 the oscillator frequency, and may be used for external timing or
clocking purposes.
Note, however, that one ALE pulse is skipped during each access to
external Data Memory. If desired, ALE operation can be disabled by
setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during
a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
Setting the ALE-disable bit has no effect if the microcontroller is in
external execution mode.
PSEN
Program Store Enable is the read strobe to external program memory.
When the AT89C52 is executing code from external program memory, PSEN
is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external data memory.
EA/VPP
External Access Enable EA must be strapped to GND in order to enable
the device to fetch code from external program memory locations starting at
0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will
be internally latched on reset. EA should be strapped to VCC for internal
program executions. This pin also receives the 12-volt programming enable
voltage (VPP) during Flash programming when 12-volt programming is
selected.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier which can be configured for use as an on chip oscillator,
as shown in Figure 5.3. Either a quartz crystal or ceramic resonator may be
used. To drive the device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 5.4.
Figure 2.3 crystal connections
Figure 2.4 External Clock Drive Configuration
There are no requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is through a divide-by
two flip-flop, but minimum and maximum voltage high and low time
specifications must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip
peripherals remain active. The mode is invoked by software. The content of
the on-chip RAM and all the special functions registers remain unchanged
during this mode. The idle mode can be terminated by any enabled interrupt
or by a hardware reset. It should be noted that when idle is terminated by a
hardware reset, the device normally resumes program execution, from
where it left off, up to two machine cycles before the internal reset algorithm
takes control.
On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminated by reset, the
instruction following the one that invokes Idle should not be one that writes
to a port pin or to external memory.
Power down Mode
In the power down mode the oscillator is stopped, and the instruction
that invokes power down is the last instruction executed. The on-chip RAM
and Special Function Registers retain their values until the power down mode
is terminated. The only exit from power down is a hardware reset. Reset
redefines the SFRs but does not change the on-chip RAM. The reset should
not be activated before VCC is restored to its normal operating level and
must be held active long enough to allow the oscillator to restart and
stabilize.
Table 2.2 Status Of External Pins During Idle and Power Down
Mode
Program Memory Lock Bits
On the chip are three lock bits which can be left unprogrammed (U) or
can be programmed (P) to obtain the additional features listed in the table
5.4. When lock bit 1 is programmed, the logic level at the EA pin is sampled
and latched during reset. If the device is powered up without a reset, the
latch initializes to a random value, and holds that value until reset is
activated. It is necessary that the latched value of EA be in agreement with
the current logic level at that pin in order for the device to function properly.
Table 2.3 Lock Bit Protection Modes
TIMERS
Timer 0 and 1
Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0
and Timer 1 in the AT89C51.
Register pairs (TH0, TL1), (TH1, TL1) are the 16-bit counter registers
for timer/counters 0 and 1.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or
an event counter. The type of operation is selected by bit C/T2 in the SFR
T2CON. Timer 2 has three operating modes: capture, auto-reload (up or
down counting), and baud rate generator. The modes are selected by bits in
T2CON, as shown in Table 5.2. Timer 2 consists of two 8-bit registers, TH2
and TL2. In the Timer function, the TL2 register is incremented every
machine cycle. Since a machine cycle consists of 12 oscillator periods, the
count rate is 1/12 of the oscillator frequency.
Table 2.4 Timer 2 Operating Modes
In the Counter function, the register is incremented in response to a 1-
to-0 transition at its corresponding external input pin, T2. In this function, the
external input is sampled during S5P2 of every machine cycle. When the
samples show a high in one cycle and a low in the next cycle, the count is
incremented. The new count value appears in the register during S3P1 of the
cycle following the one in which the transition was detected. Since two
machine cycles (24 oscillator periods) are required to recognize a 1-to-0
transition, the maximum count rate is 1/24 of the oscillator frequency. To
ensure that a given level is sampled at least once before it changes, the
level should be held for at least one full machine cycle.
There are no restrictions on the duty cycle of external input signal, but
it should for at least one full machine to ensure that a given level is sampled
at least once before it changes.
Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON.
If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets
bit TF2 in T2CON.This bit can then be used to generate an interrupt. IfEXEN2
= 1, Timer 2 performs the same operation, but a 1-to-0 transition at external
input T2EX also causes the current value in TH2 and TL2 to be captured into
RCAP2H andRCAP2L, respectively. In addition, the transition at T2EXcauses
bit EXF2 in T2CON to be set. The EXF2 bit, likeTF2, can generate an interrupt.
Auto-reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when configured in
its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down
Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the
DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is
set, Timer 2 can count up or down, depending on the value of the T2EX pin.
Table2.5: T2MOD-Timer 2 Mode Control Register
Table2.6: T2CON-Timer/Counter2 Control Register
2.5 Interrupts
The AT89C52 has a total of six interrupt vectors: two external
interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and
the serial port interrupt. These interrupts are all shown in Figure 2.5
Figure 2.5 Interrupts source
Each of these interrupt sources can be individually enabled or disabled
by setting or clearing a bit in Special Function Register IE. IE also contains a
global disable bit, EA, which disables all interrupts at once.
Note that Table 5.3 shows that bit position IE.6 is unimplemented. In
the AT89C51, bit position IE.5 is also unimplemented. User software should
not write 1s to these bit positions, since they may be used in future AT89
products.
Table 2.7 Interrupts Enable Register
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in
register T2CON. Neither of these flags is cleared by hardware when the
service routine is vectored to. In fact, the service routine may have to
determine whether it was TF2 or EXF2 that generated the interrupt, and that
bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the
cycle in which the timers overflow. The values are then polled by the
circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and
is polled in the same cycle in which the timer overflows.
2.6 Special function registers:
Special function registers are the areas of memory that control specific
functionality of the 89c52 microcontroller.
a) Accumulator (0E0h)
As its name suggests, it is used to accumulate the results of large no.
of instructions. It can hold 8 bit values.
b) B register (oFoh)
The B register is very similar to accumulator. It may hold 8-bit value.
The B register is only used by MUL AB and DIV AB instructions. In MUL AB the
higher byte of the products gets stored in B register. In DIV AB the quotient
gets stored in B with the remainder in A.
c) Stack pointer (081h)
The stack pointer holds 8-bit value. This is used to indicate where the
next value to be removed from the stack should be taken from. When a
value is to be pushed on to the stack, the 8052 first store the value of SP and
then store the value at the resulting memory location. When a value is to be
popped from the stack, the 8052 returns the value from the memory location
indicated by SP and then decrements the value of SP.
d) Data pointer (Data pointer low/high, address 82/83h)
The SFRs DPL and DPH work together to represent a 16-bit value called
the data pointer. The data pointer is used in operations regarding external
RAM and some instructions code memory. It is a 16-bit SFR and also an
addressable SFR.
e) Program counter
The program counter is a 16 bit register, which contains the 2 byte
address, which tells the next instruction to execute to be found in memory.
When the 8052 is initialized PC starts at 0000h and is incremented each time
an instruction is executes. It is not addressable SFR.
f) PCON (power control, 87h)
The power control SFR is used to control the 8052’s power control
modes. Certain operation modes of the 8052 allow the 8052 to go into a type
of “sleep mode” which consumes low power.
g)TCON(Timer control, 88h)
The timer mode control SFR is used to configure and modify the way in
which the 8052’s two timers operate. This SFR controls whether each of the
two timers is running or stopped and contains a flag to indicate that each
timer has overflowed. Additionally, some non-timer related bits are located in
TCON SER. These bits are used to configure the way in which the external
interrupt flags are activated, which are set when an external interrupt occur.
h)TMOD(Timer Mode,89h)
The timer mode SFR is used to configure the mode of operation of each
of the two timers. Using this SR your program may configure each timer to
be a 16-bit timer, or 13 bit timer, 8-bit auto reload timer, or two separate
timers. Additionally you may configure the timers to only count when an
external pin is activated or to count “events” that are indicated on an
external pin.
SMOD ---- --- ---- GF1 GF0
PD IDL
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TIMER1 TIMER0
i) T0 (Timer 0 low/ high, address 8A/ 8C h)
These two SFRs together represent timer 0. Their exact behavior
depends on how the timer is configured in the TMOD SFR; however, these
timers always count up. What is configurable is how and when they
increment value.
j) T1 (Timer 1 low/ high, address 8B/ 8D h)
These two SFRs together represent timer 1. Their exact behavior
depends on how the timer is configured in the TMOD SFR; however, these
timers always count up. What is configurable is how and when they
increment in value.
k) P0 (Port 0, address 80h, bit addressable)
This is port 0 latch. Each bit of this SFR corresponds to one of the pins
on a micro controller. Any data to be outputted to port 0 is first written on P0
register. For e.g., bit 0 of port 0 is pin P0.0, bit 7 is pin P0.7. Writing a value
of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to low level.
l) P1(Port 1, address 90h, bit addressable)
This is port 1 latch. Each bit of this SFR corresponds to one of the pins
on a micro controller. Any data to be outputted to port 1 is first written on P1
register. For e.g., bit 0 of port 1 is pin P1.0, bit 7 is pin P1.7. Writing a value
of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to low level.
Gate C/ T M1 M0 Gate
C/ T M1 M0
m) P2 (Port 2, address 0A0h, bit addressable)
This is port 2 latch. Each bit of this SFR corresponds to one of the pins
on a micro controller. Any data to be outputted to port 2 is first written on P2
register. For e.g., bit 0 of port 2 is pin P2.0, bit 7 is pin P2.7. Writing a value
of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to low level.
n) P3 (Port 3, address 0B0h, bit addressable)
This is port 3 latch. Each bit of this SFR corresponds to one of the pins
on a micro controller. Any data to be outputted to port 3 is first written on P3
register. For e.g., bit 0 of port 3 is pin P3.0, bit 7 is pin P3.7. Writing a value
of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to low level.
o) IE (Interrupt Enable, 0A8h)
The interrupt enable SFR is used to enable and disable specific
interrupts. The low 7 bits of the SFR are used to enable/disable the specific
interrupts, where the MSB bit is used to enable or disable all the interrupts.
Thus, if the high bit of IE 0 all interrupts are disabled regardless of whether
an individual interrupt is enabled by setting a lower bit.
EA _ _ _
ET2 ES ET1 EX1 ET0 EX0
p) IP (Interrupt Priority, 0B8h)
The interrupt priority SFR is used to specify the relative priority of each
interrupt. On 8052, an interrupt may be either low or high priority. An
interrupt may interrupt interrupts. For e.g., if we configure all interrupts as
low priority other than serial interrupt. The serial interrupt always interrupts
the system; even if another interrupt is currently executing no other
interrupt will be able to interrupt the serial interrupt routine since the serial
interrupt routine has the highest priority.
_ _ _ _ _ _ PT2 PS PT1 PX1 PT0 PX0
q)PSW (Program Status Word, 0D0h)
The Program Status Word is used to store a number of important bits
that are set and cleared by 8052 instructions. The PSW SFR contains the
carry flag, the auxiliary carry flag, the parity flag and the overflow flag.
Additionally, it also contains the register bank select flags, which are used to
select, which of the “R” register banks currently in use.
CY AC F0 RS1 RS0 OV - - - - P
r) SBUF (Serial Buffer, 99h)
SBUF is used to hold data in serial communication. It is physically two
registers. One is writing only and is used to hold data to be transmitted out
of 8052 via TXD. The other is read only and holds received data from
external sources via RXD. Both mutually exclusive registers use address 99h.
2.7 Memory Organization
The total memory of 89C52 system is logically divided in Program
memory and Data memory. Program memory stores the programs to be
executed, while data memory stores the data like intermediate results,
variables and constants required for the execution of the program. Program
memory is invariably implemented using EPROM, because it stores only
program code which is to be executed and thus it need not be written into.
However, the data memory may be read from or written to and thus it is
implemented using RAM.
Further, the program memory and data memory both may be
categorized as on-chip (internal) and external memory, depending upon
whether the memory physically exists on the chip or it is externally
interfaced. The 89C52 can address 8Kbytes on-chip memory whose map
starts from 0000H and ends at 1FFFH. It can address 64Kbytes of external
program memory under the control of PSEN (low) signal.
The AT89C52 implements 256 bytes of on-chip RAM. The upper 128
bytes occupy a parallel address space to the Special Function Registers. That
means the upper 128bytes have the same addresses as the SFR space but
are physically separate from SFR space. When an instruction accesses an
internal location above address 7FH, the address mode used in the
instruction specifies whether the CPU accesses the upper 128 bytes of RAM
or the SFR space. Instructions that use direct addressing access SFR space.
For example, the following direct addressing instruction accesses the SFR at
location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper128 bytes
of RAM. For example, the following indirect addressing instruction, where R0
contains 0A0H, accesses the data byte at address 0A0H, rather than P2
(whose address is 0A0H)
.MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper
128 bytes of data RAM are available as stack space.
7. REGULATED POWER SUPPLY
7.1 Description:
A variable regulated power supply, also called a variable bench
power supply, is one where you can continuously adjust the output voltage
to your requirements. Varying the output of the power supply is the
recommended way to test a project after having double checked parts
placement against circuit drawings and the parts placement guide. This type
of regulation is ideal for having a simple variable bench power supply.
Actually this is quite important because one of the first projects a hobbyist
should undertake is the construction of a variable regulated power supply.
While a dedicated supply is quite handy e.g. 5V or 12V, it's much handier to
have a variable supply on hand, especially for testing. Most digital logic
circuits and processors need a 5 volt power supply. To use these parts we
need to build a regulated 5 volt source. Usually you start with an unregulated
power supply ranging from 9 volts to 24 volts DC (A 12 volt power supply is
included with the Beginner Kit and the Microcontroller Beginner Kit.). To
make a 5 volt power supply, we use a LM7805 voltage regulator IC .