3G-08-CellSearch

8/6/2019 3G-08-CellSearch

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Wireless Information Transmission System Lab.

National Sun Yat-sen University Institute of Communications Engineering

Initial Synchronization



2

ContentsIntroduction and Over-sampling

Downlink Synchronization -- Cell Search

Correlator

Parallel Matched Filter

Detail considerations in designing cell search.

Serial and Parallel Matched Filter

Frequency Offset

Coherent vs. Non-coherent Detection

Implement of Square Root CircuitNoise Effect and Multi-path Signals.

Uplink Synchronization -- PRACH Preamble Detection





Introduction and Over-sampling



4

Sampling TheoremSampling Theorem: A bandlimited signal having no

spectral components above f m hertz can be determined

uniquely by values sampled at uniform intervals of T sseconds, where

In sample-and-hold operation, a switch and storage

mechanism form a sequence of samples of thecontinuous input waveform. The output of the sampling

process is called pulse amplitude modulation (PAM).

mS f

T 2

1≤

mS f f 2ratesamplingor≥



5

Sampling Theorem

∑∞

−∞=

−=∗=n

S

S

S nf f X

T

f X f X f X )(1

)()()( δ



6

Spectra for Various Sampling Rates





8

Initial SynchronizationTo establish initial synchronization between BS and

MS.

At the receiving end, there is often a over-samplingprocedure, which takes several samples per chip.

Depending on the over-sampling rate, the accuracy of

initial synchronization is within ±1/(2·over-sampling

rate).

Determination of over-sampling rate is a trade off

between performance and hardware cost.

Under most of the conditions, over-sampling rate is

chosen among 2, 4, and 8.



9

Over-sampling of a sinc Function (I)

-6 -4 -2 0 2 4 6-0.4

-0.2

0

0.2

0.4

0.6

0.8

1Oversampling Rate = 2

T

s i n c

Max(Sample)=0.90032



10

Over-sampling of a sinc Function (II)

-6 -4 -2 0 2 4 6-0.4

-0.2

0

0.2

0.4

0.6

0.8

1Oversampling Rate = 4

T

s i n c

Max(Sample)=0.97450



11

Over-sampling of a Raised Cosine (I)

-6 -4 -2 0 2 4 6-0.4

-0.2

0

0.2

0.4

0.6

0.8

1Oversampling Rate = 2; Beta = 0.22;

T

r a i s e d c

o s i n e

Max(Sample)=0.89017



12

Over-sampling of a Raised Cosine (II)

-6 -4 -2 0 2 4 6-0.4

-0.2

0

0.2

0.4

0.6

0.8

1Oversampling Rate = 4; Beta = 0.22;

T

r a i s e d c

o s i n e

Max(Sample)=0.97174



13

Over-sampling of a Raised Cosine (III)

-5 0 5-0.2

0

0.2

0.4

0.6

0.8

OS Rate = 2; Beta = 0.50;

T

r a i s e d c o s

i n e

Max=0.84883

-5 0 5-0.2

0

0.2

0.4

0.6

0.8


T

r a i s e d c o s

i n e

Max=0.96034

-5 0 5-0.2

0

0.2

0.4

0.6

0.8


T

r a i s e d c o s i n e

Max=0.70711

-5 0 5-0.2

0

0.2

0.4

0.6

0.8


T

r a i s e d c o s i n e

Max=0.91876





Downlink Initial SynchronizationCell Search



15

Structure of Synchronisation Channel

(SCH)

One 10 ms SCH radio frame

256 chips

2560 chips

SecondarySCH acsi,0 acs

i,1 acsi,14

PrimarySCH acp acp acp

Slot #0 Slot #1 Slot #14



16

Cell Search ProceduresDuring the cell search, the UE searches for a cell and

determines the downlink scrambling code and framesynchronisation of that cell. The cell search is

typically carried out in three steps:

1. Slot synchronization

2. Frame synchronization/code-group identification

3. Scrambling-code identification



17

Synchronization Channel and Common

Pilot Channel for Cell SearchFirst step of cell search uses primary synchronization (P-SCH).

Second step of cell search uses secondary synchronization (S-

SCH).Third step of cell search uses common pilot channel (CPICH).

P-SCH

One Frame (10 ms)One Slot (0.67 ms, 2560 chips)

256 chips (0.067 ms)

S-SCH

CPICH



18

Slot SynchronizationDuring the first step of the cell search procedure theUE uses the SCH’s primary synchronisation code to

acquire slot synchronisation to a cell.In 3GPP W-CDMA, Primary SCH is the same forevery BS

At each slot beginning, P-SCH codes of 256 aretransmitted and then turned off until the next slot.

A matched filter could be used to match the codesuch that the strongest path from a certain BS could

be captured.Due to path propagation loss, the strongest path usuallycomes from the nearest BS.



19

Primary Synchronization CodesPrimary SYN code (PSC), Cpsc

Constructed as a so called generalised hierarchical Golay

sequence.

Good aperiodic auto-correlation properties.

Define a = < x1, x2, x3, …, x16> = <1, 1, 1, 1, 1, 1, -1, -1, 1, -1, 1,

-1, 1, -1, -1, 1>

PSC, Cpsc = (1 + j) × <a, a, a, -a, -a, a, -a, -a, a, a, a, -a, a, -a,

a, a>,

The leftmost chip in the sequence corresponds to the chip transmitted

first in time





Correlator



21

Structure of Correlator

90o carrier

cos(2πft)

sin(2πft)

H*(f)

H*(f)

Received∑

=

N

n 1( )2

∑=

N

n 1( )2

an(k )Sample

Correlator

90o

sin(2πft)

H*(f)H*(f)

H*(f)H*(f)

Received

Signal

∑=

N

n 1( )2∑

=

N

n 1( )2

Threshold

Detection

Samples are taken atover-sampling rate.

S

Read code coefficient

at chip rate.

Correlation is done

at chip rate.



22

Over-sampling Rate.Delay Line and Correlator Bank

1·Tc/2

2·Tc/2

3·Tc/2.

.

.

.

(N-1)·Tc/2

C1(t-Tc/2)

C1(t-2Tc/2)

C1(t-3Tc/2)

∑C1(t-(N-1)Tc/2)

C1(t)

Received Signals

D e l a y L i n e

Local PN Code

.

.

.

.

.

.

.

.

.

.

.

.

Output

i=0

i=1

i=2

i=3

i=N-1

S

∑

∑

∑

∑



23

Operation of Correlator BankExample:

Over-sampling rate : 2.

Received signals after over-sampling:

PN code or Synchronization code: C1, C2, C3, …, C256.

Searching window : 2560 chips.

Note that, we need 2560·2=5120 correlators for a over-sampling rate of 2 and searching window of 2560 chips. If

we consider both I and Q, the number of correlators isdoubled.

Of course, if hardware re-use is applied, number of correlators needed can be reduced.

1 2 1 2 1 2 1 2

1 1 2 2 3 3, , , , , ,..., , ,... .i ir r r r r r r r etc



24

Operation of Correlator Bank

2561

2559

1

i i

i

c r +=

⋅∑

2561

0

1

i i

i

c r +=

⋅∑

2562

2559

1

i i

i

c r +=

⋅∑

Received signals after over-sampling.

●

●

●

2562

0

1

i i

i

c r +=

⋅∑

● ● ● C1C2C256

28152 28151 25602 25601 22 21 12 112562 2561

● ● ● C1

C2

C256

● ● ● C1

C2

C256

● ● ● C1

C2

C256

51192

cT ⋅

51182

cT ⋅

12

cT

⋅

02

cT ⋅

Code Delay





Parallel Matched Filter



26

Structure of Parallel Matched Filter

∑Output

Tapped Delay Line

Code Coefficient

Received

Signals



27

Operation of Parallel Matched Filter

Example:




Searching window : 2560 chips.

Note that we need only one matched filter of tap length 256

to search virtually infinite large time window.

1 2 1 2 1 2 1 2

1 1 2 2 3 3, , , , , ,..., , ,... .i ir r r r r r r r etc



28


∑

● ● ●

C 2

1

2r 2

3r

C 3

1

3r 2

255r

C 255

1

255r 2

256r

C 256

1

256r

● ● ●

Output

Over-sampled

signals

Time = 0

2561

0

1

i i

i

c r +=

⋅∑

2

1r

C 1

1

1r 2

2r



29


∑

● ● ●

C 2

2

2r 1

4r

C 3

2

3r 1

256r

C 255

2

255r 1

257r

C 256

2

256r

● ● ●

Output

Over-sampled

signals

Time = 1·Tc/2

1

2r

C 1

2

1r 1

3r

2562

0

1

i i

i

c r +=

⋅∑



30


∑

● ● ●

C 2

1

2561r 2

2562r

C 3

1

2562r 2

2814r

C 255

1

2814r 2

2815r

C 256

1

2815r

● ● ●

Output

Over-sampled

signals

Time = 5118·Tc/2

2

2560r

C 1

1

2560r 2

2561r

2561

2559

1

i i

i

c r +=

⋅∑





32


2561

2559

1

i i

i

c r +=

⋅∑

256 1

0

1

i i

i

c r +=

⋅∑

2562

2559

1

i i

i

c r +=

⋅∑


●

●

●

2562

0

1

i i

i

c r +=

⋅∑

● ● ● C1C2C256

28152 28151 25602 25601 22 21 12 112562 2561

● ● ● C1

C2

C256

● ● ● C1

C2

C256

● ● ● C1

C2

C256

51192

cT ⋅

51182

cT ⋅

12

cT

⋅

02

cT ⋅

Time of output.



33

Adder Tree of Matched Filter

m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 ma mb mc md me mf

<5,4,t>

<6,5,t>

<7,6,t>

<8,7,t>

<9,8,t>

C l B k P ll l M h d



34

Correlator Bank vs. Parallel Matched

FilterThe number of correlators needed in a correlator bank is equal tothe number of chips, which corresponds to the length of the searchwindow, times the over-sampling rate.

The length of the matched filter tapped delay line equals to boththe accumulation time and the number of code chips.

The matched filter needs much more registers, multipliers, and

adders.Matched filter is adopted under most of the situations for coarsesynchronization.

Wireless Information Transmission System Lab





Detail Considerations in Designing CellSearch

P bl ith th 1 t St C ll



36

Problems with the 1st Stage Cell

SearchThere are a few problems with the 1st stage cell search

using matched filter:

Matched filter usually occupies a large area in the IC.Serial and Parallel Matched Filter

Frequency error due to low cost crystal oscillator (frequency

offset).Coherent vs. non-coherent detection.

Complexity of square root circuit.

Noise effect and multi-path signals.



37


∑

Output

tapped delay line

PN code coefficient

Parallel

Load

N-chip digital delay∑

tapped delay line

PN code coefficient

N-chip digital delay

Received

Signal

1 2 3 N

G.. J. R. Povey and P. M. Grant, “Simplified matched filter receiver designs forspread spectrum communications applications,” Electronics & Communication Engineering Journal, Apr. 1993



38


Example:


Matched filter tap length : 32 (N=32).



Note that N=32 implies that we would like to search for atime window of 32 chips.

We need to store the sampled data of 64 samples.

We need a 32-chip digital delay registers (64 data).

We need a matched filter of 32 taps in length.

1 2 1 2 1 2 1 2

1 1 2 2 3 3, , , , , ,..., , ,... .i i

r r r r r r r r etc



39


1

31r 1

32r 2

31r 2

1r

C 1C 31C 32

∑ 0

1

1r

2

32r

321

0

1

i i

i

c r +=

⋅∑

Received sample: 1-1

● ● ●

● ● ●

● ● ●

32 X 2

Length of matched filtertimes over-sampling rate.

0

Time = 0·Tc/2



40


1

33r 1

32r 2

31r 1

2r

C 1C 31C 32

∑32

2

0

1

i i

i

c r +=

⋅∑ 0

C 33

2

1r

2

32r

321

0

1

i i

i

c r +=

⋅∑


● ● ●

● ● ●

● ● ●

32 X 2

Time = 1·Tc/2



41


1

33r 1

32r 2

31r 1

2r

C 1C 31C 32

∑32

2

0

1

i i

i

c r +=

⋅∑ 0

C 33

2

2r

2

32r

321

1

1

i i

i

c r +=

⋅∑


● ● ●

● ● ●

● ● ●

32 X 2

Time = 2·Tc/2



42


2

32r 2

62r 1

61r 1

63r

C 1C 31C 32

∑32

2

29

1

i i

i

c r +=

⋅∑

2

63r

1

32r

321

31

1

i i

i

c r +=

⋅∑


C 63

● ● ●

● ● ●

● ● ●

32 X 2

C 62

0

Time = 62·Tc/2



43


1

33r 1

63r 2

62r 2

63r

C 1C 31C 32

∑32

1

31

1

i i

i

c r +=

⋅∑

C 33

1

64r

2

32r

322

31

1

i i

i

c r +=

⋅∑


C 64

● ● ●

● ● ●

● ● ●

32 X 2

321

0

1

i i

i

c r +=

⋅∑

C 63

Time = 63·Tc/2



44


2

33r 2

63r 1

63r 1

64r

C 33C 63C 64

∑32

2

31

1

i i

i

c r +=

⋅∑

2

64r

1

33r

641

0

1

i i

i

c r +=

⋅∑


● ● ●

● ● ●

● ● ●

32 X 2

322

0

1

i i

i

c r +=

⋅∑

32 641 1

1 33

i i i i

i i

c r c r = =

⋅ + ⋅∑ ∑

Time = 64·Tc/2



45


2

64r 2

94r 1

65r 1

95r

C 33C 63C 64

∑

2

95r

641

31

1

i i

i

c r +=

⋅∑


● ● ●

● ● ●

● ● ●

32 X 2

641

0

1

i i

i

c r +=

⋅∑

1

96r

642

31

1

i i

i

c r +=

⋅∑

C 65C 96 C 95

32 642 2

31 31

1 33

i i i i

i i

c r c r + += =

⋅ + ⋅∑ ∑

Time = 127·Tc/2



46


2

65r 2

95r 1

95r 1

96r

C 65C 95C 96

∑64

2

31

1

i i

i

c r +=

⋅∑

2

96r

1

65r

961

0

1

i i

i

c r +=

⋅∑


● ● ●

● ● ●

● ● ●

32 X 2

642

0

1

i i

i

c r +=

⋅∑

64 961 1

1 65

i i i i

i i

c r c r = =

⋅ + ⋅∑ ∑

Time = 128·Tc/2



47


2

256r

2

286r 1

257r 1

287r

C 225C 255C 256

∑

2

287r

2561

31

1

i i

i

c r +=

⋅∑


● ● ●

● ● ●

● ● ●

32 X 2

2561

0

1

i i

i

c r +=

⋅∑

1

288r

2562

31

1

i i

i

c r +=

⋅∑

Code Length Over-sampling Rate

Stop matching !!

Time = 511·Tc/2

06263



48


256

131

1

i i

i

c r +=

⋅∑

2561

0

1

i i

i

c r +=

⋅∑

2562

31

1

i i

i

c r +=

⋅∑


2872 2871 2862 2861 22 21 12 11

C1C2C256 ● ● ●

C1C2C256● ● ●

C1C2C256 ● ● ●

C1C2C256 ● ● ●

●

●

●

2562

01

i ii

c r +=

⋅

∑

2562 2561

Output read at

time = 511·Tc/2

0

1

62

63



49


The serial parallel matched filter is more flexible than theparallel matched filter.

The accumulation time can be much longer than the tappeddelayed line length.

The length of the N-chip digital delay equals to the length of the matched filter tapped delay line.

The PN code is shifted to the code tapped delay line. After Ncode chips are loaded, they are parallel loaded to the matchedfilter.

The input signal is loaded into the upper tapped delay line

continuously.The matched filter output results are accumulated in the N-chip digital delay.



50

Problems Due to Frequency Offset

Crystal oscillators at mobile terminal have inaccuracies in therange of 3-13 ppm, which gives rise to a frequency error in therange of 6-26 KHz when operated at 2 GHz.

1 ppm = 10-6 = one part per million.

An important goal for the MS is thus to reduce its frequency errorto a reasonable range during initial search so that furthercommunication functions can take place.

Non-coherent detection is adopted instead of coherent detection.

Wang, Y.-P. E., and Ottosson, T., “Cell Search in W-CDMA,＂

IEEE Journal on Selected Areas in Communications, pp. 1470-1482, Volume 18, Issue 8, August 2000.

System Model for Frequency Error



51

y q yDue to Imperfect Crystal Oscillator

Despread

c(t) n(t) θ π +t f j ee2

s(t)r(t)

)(t hr

xk

)(sin

)(sin12

2

2

ce

ce

N

yT f N

NT f SNR π

π

σ ⋅=

yk

Yi-Pin Eric Wang and Tony Ottosson, “Initial Frequency Acquisition In WCDMA”

VTC’99, pp 1013 - 1017

f e is equal to sum of frequency error and maximum Doppler shift.

Non-coherent Detection for



52

Frequency Error

0 100 200 300 400 500 600 700 800 900 10000

20

40

60

80

100

120

140

160

180SNR Under Different Frequency Error (Chip Rate = 3.84 Mcps)

N

N o r m a l i z e d S N R

fe = 5 KHz

fe = 10 KHz

fe = 20 KHz

Non-coherent Detection for 1st



53

Stage Cell Search

I/Q

Splitter

Matched

Filter

Non-coherent

Combiner

2 2

I Q+Peak

Detection

Matched

Filter

Non-coherent

Combiner

Received

Signals

A i i f S R Ci i



54

Approximation of Square Root Circuit

In practice, it is very difficult to implement the square root circuit.

A few approximations can be adopted for square root circuitry:

( ) ( )

2 21.

2.1

3. max , min ,2

where cossin

I Q

I Q

I Q I Q

I Q

θ θ

+

+

+ ⋅

∼∼

A i ti f S R t Ci it



55

Approximation of Square Root Circuit

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 10

0.5

1

1.5Approximation of Non-Coherent Detection

A m p l i t u d e

Radian (pi)

|sin| a=max(|sin|,|cos|)

|cos| b=min(|sin|,|cos|)

(sin)2+(cos)2

|sin|+|cos|

a+b/2a+(sqrt(2)-1)*b

max((a+b/8),(53a+37b)/64)

Sl t S h i ti



56

Slot Synchronization

To reduce the noise effect, slot-wise accumulator could be

used for accumulating the output power in several slots.

Slot timing is then acquired by finding the maximum peak of accumulator output within one observation interval.

One observation interval = slot period

Matched

filter (cp)

Slot-wise

accumulation

Two rays from BS i One ray from BS j

Find

maximum

Timing modulo Tslot

Tslot

Multipath

channel!!

Frame Synchronization and CodeG Id tifi ti



57

Group Identification

During the second step of the cell search procedure,

the UE uses the SCH’s secondary synchronisation

code to find frame synchronisation and identify the

code group of the cell found in the first step.

This is done by correlating the received signal with all

possible secondary synchronisation code sequences,

and identifying the maximum correlation value.

Secondary Synchronization Codes



58


16 codes: {C ssc,1,…,C ssc,16}

Complex-valued with identical real and imaginary

components.Constructed from position wise multiplication of a

Hadamard sequence and a sequence z

The Hadamard sequences are obtained as the rows in

a matrix H 8 constructed recursively by:

1

)1(

11

11

0

≥⎟⎟ ⎠

⎞⎜⎜⎝

⎛

−=

=

−−

−−k

H H

H H H

H

k k

k k

k

Rows are numbered

from the top (row): the

all ones sequence.




59

z = <b, b, b, -b, b, b, -b, -b, b, -b, b, -b, -b, -b, -b, -b>

b = < x1, x2, x3, x4, x5, x6, x7, x8, -x9, - x10, -x11, - x12, -x13, - x14,- x15, - x16>

The k-th SSC, C ssc,k , k = 1, 2, 3, …, 16

C ssc,k = (1 + j) × <hm(0) × z(0), hm(1) × z(1), hm(2) × z(2), …, hm(255) × z(255)>

m = 16×(k – 1)

C ssc,k (0) is the first transmitted chip in time.


Code Allocation of SSCs



60

Code Allocation of SSCs

The 64 secondary SCH sequences are constructed

such that their cyclic-shifts are unique.

A non-zero cyclic shift less than 15 of any of the 64

sequences is not equivalent to some cyclic shift of any

other of the 64 sequences.

Also, a non-zero cyclic shift less than 15 of any of the

sequences is not equivalent to itself with any other cyclic

shift less than 15.

Allocation of SSCs for secondary SCH



61





62


Frame Synchronization and CodeGroup Identification



63


After the receiver knows the slot timing in the first

step of cell search, the receiver can correlate the

received signal with 16 matched correlators.

Each matched to Secondary Synchronization codes.

However, the receiver has no knowledge about the

slot position in the frame and in what group.

Frame Synchronization and CodeGroup Identification



64

Solution: Exhaustive search for the slot position and

the sequence of S-SCH codes.

Accumulate these 16 output samples extensively slot-by-slot over all possible 960 combinations.

64 sequences and 15 slot positions.

Choose one from 960 candidates to determine the codegroup and frame timing of the chosen BS.

Since the cyclic shifts of the sequences are unique,the code group as well as the frame synchronisation

is determined.


Scrambling-code Identification



65

During the third and last step of the cell searchprocedure, the UE determines the exact primary

scrambling code used by the found cell.The primary scrambling code is typically identifiedthrough symbol-by-symbol correlation over the CPICHwith all codes within the code group identified in thesecond step.

Recall that 8 scrambling codes are in the derived code group.

After the primary scrambling code has been identified,

the Primary CCPCH can be detected. And the system-and cell specific BCH information can be read.

Scrambling code Identification

Serial Searching Procedure



66

Serial Searching Procedure

Stage 1 Stage 2 Stage 3 Stage 1 Stage 2 Stage 3

Failure

First Trial

……

Success

N-th TrialStart

Pipeline Searching Procedure



67

Pipeline Searching Procedure

Stage 1 Stage 1 Stage 1 Stage 1 Stage 1 Stage 1

Stage 2 Stage 2 Stage 2 Stage 2 Stage 2

Stage 3 Stage 3 Stage 3 Stage 3

Stage 3 rejects candidates. Stage 3 accepts candidates.





Uplink Initial SynchronizationPRACH Preamble Detection

Uplink PRACH Preamble Detection



69

The purpose of PRACH detection is to provide Node

B the information of incoming requests, as well as

the reference timing for delay estimation.The random-access transmission is based on a Slotted

ALOHA approach.

The UE can start the random-access transmission atthe beginning of a number of well-defined time

intervals, denoted access slots.

There are 15 access slots per two frames and they are

spaced 5120 chips apart.

p

Uplink RACH Access Slot Numbersand Their Spacing



70

p g

#0 #1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 #14

5120 chips

radio frame: 10 ms radio frame: 10 ms

Access slot

Random Access Transmission




Structure of the Random-AccessTransmission



71

Transmission

Message partPreamble

4096 chips10 ms (one radio frame)

Preamble Preamble

Message partPreamble

4096 chips 20 ms (two radio frames)

Preamble Preamble

The random-access transmission consists of oneor several preambles of length 4096 chips and amessage of length 10 ms or 20 ms.

RACH Preamble Code Construction



72

Each preamble is of length 4096 chips and consists of 256

repetitions of a signature of length 16 chips. There are a

maximum of 16 available signatures.

The random access preamble code C pre,n, is a complex valued

sequence.

It is built from a preamble scrambling code Sr-pre,n and a

preamble signature C sig,s as follows:

where k =0 corresponds to the chip transmitted first in time.

The modulation is performed by multiplying each chip of the RACH

preamble sequence with a rotating vector that takes the values (1,j,-1,-j)

4095,,2,1,0 ,)()()()

24(

,,,, …=××=+

− k ek C k Sk C k j

ssign prer sn pre

π π

PRACH Preamble Scrambling Code



73

g

The scrambling code for the PRACH preamble part is constructedfrom the long scrambling sequences.

There are 8192 PRACH preamble scrambling codes in total. The n:th

preamble scrambling code, n = 0, 1, …, 8191 , is defined as:Sr-pre,n(i ) = clong,1,n(i ), i = 0, 1, …, 4095;

The 8192 PRACH preamble scrambling codes are divided into512 groups with 16 codes in each group.

There is a one-to-one correspondence between the group of PRACH preamble scrambling codes in a cell and the primaryscrambling code used in the downlink of the cell.

The k :th PRACH preamble scrambling code within the cell withdownlink primary scrambling code m, k = 0, 1, 2, …, 15 and m= 0, 1, 2, …, 511, is Sr-pre,n(i) as defined above with n = 16×m +k .

PRACH Preamble Signature



74

g

The preamble signature corresponding to a signature s

consists of 256 repetitions of a length 16 signature Ps(n),

n=0…

15. This is defined as follows:

C sig,s(i) = Ps(i modulo 16) , i = 0, 1, …, 4095.

The signature Ps(n) is from the set of 16 Hadamard codes of

length 16.

PRACH Preamble Signature



75

1-1-11-111-1-111-11-1-11P15

(n)

-1-11111-1-111-1-1-1-111P14

(n)

-11-111-11-11-11-1-11-11P13

(n)

1111-1-1-1-1-1-1-1-11111P12

(n)

-111-1-111-11-1-111-1-11P11

(n)

11-1-111-1-1-1-111-1-111P10

(n)

1-11-11-11-1-11-11-11-11P9(n)

-1-1-1-1-1-1-1-111111111P8(n)

-111-11-1-11-111-11-1-11P7(n)

11-1-1-1-11111-1-1-1-111P6(n)

1-11-1-11-111-11-1-11-11P5(n)

-1-1-1-11111-1-1-1-11111P4(n)

1-1-111-1-111-1-111-1-11P3(n)

-1-111-1-111-1-111-1-111P2(n)

-11-11-11-11-11-11-11-11P1(n)

1111111111111111P0(n)

1514131211109876543210

Value of n PreambleSignature

PRACH Preamble Detection



76

…

…

…

…

…

…

…

…

SRRC

R(t)

( )2

( )2

t ω cos

t ω sin

cI

cI

cQ

cQ

yI

yQ

YI

YQ

SRRC

MF

MF

MF

MF

( )( )

I Q 4 2, , , ,c , c ( ) ( )

j k

pre n s r pre n sig sC k j S k C k e

π π +

−⎡ ⎤= = × ×⎣ ⎦




77

( )

( )4 2

, , , ,Transmitter: ( ) ( ) ( )

where or

At the receiving end, because of propagation delay,

cos sin

j k I Q

pre n s k k r pre n sig s

I Q I Q

k k k k

I Q I Q j

k k k k k

I Q

i i

C k c jc S k C k e

c a c c a c

r r jr c jc e

c c

π π

φ

φ

+

−= + = × ×

= = = = −

= + = + ⋅

= ⋅ − ⋅( ) ( )

( ) ( )

( )( ) ( )( )

( ) ( )

2 2

1 1

2 2

2 2

sin cos

At the output of matched filter:

cos sin cos sin

2

I Q

i i

N N I I Q I I Q Q Q

k k k k k k k k

k k

I Q

k k

j c c

r c r c r c r c

N c N c

Na Na a N

φ φ φ

φ φ φ φ

= =

+ ⋅ + ⋅

⎛ ⎞ ⎛ ⎞⋅ + ⋅ + ⋅ + ⋅⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠

= + + −

= + =

∑ ∑

i

PRACH Preamble Detection withPhase De-rotator



78

…

…

SRRC

R(t)

( )2

t ω cos

t ω sin

dI

yI

YI

…

…

SRRC ( )2

dQ

yQ

YQ

( )I Q 4

, ,d , d ( ) ( )

j

r pre n sig s j S k C k e

π

−⎡ ⎤

= × ×⎣ ⎦

The De-rotation Block



79

The de-rotation block performs the reverse operation

by multiplying each complex data sample with a

rotating vector that has the opposite phase (1,-j,-1,j).

Data I = Data I

Data Q = Data Q

Data I = Data Q

Data Q = - Data I

Data I = - Data I

Data Q = - Data Q

Data I = - Data Q

Data Q = Data I

……

……

Data i+0 Data i+1 Data i+2 Data i+3 ……




80

( )

( )

( )2 4 2

, ,Transmitter: , ( ) ( )

Note that .

After de-rotator, because of propagation delay,

cos sin sin cos

j k j k I Q

r pre n sig s

I Q

I Q I Q j

k k k k k

I Q I Q

i i i i

d jd e S k C k e

d d a

r r jr d jd e

d d j d d

π π π

φ

φ φ φ

⎛ ⎞+⎜ ⎟

⎝ ⎠−

⎡ ⎤ ⋅ = × ×⎣ ⎦

= = ±

= + = + ⋅

= ⋅ − ⋅ + ⋅ + ⋅( )

( ) ( )

( )( ) ( )( )

( ) ( )

2 2

1 1

2 2

2 2

At the output of matched filter:

cos sin sin cos

2

N N I I Q Q

k k k k

k k

I Q

k k

r d r d

N d N d

Na Na a N

φ

φ φ φ φ

= =

⎛ ⎞ ⎛ ⎞⋅ + ⋅⎜ ⎟ ⎜ ⎟

⎝ ⎠ ⎝ ⎠

= − + +

= + = ⋅

∑ ∑

Non-coherent Detection of PRACHPreamble



81

RACH Segment Detector 3




N o n - C o

h e r e n t

S u m m

a t i o n

D e

- r o t a t i o n

Matched Filter Length = 1024

Data Buffer = 1024 x Over-Sampling

Fixed Point



82

a0 a1 a2 a3 a4 a5 a15 a16 a17 a18a19 a20

Hadamard

Transform( 16 X 16 )

Delay

.

.

.

s0

s1

s15

.

.

.

| |2DSP

< 8,6,t > < 10,8,t > < 11,11,t > < 16,25,u >

Delay | |2

<10,12,t>

3G-08-CellSearch

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