354 33 Powerpoint-slides CH6

8/12/2019 354 33 Powerpoint-slides CH6

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N. Senthil Kumar,

M. Saravanan &

S. Jeevananthan

Oxford University Press 2013


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Interfacing MEMORY and

I/O devices WITH 8085



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Introduction

RAM,ROM,EPROM The programs and data which are executed by the

microprocessor have to be stored in ROM/EPROM andRAM which are basically semiconductor memory chips.

The programs and data which are stored in ROM/EPROMare not erased even-though the power supply to theROM/EPROM chip is removed.

Hence the ROM/EPROM are called non-volatile memory

and we can use them to store permanent programs suchas monitor program and data such as look up table,which are needed in microprocessor based systems.



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Difference

RAM,ROM,EPROM The difference between ROM and EPROM is that ROM

chip is programmable only one time whereas an EPROM

chip can be programmed many times after erasing thepreviously stored contents in it, by passing UV rays for

few minutes through the quartz window situated at the

top of the EPROM chip.

The programs and data which are stored in RAM areerased when the power supply to the RAM chip is

removed and hence RAM is called volatile memory.



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RAM - Introduction

Program and data which are often changed such asprogram written during the development process ofsoftware for a microprocessor based system, program

written during the learning of assembly languageprogramming and data entered while testing the aboveprograms, are stored in RAM.

RAM is also used to store data which are variable innature such as parameters entered by the user for aparticular operating condition, in a microprocessor basedsystem.



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Introduction contd..

Data can be only read from ROM or EPROM after

programming it whereas in RAM, data can be read or

written by the microprocessor.

In this chapter, the interfacing of EPROM and RAM chips

with 8085 using address decoders constructed using logic

gates and decoder IC such as 74LS138 are discussed.



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I/O Devices Input and Output (I/O) devices are needed in a

microprocessor based system to give inputs (programs

and data) to the system and to get the outputs (results of

the execution of a program) from the system

respectively.

Typical examples for the input devices are keyboard and

DIP switches and typical examples for the output devices

are LEDs, 7-segment LED and printer.



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I/O Interfacing Schemes There are two schemes namely

I/O mapped I/O and

memory mapped I/O to interface I/O devices with 8085.

In the I/O mapped I/O scheme, the I/O devices are

treated separately from memory.

In memory mapped I/O scheme, each I/O device is

treated as if it is a memory location.



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Interfacing memory

chips with 8085 8085 has 16 address lines namely (A15 to A0), a

maximum of 64Kbytes (=216) memory can be interfaced

with 8085 and the memory address space of 8085 (i.e.range of memory addresses that can be generated by8085) has the value from 0000H to FFFFH whenrepresented in hexadecimal form.

While executing a program stored in memory, the 8085

microprocessor needs to access memory regularly toread the instructions and data stored in memory and alsoto store the result to memory.



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Interfacing memory

chips with 8085contd..

The 8085 initiates a set of signals and when it wants to

read from and write into memory and the memory chip

has certain signals such as chip Enable or Chip Select, or

Output Enable or Read and or Write Enable or Write.

The memory interfacing circuit must match the above

8085ssignals with the memory chipssignals.



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Generation of control

signals for memory

Two control signals namely (Memory Read) and (Memory

Write)are generated for memory such that alone is at logic 0

during memory read operation from RAM or EPROM andalone is at logic 0 during memory write operation into RAM.



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Circuit used to generate

and signals



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Relation between 8085s control

signals and memory control signals

When the signal is at logic high level, both memory

control signals are deactivated (i.e. at logic high)

independent of the status of and signals which is

shown in the third row.



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Interfacing EPROM chip

with 8085

Pin Diagram of IC 2764

There are 8192 locations (8K=8x210 =8192)

in the IC 2764 and in each location, one

byte of information (instruction or data) isstored.

There are 13 address lines (Since 213 =8K)

namely A12 to A0 present in IC 2764 where

A0 is the least significant bit of the address

and A12 is the most significant bit of the

address.



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Steps to read content of

Memory Location In order to read the content of a memory location in

EPROM chip, the following steps are done

The address of the memory location from where data

has to be read is placed in the address lines of EPROM.

CE signal is made logic low (i.e. 0)

OE signal is made logic low(i.e. 0)

Now the data in the selected memory location will be

available in the data lines (D7-D0) of EPROM.



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Selection of memory location for

various values of address inputs in IC

2764

8085 has 16 address lines (A15-A0) and hence it can be interfacedwith maximum memory size of 64K bytes (= 216bytes)

The address range of the memory can vary from 0000H to FFFFH and

this is known as memory space of 8085



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Interfacing EPROM chip with

8085 using decoder IC

Whenever many number of same capacity memory chips

have to be interfaced with 8085, decoder IC with activelow outputs such as 74LS138 is very useful.

By using a single 74LS138 IC, maximum of eight memory

chips (RAM and EPROM) can be interfaced with 8085.



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Logic diagram of 74LS138

decoder IC



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Truth table of

74LS138 decoder IC



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Introduction - 74LS138

decoder IC 74LS138 decoder IC has three select inputs namely A (LSB), Band C (MSB) and three enable inputs namely G1,

G2 represents the two active low enable signals of 74LS138

namely and .

Only when G1=1 and = = 0, 74LS138 functions as decoder and

under that condition depending upon the value in the select

inputs, one of the outputs will be low (i.e. 0) as shown in table

6.6.

If either G1=0 or =1 or =1 then all of its outputs are 1,independent of the value in the select inputs.

In table 6.6, X represents dont care condition which means

the input can be either 0 or 1.

G2A



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Truth table for the 6264

IC (8K x 8) RAM chip



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Interfacing EPROM chips

using 74LS138 Decoder



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6264 IC (8K x 8) RAM chip



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Interfacing RAM chip with

8085 using logic gates

The interfacing of RAM chip with 8085 is same as that of

EPROM chip except that one more signal namely of 8085

is used.



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Partial address

decoding: In the methods so far discussed, the entire address bus

of 8085 (A15 to A0) is used to interface memory chipswith 8085 and this technique is called absolute address

decoding.

Using the absolute address decoding method, maximumof 64 Kbytes of memory can be interfaced with 8085.

There is another method known as partial address

decoding which is used when the amount of memoryneeded in an 8085 based system is less than 64 Kbytessuch as 8K or 16K or 32K.



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In the partial address decoding method, all the address

lines of 8085 are not used in interfacing with memory.

In the partial address decoding method, the lower order

address lines of 8085 are connected to the address lines

in memory chip same as in the absolute address

decoding method and some of the higher order address

lines of 8085 are left unconnected and only few higher

order lines of 8085 are connected to the chip enable

signal of memory through address decoder.



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Hence the size of the address decoder gets reduced and

sometimes the amount of hardware (number of gates)

needed for interfacing is reduced in the partial address

decoding method. At the same time for the same memory chip, different

address ranges will get assigned in the partial address

decoding method and any one of the address ranges can

be used to access the memory.



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I/O or Peripheral

mapped I/O In this method, the I/O devices are treated separately from memory.

The control signals I/O read ( ) and I/O write ( ) which are derivedfrom , and signals of 8085, are used to activate input device andoutput device respectively.

IN instruction and OUT instruction of 8085 are used to access theinput device and output device respectively.

Each I/O device is identified by a unique 8-bit address assigned to it.

Since 8-bit address is used for each I/O device, a maximum of 256(=28) input devices and a maximum of 256 (=28) output devices canbe interfaced with 8085 since the control signal used to access inputdevices and output devices are different.



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Generation of signals



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Status signals in 8085 Table shows the values in, and lines of 8085 during the

I/O read and I/O write operation and the correspondingvalues in the signals and during the above operations.



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Memory mapped I/O In memory mapped I/O, each input device or output

device is treated as if it is a memory location.

The control signal is used to activate the input device

and the control signal and is used to activate the output

device.

Each input or output device is identified by a unique 16-

bit address same as 16-bit memory address assigned to a

memory location.



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All the memory related instructions used to read data

from memory such as LDA 2000H, LDAX B and MOV A,M, etc. can be used to access input device and all thememory related instructions used to write data intomemory such as STA 3000H, STAX D and MOV M, A, etccan be used to send data to output device.

Since the I/O devices use some of the memory addressspace of 8085, the maximum memory capacity (EPROM& RAM capacity) will be less than 64K bytes in thismethod.



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Partial address decoding

the entire address bus of 8085, (i.e. A7 to A0 in I/O

mapped I/O scheme and A15 to A0 in memory mapped

I/O scheme) is used to interface I/O devices with 8085

and this technique is called absolute address decoding.

Partial address decoding can also be used in both the

schemes



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In this method, for a single I/O device there will be more

than one address and any one of them can be used to

access it. Here the address lines which are not used in the

interfacing are considered as dont care condition (i.e.

either 0 or 1) and then depending on the way the

remaining address lines are connected to the addressdecoder, the addresses assigned to the I/O device are

found out.



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Summary Any microprocessor based system need memory and I/O ports

to be interfaced with it.

8085 based systems need at least two memory chips to be

interfaced with it. One RAM and one ROM.

Memory map is important and should differentiate the

addresses for different memory chips in a system.

The memory can be interfaced with the processor using

address lines and data lines with the control signals from thedecoder and the processor.

The control signals , and play an important role in interfacing.



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Summary contd.. Address decoding is necessary to select a particular memory

chip in a system.

Chip selection is done using higher order address lines and canbe done in two ways Absolute address decoding and partial

address decoding.

Input and output devices also follow the same interfacing

concepts similar to memory chips.

Input and output devices such as switches and LEDs can beinterfaced to 8085 either using memory mapped addressing

or using peripheral mapped interfacing techniques.



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Key terms RAM Random Access Memory is a semiconductor

memory in which both read and write of data is possible.IC 6264 is a 8K RAM chip with 8bit words.

EPROM Erasable and Programmable Read Onlymemory is a semiconductor memory in which the datacan be programmed once and read many times.

In general, erasing of the data can be done by the user.

There are two types of erasing one by electrical meansand the other by using ultraviolet rays.

Control signals for reading from and writing to memory.



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Key terms contd.. Absolute Address Decoding Decoding technique in which all the bits of

address bus is used for accessing and decoding memory chips.

Partial Address Decoding Decoding technique in which all the addressbits are not used for decoding. Instead less number of address bits areused and some higher order bits are not used in decoding and selectionof memory locations.

Peripheral or I/O mapped I/O The technique by which the input andoutput devices are addressed using 8 bit I/O addresses and accessedusing IN and OUT instruction.

Memory mapped I/O The technique by which the input and outputdevices are addressed using 16 bit memory addresses and accessed likea memory location using memory access instructions like LDA, STA etc.


354 33 Powerpoint-slides CH6

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