1 Testing - Overview MotivationMotivation –fault models –testing methods Automatic Test Pattern Generation (ATPG) algorithmsAutomatic Test Pattern Generation.

1

Testing - OverviewTesting - Overview

• MotivationMotivation– fault modelsfault models– testing methodstesting methods

• Automatic Test Pattern Generation Automatic Test Pattern Generation (ATPG) algorithms(ATPG) algorithms– D-algorithmD-algorithm– PODEMPODEM– SocratesSocrates– SATSAT

2

Testing: Why?Testing: Why?• Testing is manufacture verificationTesting is manufacture verification

““Is what I manufactured what I designed?”Is what I manufactured what I designed?”

• Incorrect Operation (faults) occurs due to Incorrect Operation (faults) occurs due to physical defectsphysical defects– Logical faultsLogical faults

• shorts, missing transistors, …shorts, missing transistors, …

– Parametric faultsParametric faults• process variations, die anomalies, …process variations, die anomalies, …

• Faults may be intermittent or permanentFaults may be intermittent or permanent• Permanent faults may be created during life of Permanent faults may be created during life of

the circuitthe circuit– physical/thermal stressphysical/thermal stress– radiationradiation

3

Testing: Why?Testing: Why?

• No manufacturing process can guarantee 100% defect No manufacturing process can guarantee 100% defect free IC’sfree IC’s

• Larger the circuit, greater the probability of defects Larger the circuit, greater the probability of defects occuringoccuring

• EconomicsEconomics: Cost of detecting a faulty component is : Cost of detecting a faulty component is lowest before it is packaged and embedded in a system lowest before it is packaged and embedded in a system and shipped.and shipped.

Detection Detection (either during manufacture or during operation)(either during manufacture or during operation) of intermittent and permanent faults of intermittent and permanent faults

reliable circuitsreliable circuits

4

Fault Modeling and TestingFault Modeling and Testing

• Logical Fault Logical Fault – Single/multiple stuck-at Single/multiple stuck-at

(most used)(most used)– CMOS stuck-openCMOS stuck-open– CMOS stuck-onCMOS stuck-on– Bridging faultsBridging faults

• Parametric faultsParametric faults– low/high voltage/current low/high voltage/current

levelslevels– gate or path delay faultsgate or path delay faults

Parametric Parametric (electrical)(electrical) tests tests also detect stuck-on also detect stuck-on faultsfaults

Logical tests detect stuck-at Logical tests detect stuck-at faultsfaults

Transition tests detect Transition tests detect stuck-open faultsstuck-open faults

Timed transition tests Timed transition tests detect delay faultsdetect delay faults

A fault model is a model of how a physical or parametric A fault model is a model of how a physical or parametric fault manifests itself in the circuit. Operation. Fault tests fault manifests itself in the circuit. Operation. Fault tests are derived based on these modelsare derived based on these models

Faults Faults Tests Tests

5

Stuck-at fault test Stuck-at fault test generationgeneration

To generate a test for To generate a test for yy stuck-at 0, we need to stuck-at 0, we need to find an vector of primary inputs which sets find an vector of primary inputs which sets signal signal yy to 1 to 1 (justify)(justify) and such that and such that somesome primary output differs between the good primary output differs between the good circuit and the faulty circuit circuit and the faulty circuit (propagate)(propagate)

s-a-0s-a-0yPIPI POPOjustifyjustify

propagatepropagate

6

Fault ReductionsFault Reductions

Dominated faultDominated fault: If every test for fault : If every test for fault f1f1 detects detects f2 ,f2 , then then f1f1 dominates dominates f2 f2 .. only have to generate test for only have to generate test for f1f1

Set of faults required for testing is a Set of faults required for testing is a minimalminimal set set with respect to fault equivalence and with respect to fault equivalence and dominancedominance

s-a-0s-a-0 s-a-0s-a-0

fault equivalencefault equivalence

f1: s-a-1f1: s-a-1 f2: s-a-1f2: s-a-1

fault dominancefault dominance

7

Fault ReductionsFault ReductionsStuck fault checkpointsStuck fault checkpoints: [Davidson] [Kohavi, Kohavi]: [Davidson] [Kohavi, Kohavi]

Theorem:Theorem: In a combinational circuit, any set of tests In a combinational circuit, any set of tests which detects all single (multiple) stuck faults on which detects all single (multiple) stuck faults on 1.1. all primary inputs and all primary inputs and

2.2. all all branchesbranches of fanout points of fanout points ((including primary inputsincluding primary inputs),),

detects all single (multiple) stuck faults.detects all single (multiple) stuck faults.

The set of primary inputs and branches of fanout The set of primary inputs and branches of fanout points are called the points are called the checkpointscheckpoints of the circuit of the circuit ((i.e.i.e. checkpoints are the set of faults that are tested)checkpoints are the set of faults that are tested)

8

Checkpoints & fault Checkpoints & fault collapsing collapsing

Fault Fault collapsingcollapsing is the process of reducing the is the process of reducing the size of the set of faults to be tested, using size of the set of faults to be tested, using fault fault equivalenceequivalence and and fault dominancefault dominance on the on the checkpointscheckpoints of the circuit of the circuit

bbaa

cc

f1f1

f2f2

• xx shows checkpoints shows checkpoints (s-a-0 (s-a-0 and s-a-1 on each checkpoint)and s-a-1 on each checkpoint)

• f1 s-a-0 is equivalent to f2 s-a-f1 s-a-0 is equivalent to f2 s-a-0. Similarly for other faults.0. Similarly for other faults.

Exercise:Exercise: find minimal set of find minimal set of collapsedcollapsed faults for this circuit. faults for this circuit. Have to test all sites for both Have to test all sites for both s-a-0 and s-a-1.s-a-0 and s-a-1.

9

Test EffectivenessTest EffectivenessUndetectableUndetectable fault: No test exists for fault fault: No test exists for fault

RedundantRedundant fault: Undetectable fault fault: Undetectable fault butbut whose whose occurrence does not affect circuit operationoccurrence does not affect circuit operation

TestabilityTestability = ( = (#detectable faults)#detectable faults) / / #faults#faults

Effective Effective faultsfaults = faults\redundant faults = faults\redundant faults(These are the ones we must detect if we want to completely test (These are the ones we must detect if we want to completely test

the chip. Since redundant faults cause no harm, they should not the chip. Since redundant faults cause no harm, they should not be counted against us.)be counted against us.)

(This is a better measure of how well a piece of logic is tested by a (This is a better measure of how well a piece of logic is tested by a set of test vectors.)set of test vectors.)

|detectable faults|fault coverage =

|effective faults|

10

Test EffectivenessTest Effectiveness

Test set sizeTest set size = # of test vectors= # of test vectors

Goal:Goal: 100% fault coverage 100% fault coverage ((not 100% testabilitynot 100% testability))

with a with a minimumminimum sized test set sized test set

11

Logic Level Test Logic Level Test GenerationGeneration

Test generation in Test generation in combinationalcombinational circuits circuits– Satisfiability check on Boolean network Satisfiability check on Boolean network [Larrabee] [Larrabee]

[Stephan et al.][Stephan et al.]– ““Best” solution is SAT based approach Best” solution is SAT based approach ((Berkeley Berkeley

experience - not all test community agreesexperience - not all test community agrees))

Test generation in Test generation in sequentialsequential circuits circuits– understood only for stuck-at faultsunderstood only for stuck-at faults– tests are tests are sequencessequences of vectors of vectors– still still impracticalimpractical on large circuits ( > 30 latches) on large circuits ( > 30 latches)

12

Logic Level Test Logic Level Test GenerationGeneration

Convert testing of sequential circuits to testing Convert testing of sequential circuits to testing on combinational circuits by allowing access to on combinational circuits by allowing access to memory elements memory elements ( “scan design” )( “scan design” )– 10-20% area overhead10-20% area overhead– 10% performance penalty10% performance penalty

All combinational test generation algorithms All combinational test generation algorithms reduce to reduce to SATSAT solve SAT problem efficientlysolve SAT problem efficiently

13

Combinational test pattern Combinational test pattern generation - Heuristicgeneration - Heuristic

Structural search methods:Structural search methods: perform search on Boolean perform search on Boolean space using space using topologytopology of of the circuit as guide.the circuit as guide.– D-algorithm [Roth ‘66]D-algorithm [Roth ‘66]– PODEM [Goel ‘81]PODEM [Goel ‘81]– FAN [Fujiwara, Shimono FAN [Fujiwara, Shimono

‘83]‘83]– Socrates [Schulz et al. ‘88]Socrates [Schulz et al. ‘88]

SAT based methods:SAT based methods:– [Larrabee 89][Larrabee 89]– [Stephan 91][Stephan 91]

Symbolic and algebraic Symbolic and algebraic methods:methods: Abstract Abstract formulation formulation (conceptually (conceptually elegant but practically elegant but practically infeasible)infeasible)– ENF [Armstrong ‘66]ENF [Armstrong ‘66]– Boolean differences [Sellers Boolean differences [Sellers

et al. ‘68]et al. ‘68]

14

D-AlgorithmD-Algorithm

Use Use 5-valued logic5-valued logic for logic value in good (true) for logic value in good (true) and faulty circuit. Implies only one circuit is and faulty circuit. Implies only one circuit is necessary.necessary.– 0 0 0 in true circuit, 0 in faulty circuit 0 in true circuit, 0 in faulty circuit– 1 1 1 in true circuit, 1 in faulty circuit 1 in true circuit, 1 in faulty circuit– DD 1 in true circuit, 0 in faulty circuit 1 in true circuit, 0 in faulty circuit– DD 0 in true circuit, 1 in faulty circuit 0 in true circuit, 1 in faulty circuit– XX unknown value in either true or faulty circuit unknown value in either true or faulty circuit

GoalGoal: Find an assignment to primary inputs that : Find an assignment to primary inputs that causes a causes a DD or or DD at at somesome primary output primary output

15

D-Algorithm CalculusD-Algorithm Calculus

B=~AA B0 11 0X XD ~D

~D D

C=A&BA\B 0 1 X D ~D0 0 0 0 0 01 0 1 X D ~DX 0 X X X XD 0 D X D 0

~D 0 ~D X 0 ~D

16

D-Algorithm exampleD-Algorithm example

aa

bb

cc

dd

eeii

jj

s-a-0s-a-01111

XXXX 00

XXXX

00

00

00

DDDD

Test is abcde = xx110Test is abcde = xx110

17

D-AlgorithmD-Algorithm

• At fault location, determine what value must At fault location, determine what value must exist exist (e.g. for a s-a-0 fault, a D is required)(e.g. for a s-a-0 fault, a D is required)

• Assign each internal line of the circuit a value Assign each internal line of the circuit a value (0,1,D,D,X) which is consistent under some (0,1,D,D,X) which is consistent under some primary input vector. A test exists if such a primary input vector. A test exists if such a vector is found vector is found (with at least one D or D at an (with at least one D or D at an output),output), otherwise the fault cannot be tested otherwise the fault cannot be tested ((redundantredundant).).

NoteNote: Given : Given nn ( (internalinternal) lines, 2) lines, 2nn values need to values need to enumerated in the worst caseenumerated in the worst case

18

End of lecture 16End of lecture 16

19

D-Algorithm: Decision TreeD-Algorithm: Decision Tree

Search performed level by level from Search performed level by level from PO’sPO’s to PI’s to PI’s

startstart

k=1k=1

l l =1=1

i=0,j=1i=0,j=1i=1,j=0i=1,j=0

g=0,h=0g=0,h=0

a=0,b=1a=0,b=1 a=1,b=0a=1,b=0

c=1,d=1c=1,d=1

g=1,h=1g=1,h=1

c=0,d=0c=0,d=0

““backtracking”backtracking”

20

D-algorithm ProblemD-algorithm Problem

Note thatNote that k k and and ll are complementary signals. are complementary signals.

Assume Assume k k =1, =1, l l =1 is chosen as assignment by D-algorithm. =1 is chosen as assignment by D-algorithm.

It takes several other assignments before D-algorithm determines It takes several other assignments before D-algorithm determines this is inconsistent.this is inconsistent.

SolutionSolution: Backtrack only on PI values to determine consistency of : Backtrack only on PI values to determine consistency of signalssignals

aabb

ccdd

eeff

ii

jj

gg

hh

kk

nn

ll

mm

21

Implicit Search Implicit Search Enumeration: PODEMEnumeration: PODEM

Actual space of consistent assignments is only Actual space of consistent assignments is only 22nn, where , where nn is the number of primary inputsis the number of primary inputs

Hence, search space can be greatly reduced Hence, search space can be greatly reduced ((compared to D-algorithmcompared to D-algorithm) by enumerating ) by enumerating over primary inputs onlyover primary inputs only

PODEM (PODEM (Path oriented decision makingPath oriented decision making) is such ) is such an algorithman algorithm

22

PODEM Decision TreePODEM Decision Treestartstart

PIPI11=0=0

(All PI’s initially (All PI’s initially unassignedunassigned))

(unused alternative assignment)(unused alternative assignment)

(no remaining alternative)(no remaining alternative)

PIPI11=1=1

PIPI22=0=0

(unused alternative (unused alternative assignment)assignment)

PIPI22=1=1

PIPI33=0=0PIPI33=1=1

PIPI44=1=1PIPI44=0=0

PIPI55=1=1 PIPI55=0=0

PIPI44=1=1PIPI44=0=0

(conflict: (conflict: no test)no test)

(conflict: (conflict: no test)no test)

(no remaining alternative)(no remaining alternative)

(conflict: (conflict: no test)no test)

(conflict: (conflict: no test)no test)

indicates no remaining alternative at nodeindicates no remaining alternative at node

23

PODEM: AlgorithmPODEM: Algorithm

1.1. Start with given fault, empty decision tree, all PI’s Start with given fault, empty decision tree, all PI’s set to set to XX

2.2. 3 types of operations performed3 types of operations performeda)a) check if current PI assignment is check if current PI assignment is consistentconsistent. If so, . If so,

choose an unassigned PI and set it to 0 or 1choose an unassigned PI and set it to 0 or 1

b)b) If inconsistent and if alternative value of currently If inconsistent and if alternative value of currently assigned PI has not been tried, try it and mark this PI as assigned PI has not been tried, try it and mark this PI as having having no remaining alternativeno remaining alternative

c)c) If no remaining alternative on this PI, If no remaining alternative on this PI, backupbackup to previous to previous PI that was assigned, deleting the decision tree belowPI that was assigned, deleting the decision tree below

Algorithm complete: either terminates with a test Algorithm complete: either terminates with a test (all PI’s assigned)(all PI’s assigned) or proves fault is redundant or proves fault is redundant

24

PODEM: HeuristicsPODEM: Heuristics

Choosing which PI to assign Choosing which PI to assign nextnext– This depends on how the fault could This depends on how the fault could propagatepropagate to a to a

primary outputprimary output– Choose “Choose “closestclosest” PO to which fault can propagate and ” PO to which fault can propagate and

determine which PI affects the propagation “determine which PI affects the propagation “the mostthe most””– This is done by computing approximate node This is done by computing approximate node

controllabilitiescontrollabilities and and observabilitiesobservabilities

Heuristic is quite Heuristic is quite ad-hocad-hoc. .

PODEM is PODEM is ineffectiveineffective on large networks with a lot on large networks with a lot of of reconvergencereconvergence

25

SocratesSocrates

Provides improvements to PODEMProvides improvements to PODEM– implicationsimplications– static and dynamic learningstatic and dynamic learning

Basic IdeaBasic Idea– When a value is set on a node When a value is set on a node (due to current partial (due to current partial

PI assignment)PI assignment) what conclusions can be made? what conclusions can be made?• Values on other nodes/PI’sValues on other nodes/PI’s

This allows detection of This allows detection of inconsistenciesinconsistencies, thereby causing , thereby causing early backtrackingearly backtracking

26

ImplicationsImplications

Implications are computed in Implications are computed in pre-processingpre-processing phase and phase and stored for use during backtracking and assignment stored for use during backtracking and assignment phase of algorithmphase of algorithm

aa

cc

bb dd

eeff

a = 1 a = 1 (d = 1) & (e = 1) (d = 1) & (e = 1) f = 1 f = 1

Hence, f = 0 Hence, f = 0 a = 0 a = 0

27

Static and Dynamic Static and Dynamic LearningLearning

If a has a D value and it must propagate through g, d must be set to 1. If If a has a D value and it must propagate through g, d must be set to 1. If it can’t be, then D on a can’t propagate.it can’t be, then D on a can’t propagate.– This is an implication learned from the This is an implication learned from the topologytopology of the network of the network

a = D a = D d = 1d = 1 • Static learning:Static learning: implications learned in pre-processing phase implications learned in pre-processing phase• Dynamic learning:Dynamic learning: implications learned under partial PI assignments implications learned under partial PI assignments

aa

bb

cc

g g (dominator)(dominator)

dd

28

Socrates: AlgorithmSocrates: Algorithm1.1. Perform implication of each Perform implication of each singlesingle lead value and store lead value and store

informationinformation

2.2. Given a fault, determine implied values by Given a fault, determine implied values by static learningstatic learning

3.3. Use PODEM and determine implied values using Use PODEM and determine implied values using dynamic dynamic learninglearning

Heuristic used to determine when to “learn” Heuristic used to determine when to “learn” 1.1. (e.g. don’t learn implications which are trivial or already (e.g. don’t learn implications which are trivial or already

known from previous steps)known from previous steps)

Socrates completely subsumed by SAT procedure Socrates completely subsumed by SAT procedure ((P.R. P.R. Stephan, R.K. Brayton and A. Sangiovanni-Vincentelli, Stephan, R.K. Brayton and A. Sangiovanni-Vincentelli, “Combinational Test Generation Using Satisfiability,” IEEE TCAD, “Combinational Test Generation Using Satisfiability,” IEEE TCAD, Nov. 1992Nov. 1992))

29

Boolean Network Boolean Network SatisfiabilitySatisfiability

Problem:Problem: Given a Boolean network, find a satisfying Given a Boolean network, find a satisfying assignment to the primary inputs that makes at least assignment to the primary inputs that makes at least primary output have value 1.primary output have value 1.

Applications:Applications: Test pattern generationTest pattern generation– CombinationalCombinational– Sequential Sequential – Delay faultsDelay faults

Timing analysisTiming analysis

Hazard detectionHazard detection

In general, SAT is a good alternative to BDD’s if In general, SAT is a good alternative to BDD’s if • only one solutiononly one solution is needed or is needed or • a a canonicalcanonical form is not useful form is not useful

Image computationImage computationLow powerLow power

30

SAT OutlineSAT Outline

• Method of Boolean DifferencesMethod of Boolean Differences• Formulation as SAT problemFormulation as SAT problem• Solving SAT problemsSolving SAT problems• Greedy, Dynamic Variable OrderingGreedy, Dynamic Variable Ordering• Experimental ResultsExperimental Results• SAT conclusionsSAT conclusions

31

Combinational Test Combinational Test GenerationGeneration

• Structural search methodsStructural search methods ( (most widely usedmost widely used))– D-algorithm [Roth 66]D-algorithm [Roth 66]– PODEM [Goel 81]PODEM [Goel 81]– FAN [Fujiwara, Shimono 83]FAN [Fujiwara, Shimono 83]– Socrates [Schulz et al. 88]Socrates [Schulz et al. 88]

• Symbolic & algebraic methodsSymbolic & algebraic methods ( (not practicalnot practical))– Poage’s Method, [Poage 63]Poage’s Method, [Poage 63]– ENF [Armstrong 66] (equivalent normal form)ENF [Armstrong 66] (equivalent normal form)– Boolean differences [Sellers et al. 68]Boolean differences [Sellers et al. 68]

• Hybrid ApproachHybrid Approach– SAT-based, [Larrabee 89], [Stephan 92]SAT-based, [Larrabee 89], [Stephan 92]

32

Boolean DifferencesBoolean DifferencesGeneral Case:General Case: Let Let F(X)F(X) be the global function of a network with one be the global function of a network with one

primary output, primary output, X X = {= {xx11,…,x,…,xn n } the primary inputs, and let } the primary inputs, and let FFz z ( X )( X ) be be the output of the network modified by a fault the output of the network modified by a fault zz. Then. Then

TTzz = F = Fzz F F

characterizes characterizes allall tests for fault tests for fault zz. In some cases, we can build this as . In some cases, we can build this as a BDD.a BDD.

Stuck-at Faults:Stuck-at Faults: Let Let g(X)g(X) be the global function at any intermediate be the global function at any intermediate node. Rewrite node. Rewrite FF as as F(X,g)F(X,g). Then. Then

TT00 = [F(X,0) = [F(X,0) F(X,1)] g(X) F(X,1)] g(X)

TT11 = [F(X,0) = [F(X,0) F(X,1)] g(X) F(X,1)] g(X)

characterizes all tests for characterizes all tests for gg s-a-0s-a-0, , g g s-a-1s-a-1 respectively. respectively. F(X,0) F(X,0) F(X,1) F(X,1)

is the is the Boolean DifferenceBoolean Difference of of FF with respect to with respect to gg..

Solve Solve TT0 0 ,T,T11 algebraically [Sellers et al.] algebraically [Sellers et al.]

~~

~~

~~ ~~

~~

~~~~~~

33

Conjunctive Normal FormConjunctive Normal FormConsider Consider TT00 in a circuit representation: in a circuit representation:

Express network Express network TT00 in CNF using characteristic function of each gate. in CNF using characteristic function of each gate.

• ExampleExample: : a a ==x yx y– F F = (= (x + y + a x + y + a )()(x + a x + a )()(y + a y + a ))

– Conjunction over all gates describes Conjunction over all gates describes TT00

Add clause with only one literal (Add clause with only one literal (TT0 0 ) to the CNF for the circuit. This ) to the CNF for the circuit. This says that we want to find an input where says that we want to find an input where TT00 = 1, i.e. a test for the = 1, i.e. a test for the fault. Since the entire formula is in CNF, problem is fault. Since the entire formula is in CNF, problem is SATISFIABLITYSATISFIABLITY..

FF

FF zz

TT00

34

SatisfiabilitySatisfiabilityThe The originaloriginal NP-complete problem NP-complete problem

InstanceInstance: A set of variables : A set of variables UU and a collection of and a collection of clauses, clauses, CC, over , over U.U.

QuestionQuestion: Is there a satisfying truth assignment for : Is there a satisfying truth assignment for C C ??

Cook’s Theorem (1971):Cook’s Theorem (1971): SAT is NP-complete SAT is NP-complete (See (See Garey & Johnson, 1979)Garey & Johnson, 1979)Still NP-complete if:Still NP-complete if:

cc CC | |c c | = 3 (| = 3 (3-SAT3-SAT))

uu UU at most 3 clauses contain at most 3 clauses contain uu or or ~u~u

Polynomial (Polynomial (linearlinear) if:) if:cc CC | |cc| | 2 ( 2 (2-SAT2-SAT))

35

SAT vs. TautologySAT vs. TautologyDuality:Duality:

SATSAT non-Tautologynon-TautologyCNF, product of sumsCNF, product of sums DNF, sum of productsDNF, sum of productsIs expression ever true?Is expression ever true? Is expression ever false? Is expression ever false? null clause: always falsenull clause: always false universal cube: always trueuniversal cube: always trueassign variable xassign variable x cofactor with respect to xcofactor with respect to xbacktrack if null clausebacktrack if null clause backtrack if universal cubebacktrack if universal cubeunate: easy to satisfyunate: easy to satisfy unate: trivial tautology testunate: trivial tautology test

Why not just use Espresso?Why not just use Espresso?

Unate recursive paradigm for tautology is inefficient for Unate recursive paradigm for tautology is inefficient for formulas derived from gate-level characteristic functions.formulas derived from gate-level characteristic functions.

• Extremely binate cubes, few literalsExtremely binate cubes, few literals• Experiments with Espresso confirm thisExperiments with Espresso confirm this

36

Implication GraphImplication Graph• View 2-clauses as pair of implicationsView 2-clauses as pair of implications

– (a + ~b) (a + ~b) (~a (~a ~b) ~b) (b (b a) a)– forms forms implication graphimplication graph

• Strongly-connected components Strongly-connected components (SCCs)(SCCs) are equivalent are equivalent variables variables (inverters, buffers)(inverters, buffers)

• More complex equivalences More complex equivalences notnot detected. detected. – ExampleExample: symmetry vs. SCC: symmetry vs. SCC

aa bb~a

a

b

~b

• (~a+~b+c)(a+~c)(b+~c)(~a+~b+c)(a+~c)(b+~c)(~a+~b+e)(a+~e)(b+~e)(~a+~b+e)(a+~e)(b+~e)(~c+~d)(c+d)(~c+~d)(c+d)

cc ddaa

bb ee~d

d

c

~c~a

~b~e

a

be

37

Non-local ImplicationsNon-local Implications

(~a + ~b + x)(a + ~x)(b + ~x)(~a + ~b + x)(a + ~x)(b + ~x)

(~b+ ~c + y)(b + ~y)(c + ~y)(~b+ ~c + y)(b + ~y)(c + ~y)

(x + y + ~f)(~x + f)(~y + f)(x + y + ~f)(~x + f)(~y + f)

1.1. Find Find non-localnon-local implications for b: implications for b:– Try asserting (~b)Try asserting (~b)– (b + ~x) (b + ~x) (~x), and (b + ~y) (~x), and (b + ~y) (~y) (~y)– (x + y + ~f) (x + y + ~f) (~f) (~f)– Thus, (~b) Thus, (~b) (~f), so deduce (f) (~f), so deduce (f) (b) (b)

2.2. If contradiction, (e.g. f If contradiction, (e.g. f ~f) fix to other constant (e.g. f=0) ~f) fix to other constant (e.g. f=0)

3.3. Repeat for every formula variableRepeat for every formula variable

Crucial for hard faults Crucial for hard faults (esp. redundancies, where no test exists)(esp. redundancies, where no test exists)

bb

cc

aa xx

yyff

38

Active ClausesActive ClausesProblemProblem: Good/faulty circuits related only at : Good/faulty circuits related only at I/OsI/Os, slow to find , slow to find

contradictionscontradictions

SolutionSolution: : activeactive clauses define relationships for internal nodes clauses define relationships for internal nodes (Larrabee 1990)(Larrabee 1990)

• Active variable Active variable xxaa is true if net is true if net xx differs in good and faulty network. differs in good and faulty network.

Here, Here, xxgg refers to signal refers to signal xx in good circuit and in good circuit and xxff to to xx in the faulty in the faulty

circuit:circuit:

(~(~xxaa + + xxgg + + xxf f )(~)(~xxaa + ~ + ~xxgg + ~ + ~xxf f ))• If gate is active, we require that some fanout must be activeIf gate is active, we require that some fanout must be active

xx

yy

zz

(~xa + ya + za)

39

Example FormulaExample Formula

Good circuitGood circuit (32 literals): (32 literals):(a + x)(b + x)(~x + ~a ~b)(a + x)(b + x)(~x + ~a ~b)(~a + g)(~x + g)(~g + a + x)(~a + g)(~x + g)(~g + a + x)(x + z)(x + z)(~x + ~z)(~x + ~z)(~z + h)(~y + h)(~h + z +y)(~z + h)(~y + h)(~h + z +y)(b + ~y)(c + ~y)(y +~b + ~c)(b + ~y)(c + ~y)(y +~b + ~c)

Faulty circuitFaulty circuit (18 literals): (18 literals):(~a + g(~a + gff)(~x)(~xff + g + gff)(~g)(~gff + a + x + a + xff))(x(xff + z + zff)(~x)(~xff + ~z + ~zff))(~z(~zff + h + hff))(~y(~yff + h + hff)(~h)(~hff + z + zff +y +yff))

Active clauseActive clause (29 literals): (29 literals):(~x(~xaa + x +x + x +xff)(~x)(~xaa + ~x + ~x + ~x + ~xff))(~z(~zaa + z + z + z + zff)(~z)(~zaa + ~z + ~z + ~z + ~zff))(~g(~gaa + g + g + g + gff)(~g)(~gaa + ~g + ~g + ~g + ~gff))(~h(~haa + h + h + h + hff)(~h)(~haa + ~h + ~h + ~h + ~hff))(~x(~xaa + z + zaa + g + gaa)(~z)(~zaa + h + haa))

Fault siteFault site (3 literals) (3 literals) & Goal& Goal (2 literals) (2 literals)(x)(~x(x)(~xff)(x)(xaa)()(ggaa + + hhaa))

aa

bb

cc hh

gg

zz

yy

s-a-0s-a-0

xx

40

Search StrategiesSearch Strategies

• Use a basic Use a basic branch-and-boundbranch-and-bound approach approach

• four basic parametersfour basic parameters

solution areassolution areas

unidentified non-unidentified non-solution areassolution areas

identified non-identified non-solution areassolution areas

1. initial assignment1. initial assignment

2. variable order2. variable order

3. Dynamic processing 3. Dynamic processing at each branch pointat each branch point

4. How long to search?4. How long to search?

41

Orthogonal StrategiesOrthogonal Strategies

• In In theorytheory, any complete algorithm will find a test , any complete algorithm will find a test for every fault, if one exists.for every fault, if one exists.

• In In practicepractice, we cannot afford to wait for the , we cannot afford to wait for the worst case.worst case.

Compromise:Compromise: try several strategies in succession try several strategies in succession for a short time (backtrack limit)for a short time (backtrack limit)– improves average performanceimproves average performance– increases robustnessincreases robustness– has difficulty with “hard” redundancieshas difficulty with “hard” redundancies

• Two strategies which complement each other Two strategies which complement each other are called are called orthogonalorthogonal

42

Static Variable OrderingStatic Variable Ordering

Larrabee’s heuristics (Larrabee’s heuristics (LSATLSAT))– Add clauses for structural heuristics Add clauses for structural heuristics (dominators, (dominators,

critical paths, etc.)critical paths, etc.)– static variable orderingstatic variable ordering– three search strategiesthree search strategies– static non-local implications static non-local implications (after all faults have (after all faults have

been tried without them)been tried without them)

• No results reported No results reported withoutwithout random patterns random patterns

Implemented as Implemented as command in command in

43

Benchmark NetworksBenchmark Networks

• MCNCMCNC Test Generation Test Generation BenchmarksBenchmarks

• Full scanFull scan assumed for assumed for sequential networkssequential networks

Network PI PO Gates FaultsC432 36 7 159 413C499 41 32 370 850C880 60 26 320 703C1355 41 32 506 1058C1908 33 25 441 1102C2670 233 140 734 1678C3540 50 22 961 2177C5315 178 123 1473 3798C6288 32 32 2384 4835C7552 207 108 2164 4901S1494 14 25 577 1220S5378 214 213 1149 2850S9234 247 250 2264 465S13207 700 790 3287 7068S15850 611 684 4057 8340S35932 1763 2048 12236 28222S38417 1664 1742 10232 21113S38584 1464 1730 11774 26008Total 121029

44

Larrabee’s HeuricticsLarrabee’s Heurictics

WithWith random tests random tests

(seconds | # aborts)(seconds | # aborts)

WithoutWithout random tests random tests

(seconds | # aborts)(seconds | # aborts)

Ckt. LSAT SocratesC499 72 0 4.9 0C880 49 0 5.2 0C1355 99 0 13.9 0C1908 184 0 33.8 0C2670 479 0 57.5 0C3540 607 0 56.6 0C5315 464 0 31.3 0C6288 227 0 87.0 0C7552 2052 0 248.0 0

Ckt. LSAT SocratesC499 5240 3 29 0C880 1730 0 10 0C1355 9540 1 44 0C1908 31000 53 81 0C2670 8600 3 80 0C3540 110000 64 159 0C5315 56000 145 102 0C6288 980000 4506 139 0C7552 270000 197 418 0

45

Greedy HeuristicsGreedy Heuristics• Heuristics must be evaluated Heuristics must be evaluated withoutwithout using random using random

teststests• Static variable ordering is not effectiveStatic variable ordering is not effective• Dynamic ordering can require too much computation Dynamic ordering can require too much computation

at each branch of the searchat each branch of the search

SolutionSolution: greedy, dynamic orderings. : greedy, dynamic orderings.

At each branch point, select:At each branch point, select:– 1st1st literal in literal in 1st1st unsatisfied clause unsatisfied clause– lastlast literal in literal in 1st1st unsatisfied clause unsatisfied clause– 1st1st literal in literal in lastlast unsatisfied clause unsatisfied clause– lastlast literal in literal in lastlast unsatisfied clause unsatisfied clause

ResultsResults: improved performance and robustness: improved performance and robustness

46

AlgorithmAlgorithmFor each uncaught fault:For each uncaught fault:

extract CNF formulaextract CNF formulatry 4 greedy strategiestry 4 greedy strategiesif all fail thenif all fail then

find static NLI (non local implications)find static NLI (non local implications)repeat 4 strategiesrepeat 4 strategies

endifendifif satisfied thenif satisfied then

fault simulate test (to see what other faults are caught)fault simulate test (to see what other faults are caught)elseelse

flag possible redundant faultflag possible redundant faultendifendif

Simple algorithm:Simple algorithm:– no testability measuresno testability measures– no 5,9-valued algebrasno 5,9-valued algebras– no multiple backtrackingno multiple backtracking

Standalone program Standalone program TEGUSTEGUS (also in (also in sis 1.1sis 1.1, but slower by 1-2 orders of magnitude), but slower by 1-2 orders of magnitude)

47

ExperimentsExperiments• Theoretical worst case performance is same Theoretical worst case performance is same

for all complete for all complete algorithms algorithms• Heuristics must be evaluated by experimentHeuristics must be evaluated by experiment• To compare heuristics:To compare heuristics:

– use the 10 ISCAS’85 benchmark networks and 8 use the 10 ISCAS’85 benchmark networks and 8 larger ISCAS’89 networks (larger ISCAS’89 networks (assuming full scanassuming full scan))

– Run on Run on samesame model computer as other reported model computer as other reported results with same optionsresults with same options

– Compare Compare CPUCPU time (not backtracks) time (not backtracks)– Try Try withwith and and withoutwithout random tests random tests

48

TEGUS Base ResultsTEGUS Base Results

• RobustRobust: 0 aborted faults in ISCAS’85/’89 : 0 aborted faults in ISCAS’85/’89 networks without fault simulationnetworks without fault simulation

• EfficientEfficient: for 18 ISCAS networks: for 18 ISCAS networks– no fault simulation: 10 min. total CPUno fault simulation: 10 min. total CPU**

75% extract, 25% SAT75% extract, 25% SAT– with random: 1 min. total CPUwith random: 1 min. total CPU**

55% extract, 20% fault sim, 15% SAT, 10% I/O55% extract, 20% fault sim, 15% SAT, 10% I/O10 MB peak memory10 MB peak memory

• SimpleSimple: 3k lines of code: 3k lines of code– 300 to extract CNF formula300 to extract CNF formula– 800 for SAT package800 for SAT package

**(DEC 3000/500)(DEC 3000/500)

49

RobustnessRobustness

Available results with Available results with no fault simulationno fault simulation for for ISCAS’85/’89 networksISCAS’85/’89 networks

• Algorithms with backtrack limits are Algorithms with backtrack limits are incompleteincomplete• Heuristics which abort on fewer faults are Heuristics which abort on fewer faults are more more

robustrobust

Algorithm# of Circuits

Aborted Faults

Normalized CPU Time

CHE88 7 798 1.6CHN89 9 1208 2.2JAC89 8 693 6.6GIR90 10 0 16.0ABR90 6 408 30.0RAJ90 10 1268 24.0GIR91 10 0 12.0TEGUS 18 0 1.0

50

EfficiencyEfficiencyAvailable results Available results with random testswith random tests for ISCAS’85/’89 networks for ISCAS’85/’89 networks

• See Tech Report UCB/ERL M92/112 or TCAD Sept. 96, Vol See Tech Report UCB/ERL M92/112 or TCAD Sept. 96, Vol 15, N0.9, 1167-117515, N0.9, 1167-1175

• Random tests Random tests maskmask effectiveness of deterministic effectiveness of deterministic algorithmalgorithm

Algorithm# of Circuits

Aborted Faults

Normalized CPU Time

SIM89 6 0 30.0SCH89 10 0 1.7MIN89 9 16 22.0LAR89 10 0 31.0JAC89 10 0 6.8SCH90 18 0 36.0WAI90 18 0 1.0MAH90 15 0 9.4CHK91 1 0 2900.0GIR91 10 0 25.0MAT92 18 0 0.9TEGUS 18 0 1.0

51

SAT ConclusionsSAT Conclusions

• Hybrid test generation algorithm extracts CNF Hybrid test generation algorithm extracts CNF formula for structural fault, and applies formula for structural fault, and applies generic generic SATSAT algorithm to generate a test algorithm to generate a test

• Greedy, dynamic orderingGreedy, dynamic ordering heuristics are as heuristics are as efficient as best published results for structural efficient as best published results for structural algorithmsalgorithms

• Heuristics must be carefully compared using real Heuristics must be carefully compared using real implementations and implementations and without random testswithout random tests

• Other fault modelsOther fault models and test restrictions can be and test restrictions can be accommodated without modifying the generic accommodated without modifying the generic SAT solverSAT solver