1. Study of OP AMPs - IC 741, IC 555, IC 565, IC 566, IC ...ece.gecgudlavalleru.ac.in/pdf/manuals/ICA-WITHOUTREADINGSMANU… · Short circuit protection 3. Offset voltage null capability

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

IC APPLICATIONS LABORATORY

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1. Study of OP AMPs - IC 741, IC 555, IC 565, IC 566,

IC 1496-functioning, parameters and specifications

IC 741

General Description

The IC 741 is a high performance monolithic operational amplifier constructed

using the planer epitaxial process. High common mode voltage range and absence

of latch-up tendencies make the IC 741 ideal for use as voltage follower. The high

gain and wide range of operating voltage provide superior performance in integrator,

summing amplifier and general feed back applications.

Internal Block Diagram of Op-Amp

Fig.1: Block diagram of op-amp

Pin Configuration

Fig.2: Pin diagram of IC741



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Features

1. No frequency compensation required.

2. Short circuit protection

3. Offset voltage null capability

4. Large common mode and differential voltage ranges

5. Low power consumption

6. No latch-up

Specifications

1. Voltage gain A = α typically 2,00,000

2. I/P resistance RL = α Ω, practically 2MΩ

3. O/P resistance R =0, practically 75Ω

4. Bandwidth = α Hz. It can be operated at any frequency

5. Common mode rejection ratio = α

(Ability of op amp to reject noise voltage)

6. Slew rate + α V/µsec

(Rate of change of O/P voltage)

7. When V1 = V2, VD=0

8. Input offset voltage (Rs ≤ 10KΩ) max 6 mv

9. Input offset current = max 200nA

10. Input bias current : 500nA

11. Input capacitance : typical value 1.4pF

12. Offset voltage adjustment range : ± 15mV

13. Input voltage range : ± 13V

14. Supply voltage rejection ratio : 150 µV/V

15. Output voltage swing: + 13V and – 13V for RL > 2KΩ

16. Output short-circuit current: 25mA

17. supply current: 28mA

18. Power consumption: 85mW

19. Transient response: rise time= 0.3 µs

Overshoot= 5%

Applications

1. AC and DC amplifiers

2. Active filters

3. Oscillators

4. Comparators

5. Regulators



3

IC 555

General Description

The operation of SE/NE 555 timer directly depends on its internal function.

The three equal resistors R1, R2, R3 serve as internal voltage divider for the source

voltage. Thus one-third of the source voltage VCC appears across each resistor.

Comparator is basically an Op amp which changes state when one of its

inputs exceeds the reference voltage. The reference voltage for the lower

comparator is +1/3 VCC. If a trigger pulse applied at the negative input of this

comparator drops below +1/3 VCC, it causes a change in state. The upper comparator

is referenced at voltage +2/3 VCC. The output of each comparator is fed to the input

terminals of a flip flop.

The flip-flop used in the SE/NE 555 timer IC is a bistable multivibrator. This

flip flop changes states according to the voltage value of its input. Thus if the voltage

at the threshold terminal rises above +2/3 VCC, it causes upper comparator to cause

flip-flop to change its states. On the other hand, if the trigger voltage falls below +1/3

VCC, it causes lower comparator to change its states. Thus the output of the flip flop

is controlled by the voltages of the two comparators. A change in state occurs when

the threshold voltage rises above +2/3 VCC or when the trigger voltage drops below

+1/3 Vcc.

The output of the flip-flop is used to drive the discharge transistor and the

output stage. A high or positive flip-flop output turns on both the discharge transistor

and the output stage. The discharge transistor becomes conductive and behaves as

a low resistance short circuit to ground. The output stage behaves similarly. When

the flip-flop output assumes the low or zero states reverse action takes place i.e., the

discharge transistor behaves as an open circuit or positive VCC state. Thus the

operational state of the discharge transistor and the output stage depends on the

voltage applied to the threshold and the trigger input terminals.



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Block Diagram of IC 555

Fig.3: Block diagram of IC 555

Pin Configuration


Function of Various Pins

Pin (1) of 555 is the ground terminal; all the voltages are measured with respect to

this pin.

Pin (2) of 555 is the trigger terminal, if the voltage at this terminal is held greater than

one-third of VCC, the output remains low. A negative going pulse from Vcc to less than



5

Vec/3 triggers the output goes to High. The amplitude of the pulse should be able to

make the comparator (inside the IC) change its state. However the width of the

negative going pulse must not be greater than the width of the expected output pulse.

Pin (3) is the output terminal of IC 555. There are 2 possible output states. In the

low output state, the output resistance appearing at pin (3) is very low (approximately

10 Ω). As a result the output current will goes to zero , if the load is connected from

Pin (3) to ground , sink a current I Sink (depending upon load) if the load is connected

from Pin (3) to ground, and sinks zero current if the load is connected between +VCC

and Pin (3).

Pin (4) is the Reset terminal. When unused it is connected to +Vcc. Whenever the

potential of Pin (4) is drives below 0.4V, the output is immediately forced to low state.

The reset terminal enables the timer over-ride command signals at Pin (2) of the IC.

Pin (5) is the Control Voltage terminal. This can be used to alter the reference levels

at which the time comparators change state. A resistor connected from Pin (5) to

ground can do the job. Normally 0.01µF capacitor is connected from Pin (5) to

ground. This capacitor bypasses supply noise and does not allow it affect the

threshold voltages.

Pin (6) is the threshold terminal. In both astable as well as monostable modes, a

capacitor is connected from Pin (6) to ground. Pin (6) monitors the voltage across

the capacitor when it charges from the supply and forces the already high O/p to Low

when the capacitor reaches +2/3 VCC.

Pin (7) is the discharge terminal. It presents an almost open circuit when the output

is high and allows the capacitor charge from the supply through an external resistor

and presents an almost short circuit when the output is low.

Pin (8) is the +Vcc terminal. 555 can operate at any supply voltage from +3 to +18V.

Features

1. The load can be connected to o/p in two ways i.e. between pin 3 & ground 1 or

between pin 3 & VCC (supply)

2. 555 can be reset by applying negative pulse, otherwise reset can be connected

to +Vcc to avoid false triggering.

3. An external voltage effects threshold and trigger voltages.

4. Timing from micro seconds through hours.

5. Monostable and bistable operation

6. Adjustable duty cycle



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7. Output compatible with CMOS, DTL, TTL

8. High current output sink or source 200mA

9. High temperature stability

10. Trigger and reset inputs are logic compatible.

Specifications

1. Operating temperature : SE 555-- -55oC to 125oC

NE 555-- 0o to 70oC

2. Supply voltage : +5V to +18V

3. Timing : µSec to Hours

4. Sink current : 200mA

5. Temperature stability : 50 PPM/oC change in temp or 0-005% /oC.

Applications

1. Monostable and Astable Multivibrators

2. dc-ac converters

3. Digital logic probes

4. Waveform generators

5. Analog frequency meters

6. Tachometers

7. Temperature measurement and control

8. Infrared transmitters

9. Regulator & Taxi gas alarms etc.

IC 565

General Description

The Signetics SE/NE 560 series is monolithic phase locked loops. The SE/NE 560,

561, 562, 564, 565, & 567 differ mainly in operating frequency range, power supply

requirements and frequency and bandwidth adjustment ranges. The device is

available as 14 Pin DIP package and as 10-pin metal can package. Phase

comparator or phase detector compare the frequency of input signal fs with frequency

of VCO output fo and it generates a signal which is function of difference between the

phase of input signal and phase of feedback signal which is basically a d.c voltage

mixed with high frequency noise. LPF remove high frequency noise voltage. Output

is error voltage. If control voltage of VCO is 0, then frequency is center frequency (fo)

and mode is free running mode. Application of control voltage shifts the output



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frequency of VCO from fo to f. On application of error voltage, difference between fs

& f tends to decrease and VCO is said to be locked. While in locked condition, the

PLL tracks the changes of frequency of input signal.

Block Diagram of IC 565

Fig.5: Block Diagram of IC 565

Pin Configuration

Fig.6: Pin diagram of IC 565



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Specifications

1. Operating frequency range : 0.001 Hz to 500 KHz

2. Operating voltage range : ±6 to ±12V

3. Inputs level required for tracking : 10mV rms minimum to 3v (p-p)

max.

4. Input impedance : 10 KΩ typically

5. Output sink current : 1mA typically

6. Drift in VCO center frequency : 300 PPM/oC typically

(fout) with temperature

7. Drif in VCO centre frequency with : 1.5%/V maximum

supply voltage

8. Triangle wave amplitude : typically 2.4 VPP at ± 6V

9. Square wave amplitude : typically 5.4 VPP at ± 6V

10. Output source current : 10mA typically

11. Bandwidth adjustment range : <±1 to >± 60%

Center frequency fout = 1.2/4R1C1 Hz

= free running frequency

FL = ± 8 fout/V Hz

V = (+V) – (-V)

fc = ± ] 2/1

3210)6.3(2

Π xCx

f L

Applications

1. Frequency multiplier

2. Frequency shift keying (FSK) demodulator

3. FM detector

IC 566

General Description

The NE/SE 566 Function Generator is a voltage controlled oscillator of

exceptional linearity with buffered square wave and triangle wave outputs. The

frequency of oscillation is determined by an external resistor and capacitor and the

voltage applied to the control terminal. The oscillator can be programmed over a ten

to one frequency range by proper selection of an external resistance and modulated

over a ten to one range by the control voltage with exceptional linearity.



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Block Diagram of IC566

Fig.7: Block diagram of IC566

Pin diagram

Fig.8 : Pin diagram of IC566

Specifications

Maximum operating Voltage --- 26V

Input voltage --- 3V (P-P)

Storage Temperature --- -65oC to + 150oC

Operating temperature --- 0oC to +70oC for NE 566

-55oC to +125oC for SE 566

Power dissipation --- 300mv



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Applications

1. Tone generators.

2. Frequency shift keying

3. FM Modulators

4. clock generators

5. signal generators

6. Function generator

IC 1496

General Description

IC balanced mixers are widely used in receiver IC’s. The IC versions are

usually described as balanced modulators. Typical example of balanced IC

modulator is MC1496. The circuit consists of a standard differential amplifier (formed

by Q5 _ Q6 combination) driving a quad differential amplifier composed of transistor

Q1 – Q4. The modulating signal is applied to the standard differential amplifier

(between terminals 1 and 4). The standard differential amplifier acts as a voltage to

current converter. It produces a current proportional to the modulating signal. Q7 and

Q8 are constant current sources for the differential amplifier Q5 – Q6. The lower

differential amplifier has its emitters connected to the package pins ( 2 & 3) so that an

external emitter resistance may be used. Also external load resistors are employed

at the device output (6 and 12 pins).The output collectors are cross-coupled so that

full wave balanced multiplication takes place. As a result, the output voltage is a

constant times the product of the two input signals.

Schematic of IC1496




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Pin Configuration

Fig.10 : Pin diagram of IC1496

Applications of MC 1496

• Balanced modulator

• AM Modulator

• Product Modulator

• AM Detector

• Mixer

• Frequency Doublers.



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2. OP AMP Applications – Adder, Subtractor,

Comparator Circuits

Aim: To design Adder, Subtractor and Comparator circuits by using operational

amplifier.

Apparatus required

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer page no 2 1

2 Resistor 1kΩ 4

3 Diode 0A79 2

4 Regulated Power supply (0 – 30V),1A 2

5 Function Generator (.1 – 1MHz), 20V p-p 1

6 Cathode Ray Oscilloscope (0 – 20MHz) 1

7 Multimeter 3 ½

digit display 1

Theory

Adder: A two input summing amplifier may be constructed using non-inverting

mode or inverting mode. The gain of this summing amplifier is 1 as all the resistors

are equal in value; any scaling factor can be obtained by selecting proper external

resistors.

Subtractor: A basic differential amplifier can be used as a subtractor as shown in

fig.3. In this circuit all external resistors are equal in value. Hence the gain of

amplifier is equal to one. The output voltage Vo is equal to the difference voltage

between the non-inverting terminal and the inverting terminal; hence the circuit is

called a subtractor.

Comparator: The circuit diagram shows an op-amp used as a comparator. A

fixed reference voltage Vref is applied to the one terminal and the varying signal

voltage Vin is applied to the other terminal. Depending upon the application of Vin to

the terminal this can be non inverting or inverting, if input Vin is connected to the non

inverting terminal of the op-amp then it is called as non- inverting comparator as vice

versa. Depending upon the levels of Vin and Vref, the circuit produces output +Vsat or

-Vsat



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Circuit Diagrams

Adder:

Fig. 1: Non- inverting Adder

Fig. 2: Inverting Adder



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Subtractor

Fig. 3: Subtractor

Comparator

Fig. 4: Non-inverting Comparator

Fig. 5: Inverting Comparator



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Designing & Model Calculations

Adder

Non-inverting

Vo = (V1 + V2)

If V1 = 2.5V and V2 = 2.5V, then

Vo = (2.5+2.5) = 5V.

Inverting

Vo = - (V1 + V2)

If V1 = 2.5V and V2 = 2.5V, then

Vo = - (2.5+2.5) = -5V.

Subtractor

Vo = V2 – V1

If V1=2.5 and V2 = 3.3, then

Vo = 3.3 – 2.5 = 0.8V

Comparator

Non-inverting

If Vin < Vref, Vo = -Vsat ≅ - VEE

Vin > Vref, Vo = +Vsat = +VCC

Inverting

If Vin < Vref, Vo = +Vsat ≅ +VCC

Vin > Vref, Vo = -Vsat = - VEE

Procedures

Adder

• Connect the circuit as per the diagram shown in Fig.1 and Fig.2.

• Apply the supply voltages of +15V to pin7 and pin4 of IC741 respectively.

• Apply the inputs V1 and V2 as shown in Fig.1 and Fig.2.

• Apply two different signals (DC/AC ) to the inputs

• Vary the input voltages and note down the corresponding output at pin 6 of the IC

741 adder circuit.

• Notice that the output is equal to the sum of the two inputs.

Subtractor

1. Connect the circuit as per the diagram shown in Fig.3.

2. Apply the supply voltages of +15V to pin7 and pin4 of IC741 respectively.

3 Apply the inputs V1 and V2 as shown in Fig.3.



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4. Apply two different signals (DC/AC) to the inputs

5. Vary the input voltages and note down the corresponding output at pin 6 of the IC

741 subtractor circuit.

7. Notice that the output is equal to the difference of the two inputs.

Comparator

1. A fixed reference voltage Vref and varying voltage Vin is applied as shown in Fig.3

and Fig.4.

2. Vary the input voltage above and below the Vref and note down the output at pin

6 of 741 IC.

3. Observe that,

when Vin is less than Vref,

Output voltage is Non-inverting Inverting

-Vsat ( ≅ - VEE) +Vsat (≅+VCC)

when Vin is greater than Vref,

Output voltage is Non-inverting Inverting

+Vsat (≅+VCC) -Vsat ( ≅ - VEE)

Observations

Adder

V1(V)

V2(V)

Inverting adder

Vo(V)

Non-Inverting

adder Vo(V)

Subtractor

V1(V) V2(V) Vo(V)



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Comparator

Vin(V)

Vref(V)

Non-Inverting

comparator

Vo(V)

Inverting

comparator

Vo(V)

Precautions

Check the connections before giving the power supply.

Readings should be taken carefully.

Results

Inferences

Questions

1. What is the saturation voltage of 741 in terms of VCC?

2. What is the maximum voltage that can be given at the inputs?



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3. Integrator and Differentiator Circuits using IC 741

Aim: To design and verify the operation of an integrator and differentiator for a

given input.

Apparatus required


1 741 IC Refer page no. 2 1

2 Capacitors 0.1µf, 0.01µf Each one

3 Resistors 159Ω, 1.5kΩ Each one

4 Regulated Power supply (0 – 30)V,1A 1

5 Function generator (1Hz – 1MHz) 1


Theory

Integrator

In an integrator circuit, the output voltage is integral of the input signal. The

output voltage of an integrator is given by Vo = -1/R1Cf Vidt

t

o

∫

At low frequencies the gain becomes infinite, so the capacitor is fully charged and

behaves like an open circuit. The gain of an integrator at low frequency can be

limited by connecting a resistor in shunt with capacitor.

Differentiator

In the differentiator circuit the output voltage is the differentiation of the input

voltage. The output voltage of a differentiator is given by Vo = -RfC1 dt

dVi .The input

impedance of this circuit decreases with increase in frequency, thereby making the

circuit sensitive to high frequency noise and the circuit may become unstable. Hence

an input resistor is connected in series with the capacitor and a capacitor is

connected in parallel with the feedback resistor.



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Circuit Diagrams

Fig. 1: Integrator

Fig. 2: Differentiator

Design equations

Integrator

Choose T = 2πR1Cf

Where T= Time period of the input signal

Assume Cf and find R1

Select Rf = 10R1

Vo (p-p) = dtVCR

ppi

T

of

)(

2/

1

1−∫

−



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Differentiator

Select given frequency fa = 1/(2πRfC1), Assume C1 and find Rf

Select fb = 10 fa = 1/2πR1C1 and find R1

From R1C1 = RfCf, find Cf

Model Calculations

Integrator

For T= 1 msec

fa= 1/T = 1 KHz

fa = 1 KHz = 1/(2πR1Cf)

Assuming Cf= 0.1µf, Rf is found from R1=1/(2πfaCf)

R1=1.59 KΩ

Rf = 10 R1

Rf= 15.9kΩ

Differentiator

For T = 1 msec

f= 1/T = 1 KHz

fa = 1 KHz = 1/(2πRfC1)

Assuming C1= 0.1µf, Rf is found from Rf=1/(2πfaC1)

Rf=1.59 KΩ

fb = 10 fa = 1/2πR1C1

for C1= 0.1µf; R1 =159Ω

Procedures

Integrator

1. Connect the circuit as per the diagram shown in Fig.1

2. Apply a square wave/sine input of 4V(p-p) at 1KHz

3. Observe the output at pin 6.

4. Draw input and output waveforms as shown in Fig.3.

Differentiator

1. Connect the circuit as per the diagram shown in Fig. 2

2. Apply a square wave/sine input of 4V(p-p) at 1KHz

3. Observe the output at pin 6

4. Draw the input and output waveforms as shown in Fig.4



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Wave Forms

Integrator

Fig. 3: Input and output waves forms of integrator



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Differentiator

Fig. 4 : Input and output waveforms of Differentiator



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Observations

Integrator

Input –Square wave Output - Triangular

Amplitude(VP-P)

(V)

Time period

(ms)

Amplitude (VP-P)

(V)

Time period

(ms)

Input –sine wave Output - cosine

Amplitude(VP-P)

(V)

Time period

(ms)

Amplitude (VP-P)

(V)

Time period

(ms)

Differentiator

Input –square wave Output - Spikes

Amplitude (VP-P)

(V)

Time period

(ms)

Amplitude (VP-P)

(V)

Time period

(ms)

Input –sine wave Output - cosine

Amplitude (VP-P)

(V)

Time period

(ms)

Amplitude (VP-P)

(V)

Time period

(ms)

Precautions



Results

Inferences



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Questions

1. What are the problems of ideal differentiator?

2. What are the problems of ideal integrator?

3. What are the applications of differentiator and integrator?

4. What is the need for Rf in the circuit of integrator?

5. What is the effect of C1 on the output of a differentiator?



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4. Active Filter Applications – LPF, HPF (first order)

Aim: To design and obtain the frequency response of

i) First order Low Pass Filter (LPF)

ii) First order High Pass Filter (HPF)

Apparatus required


1 IC 741 Refer page no. 2 1

2 Resistors

Variable Resistor

10k ohm

20kΩ pot

3

1

3 capacitors 0.01µf 1



6 Function Generator (1Hz – 1MHz) 1

Theory

LPF

A LPF allows frequencies from 0 to higher cut of frequency, fH. At fH the gain

is 3 db from maximum gain and after fH gain decreases at a constant rate with an

increase in frequency. The gain decreases 20dB each time the frequency is

increased by 10. Hence the rate at which the gain rolls off after fH is 20dB/decade or

6 dB/ octave, where octave signifies a two fold increase in frequency. The frequency

f=fH is called the cut off frequency because the gain of the filter at this frequency is

down by 3 dB from 0 Hz. Other equivalent terms for cut-off frequency are -3dB

frequency, break frequency, or corner frequency.

HPF

The frequency at which the magnitude of the gain is 0.707 times the maximum

value of gain is called low cut off frequency. Obviously, all frequencies higher than fL

are pass band frequencies with the highest frequency determined by the closed –

loop band width all of the op-amp. A HPF allows frequiences grater than lower cut of

frequency fL. At fL gain is 3 db down from maximum gain. The frequency f= fL is

called the lower cut off frequency.



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Circuit diagrams

Fig. 1: Low pass filter

Fig. 2: High pass filter

Design equations

• Chose a value of high cut off frequeinces fH =1/( 2πRC )

• Assume c <01 µF and calculate R using R= 1/(2πfHC) Ω

• Select value of R1 and RF depending on the desired pass band gain AF = 1+

(RF/R1)

First Order LPF: To design a Low Pass Filter for higher cut off frequency fH = 4 KHz

and pass band gain of 2

fH = 1/( 2πRC )



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Assuming C=0.01 µF, the value of R is found from

R= 1/(2πfHC) Ω =3.97KΩ

The pass band gain of LPF is given by AF = 1+ (RF/R1)= 2

Assuming R1=10 KΩ, the value of RF is found from

RF=( AF-1) R1=10KΩ

First Order HPF: To design a High Pass Filter for lower cut off frequency

fL = 4 KHz and pass band gain of 2

fL = 1/( 2πRC )

Assuming C=0.01 µF,the value of R is found from

R= 1/(2πfLC) Ω =3.97KΩ

The pass band gain of HPF is given by AF = 1+ (RF/R1)= 2

Assuming R1=10 KΩ, the value of RF is found from

RF=( AF-1) R1=10KΩ

Procedure

First Order LPF

1. Connections are made as per the circuit diagram shown in Fig.1.

2. Apply sinusoidal wave of constant amplitude as the input such that op-amp does

not go into saturation.

3. Vary the input frequency and note down the output amplitude at each step as

shown in Table (a).

4. Plot the frequency response as shown in Fig.3.

First Order HPF

1. Connections are made as per the circuit diagrams shown in Fig. 2.

1. Apply sinusoidal wave of constant amplitude as the input such that op-amp does

not go into saturation.

2. Vary the input frequency and note down the output amplitude at each step as

shown in Table (b).

4. Plot the frequency response as shown in Fig 4.



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Tabular Form Observations

Input voltage Vin = 0.5V

Table (a) First order LPF Table (b) First order HPF

Model graphs

Fig. 3: Frequency response of LPF Fig. 4:Frequency response of HPF

Frequency

(Hz)

O/P

Voltage(V)

Voltage

Gain

Vo/Vi

Gain

(dB)

Frequency

(Hz)

O/P

Voltage(V)

Voltage

Gain

Vo/Vi

Gain

(dB)



29

Precautions



Results

Inferences

Questions

1. What is meant by frequency scaling?

2. How do you convert an original frequency (cut off) fH to a new cut off frequency

fH?

3. What is the effect of order of the filter on frequency response characteristics?

4. What modifications in circuit diagrams require to change the order of the filter?



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5. Active Filter Applications – BPF & Band Reject

(Wideband) and Notch Filters

Aim: To design and obtain the frequency response of

i) Wide Band pass filter

ii) Wide Band reject filter

iii) Notch filter

Apparatus required

Theory

Filter is a circuit that accepts certain band of frequencies and rejects other band of

frequencies

Band pass filter: A band pass filter has a pass band between two cutoff

frequencies fH and fL such that fH > fL. Any input frequency outside this pass band is

attenuated. There are two types of band-pass filters. Wide band pass and Narrow

band pass filters. We can define a filter as wide band pass if its quality factor Q <10.

If Q>10, then we call the filter a narrow band pass filter. A wide band pass filter can

be formed by simply cascading high-pass and low-pass filter the order of band pass

filter depends on the order of high pass and low pass filter.


1 741 IC Refer page no 2 3

2 Resistors

Resistors

5.6kΩ

39kΩ

9

2

3 Resistors (20kΩ pot) 2

4 Capacitors

Capacitors

Capacitors

0.01µf

0.1µf

0.2µf

2

2 1

5 Regulated Power supply (0 – 30)V,1A 1

6 Function Generator (1Hz – 1MHZ) 1




31

Band Rejection Filter: The band-reject filter is also called a band-stop or

band-elimination filter. In this filter, frequencies are attenuated in the stop band while

they are passed outside this band. Band reject filters are classified as wide band-

reject narrow band-reject. Wide band-reject filter is formed using a low pass filter, a

high-pass filter and summing amplifier. To realize a band-reject response, the low

cut off frequency fL of high pass filter must be larger than high cut off frequency fH of

low pass filter. The pass band gain of both the high pass and low pass sections must

be equal.

Notch Filter or Narrow Band Reject Filter: The narrow band reject

filter, often called the notch fitter is commonly used for the rejection of a single

frequency. The most commonly used notch filter is the twin-T network .This is a

passive filter composed of two T-shaped networks. One T network is made up of two

resistors and a capacitor, while the other uses two capacitors and a resistor. The

passive twin-t network has a relatively low figure of merit can be increased

significantly by using active notch filter as shown in fig.3.The notch-out frequency is

the frequency at which maximum attenuation occurs and is given by

fN = 1/( 2πRC )

Circuit diagrams

Fig. 1: Wideband pass filter



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Fig. 2: Wideband reject filter

Fig. 3: Notch filter

Design

Band pass filter: To design a band pass filter having fH =400Hz and fL = 4KHz

and pass band gain of 2. As shown in Fig.1,the first section consisting of Op-

Amp,RF,R1,R and C is the high pass filter and second consisting of low pass filter.

The design of low pass and high pass filters.

Low Pass Filter Design

Assuming C’=0.01µf, the value of R’ is found from

R’ = 1/(2πfH C’) Ω =3.97KΩ

The pass band gain of LPF is given by ALPF = 1+ (R’ F / R’1) =2

Assuming R’1=5.6 KΩ, the value of R’F is found from R’F = ( AF-1) R’1=5.6KΩ



33

High Pass Filter Design

Assuming C=0.01µf, the value of R is found from

R = 1/(2πfLC) Ω =39.7KΩ

The pass band gain of HPF is given by AHPF = 1+ (RF / R1 )=2

Assuming R1=5.6 KΩ, the value of RF is found from

RF = ( AF-1) R1=5.6KΩ

Band reject filter: To design a band reject filter with fH = 400Hz, fL = 4000Hz

and pass band gain of 2

Low Pass Filter Design

Assuming C’=0.01µf, the value of R’ is found from

R’ = 1/(2πfH C’) Ω =39KΩ

The pass band gain of LPF is given by ALPF = 1+ (R’ F / R’1 )=2

Assuming R’1=5.6 KΩ, the value of R’F is found from

R’F =( AF-1) R’1=5.6KΩ

High Pass Filter Design

Assuming C=0.01µf, the value of R is found from

R = 1/ (2πfLC) Ω =3.9KΩ

The pass band gain of HPF is given by AHPF = 1+ (RF / R1) =2

Assuming R1=5.6 KΩ, the value of RF is found from

RF = (AF-1) R1=5.6KΩ

Adder circuit design: Select all resistors equal value such that gain is unity.

Assume R2=R3=R4=5.6 KΩ

Notch Filter Design: fN = 400Hz

Assuming C=0.1µf,the value of R is found from

R = 1/ (2πfNC)=39 KΩ

Procedure

Wide Band Pass Filter

1. Connect the circuit as per the circuit diagram shown in Fig.1

2. Apply sinusoidal wave of 0.5V amplitude as input such that op-amp does not go

into saturation (depending on gain).

3. Vary the input frequency from 100 Hz to 100 KHz and note down the output

amplitude at each step as shown in Table (a).




34

Wide Band Reject Filter


2. Apply sinusoidal wave of 0.5V amplitude as input such that opamp does not go



amplitude at each step as shown in Table( b).


Notch Filter

1. Connect the circuit as per the circuit diagram shown in Fig 3

2. Apply sinusoidal wave of 2Vp-p amplitude as input such that opamp does not go



amplitude at each step as shown in Table( c).

4. Plot the frequency response as shown in Fig 6.

Observations

Input voltage (Vi) = 0.5V

Table(a) Band pass filter Table(b) Band Reject Filter

Frequency O/P

Voltage(V)

Gain

Vo/Vi

Gain in

dB

Frequency O/P

Voltage

Vo(V)

Gain

Vo/Vi

Gain in

dB



35

Table(c) Notch filter

Input voltage=2Vp-p

Model graphs

Fig. 4 : Frequency response of Fig. 5 : Frequency response

wide band pass filter of wide band reject filter

Frequency O/P Voltage(V) Vo/Vi Gain in

dB



36

Fig. 6: Frequency response of notch filter

Precautions



Results

Inferences

Questions

1. What is the relation between fC & fH, fL?

2. How do you increase the gain of the wideband pass filter?

3. What is the application of Notch filter?

4. What is the order of the filter (each type)?.What modifications you suggest for

the circuit diagram to increase the order of the filter?

5. What is the gain roll off outside the pass band?

6. What is the difference between active and passive filters?

7. What are the advantages of active filters over passive filters?



37

6. IC 741 Oscillator Circuits

Phase Shift and Wien Bridge Oscillators

Aim: To design (i) phase shift and (ii) Wien Bridge oscillators for the given

frequency of oscillation and verify it practically.

Apparatus required



2 Resistors

Variable Resistor

1.3 KΩ,3.18 KΩ

13KΩ, ,31.8 KΩ

500 KΩ pot

Each Three

Each one 1

3 Capacitors 0.1 µF

0.01 µF

3

2


5 Cathode Ray Oscilloscope (0 -20MHz) 1

Theory

The function of an oscillator is to generate alternating current or voltage

waveforms.i,e. an oscillator circuits generates a repetitive wave form of fixed

amplitude and frequency without any external input signal. In oscillators positive

feedback is used. There are two conditions for oscillators

• magnitude of closed loop gain Aβ≥1

• Total phase shift of the loop gain Aβ=00 or 3600.

In the phase shift oscillator, out of 360o phase shift, 180o phase shift is

provided by the op-amp and another 180o is by 3 RC networks. In the Weinbridge

oscillator, the balancing condition of the bridge provides the total 360o phase shift.



38

Circuit Diagrams

Fig. 1 : RC Phase shift oscillator

Fig. 2: Wien Bridge oscillator



39

Design

1. Phase shift oscillator

To design a phase shift oscillator with fo =500 Hz

fo = 1/(2πRC 6 )

and gain= RF/R1= 29

Assuming C = 0.1 µF,the value of R is found from

R = 1/ (2π foC 6 ) = 1.3 KΩ

Take R1 = 10R =13 KΩ

RF = 29R1 (use 500K pot)

2. Wien Bridge Oscillator

To design a Wien bridge oscillator with fo =5 KHz

fo = 1/2πRC and RF = 2R1

Assuming C = 0.01 µF, the value of R is found from

R= 1/2πfc= 3.18 KΩ

Take R1 = 10 R=31.8 KΩ

RF = 2R1 (use 100K pot)

Procedures



2. Observe the output waveform on the CRO.

3. Vary the potentiometer to get the undistorted waveform as shown Fig.a.

4. Measure the time period and amplitude of the output waveform.

5. Plot the waveforms on a graph sheet.



2. Observe the output waveform on the CRO.

3. Vary the potentiometer to get the undistorted waveform as shown in Fig.b

4. Measure the time period and amplitude of the output waveform.

5. Plot the waveforms on a graph sheet



40

Waveforms

Fig.a: RC Phase Shift Oscillator Fig.b: Wien Bridge Oscillator

Tabular form and Observations


S.No Amplitude(VP-P) Time period

(ms)

Practical

frequency

(Hz)

Theoretical

frequency (Hz)


S.No Amplitude(VP-P) Time period

(ms)

Practical

frequency

(Hz)

Theoretical frequency

(Hz)



41

Precautions



Results

Inferences

[

Questions

1. What is an oscillator?

2. How do you change the frequency of oscillation in RC phase shift and Wien

bridge oscillators?

3. What are the applications of oscillators?

4. What is the advantage of using opamp in the oscillator circuit?

5. How do you achieve fine variations in fo ?

6. How do you achieve coarse variations in fo ?



42

7. Function Generator using OPAMPs

Aim: To generate square wave and triangular wave forms by using OPAMPs.

Apparatus required


1 741 IC Refer page no.2 2

2 Capacitors 0.01µf,0.001µf Each one

3 Resistors

Resistors

86kΩ ,68kΩ ,680kΩ

100kΩ

Each one

2


5 Cathode Ray Oscilloscope (0 -20MHz) 1

Theory: Function generator generates waveforms such as sine, triangular, square

waves and so on of different frequencies and amplitudes. The circuit shown in Fig.1

is a simple circuit which generates square waves and triangular waves

simultaneously. Here the first section is a square wave generator and second

section is an integrator. When square wave is given as input to integrator it produces

triangular wave.

Circuit Diagram

Fig.1: Function generator



43

Design

Square wave Generator

T= 2RfC ln (2R2 +R1/ R1)

Assume R1 = 1.16 R2

Then T= 2RfC

Assume C and find Rf

Assume R1 and find R2

Integrator

Take f= 1/(2π R3 Cf)

Assume Cf find R3

R4 =10 R3

Model Calculations

Square wave Generator

For T= 2 m sec

T = 2 Rf C

Assuming C= 0.01µf

Rf = 2.10-3/ 2.01.10-6

= 10 KΩ

Assuming R1 = 100 KΩ

R2 = 86 KΩ

Integrator

Assume Cf = 0.01µf

R3= 1/(2π f Cf) = 3.18KΩ take R3= 5KΩ

R4 = 50 KΩ

Procedure

1. Connect the circuit as per the circuit diagram shown above.

2. Obtain square wave at A and Triangular wave at Vo2 as shown in Fig.1.

3. Draw the output waveforms as shown in Fig.2(a) and (b).

Observations

Square Wave:

Vp-p = 26 V(p-p)

T = 1.8 msec

Triangular Wave:

Vp-p = 1.3 V

T= 1.8 msec



44

Wave Forms

Fig. 2 (a): Output at ‘A’ Fig.2(b): Output at V02

Precautions



.

Results

Inferences

Questions

1. How do you change the frequency of square wave?

2. What are the applications of function generator?



45

8. IC 555 Timer-Monostable Operation Circuit

Aim: To generate a pulse using Monostable Multivibrator by using IC555

Apparatus required

S.No Equipment/Component

name

Specifications/Value Quantity



3 Resistor 10kΩ 1


5 Function Generator (1HZ – 1MHz) 1

6 Cathode ray oscilloscope (0 – 20MHz) 1

Theory: A Monostable Multivibrator, often called a one-shot Multivibrator, is a

pulse-generating circuit in which the duration of the pulse is determined by the RC

network connected externally to the 555 timer. In a stable or stand by mode the

output of the circuit is approximately Zero or at logic-low level. When an external

trigger pulse is obtained, the output is forced to go high ( ≅ VCC). The time for which

the output remains high is determined by the external RC network connected to the

timer. At the end of the timing interval, the output automatically reverts back to its

logic-low stable state. The output stays low until the trigger pulse is again applied.

Then the cycle repeats. The Monostable circuit has only one stable state (output

low), hence the name monostable. Normally the output of the Monostable

Multivibrator is low.



46

Circuit Diagram

Fig.1: Monostable Circuit using IC555

Design

Consider VCC = 5V, for given tp

Output pulse width tp = 1.1 RA C

Assume C in the order of microfarads & Find RA

Typical values

If C=0.1 µF, RA = 10k then tp = 1.1 mSec

Trigger Voltage must be greater than 1/3 Vcc let it be = 4 V

Procedure

1. Connect the circuit as shown in the circuit diagram.

2. Apply Negative triggering pulses at pin 2 of frequency 1 KHz.

3. Observe the output waveform and measure the pulse duration T high.

4. Compare it with given tp value.



47

Waveforms

Fig. 2(a): Trigger signal (b) Output Voltage (c) Capacitor Voltage

Readings

Precautions



Results

Inferences

Trigger Output wave Capacitor output



48

Questions

1. Is the triggering given is edge type or level type? If it is edge type, trailing or

raising edge?

2. What is the effect of amplitude and frequency of trigger on the output?

3. How to achieve variation of output pulse width over fine and course ranges?

4. What is the effect of Vcc on output?

5. What are the ideal charging and discharging time constants (in terms of R and C)

of capacitor voltage?

6. What is the other name of monostable Multivibrator? Why?

7. What are the applications of monostable Multivibrator?



49

9. IC 555 Timer - Astable Operation Circuit

Aim: To generate pulse and square waveforms using IC555.

Apparatus required

S.No Equipment/Component

name

Specifications/Value Quantity


2 Resistors 3.6kΩ,7.2kΩ Each one


4 Diode OA79 1



Theory

When the power supply VCC is connected, the external timing capacitor ‘C”

charges towards VCC with a time constant (RA+RB) C. During this time, pin 3 is high

(≈VCC) as Reset R=0, Set S=1 and this combination makes Q=0 which has

unclamped the timing capacitor ‘C’.

When the capacitor voltage equals 2/3 VCC, the upper comparator triggers the

control flip flop on that Q =1. It makes Q1 ON and capacitor ‘C’ starts discharging

towards ground through RB and transistor Q1 with a time constant RBC. Current also

flows into Q1 through RA. Resistors RA and RB must be large enough to limit this

current and prevent damage to the discharge transistor Q1. The minimum value of

RA is approximately equal to VCC/0.2 where 0.2A is the maximum current through the

ON transistor Q1.

During the discharge of the timing capacitor C, as it reaches VCC/3, the lower

comparator is triggered and at this stage S=1, R=0 which turns Q =0. Now Q =0

unclamps the external timing capacitor C. The capacitor C is thus periodically

charged and discharged between 2/3 VCC and 1/3 VCC respectively. The length of

time that the output remains HIGH is the time for the capacitor to charge from 1/3 VCC

to 2/3 VCC.

The capacitor voltage for a low pass RC circuit subjected to a step input of

VCC volts is given by VC = VCC [1- exp (-t/RC)]



50

Circuit Diagram

Fig.1: 555 Astable Circuit

Design

Charging Time t c = 0.69 (RA + 2RB) C

Discharging Time t d = 0.69 (RB) C

Total time period T = 0.69 (RA + 2 RB) C

f= 1/T = 1.44/ (RA + 2RB) C

The maker of the 555 timer Signetics defined

Duty cycle (D) = td/T = RB/(RA+2RB)

For a given value of frequency assume C and Duty cycle then find RA, RB

Model calculations

Given f=1 KHz. Assuming c=0.1µF and D=0.25

∴1 KHz = 1.44/ (RA+2RB) x 0.1x10-6 and 0.25 =RB/ (RA+2RB)

Solving both the above equations, we obtain RA & RB as

RA = 7.2K Ω

RB = 3.6K Ω

Procedure

i) Pulse Generator

1. Connect the circuit as per the circuit diagram shown without connecting the

diode OA79.

2. Observe and note down the waveform at pin 6 and across timing capacitor.



51

3. Measure the frequency of oscillations and duty cycle and then compare with

the theoretical values.

4. Sketch both the waveforms to the same time scale.

ii) Square wave generator

1. Connect the diode OA79 as shown in Figure to get D=0.5 or 50%.

2. Choose Ra=Rb = 10KΩ and C=0.1µF

3. Observe the output waveform, measure frequency of oscillations and the duty

cycle and then sketch the o/p waveform.

Waveforms

Fig. 2 (a) Pulse output (b) Capacitor voltage of Unsymmetrical square wave output

(c)Square wave output

Observations

Parameter Unsymmetrical Symmetrical

Voltage VPP

Time period T

Duty cycle

Precautions





52

Results

Inferences

Questions

1. What is the effect of C on the output?

2. How do you vary the duty cycle?

3. What are the applications of 555 in astable mode?

4. What is the function of diode in the circuit?

5. On what parameters Tc and Td designed?

6. What are charging and discharging times



53

10. Schmitt Trigger Circuits- using IC 741 & IC 555

Aim: To design the Schmitt trigger circuit using IC 741 and IC 555

Apparatus required



2 555IC Refer page no 6 1


4 Multimeter 1

5 Resistors 100 Ω

56 KΩ

2

1

6 Capacitors 0.1 µf, 0.01 µf Each one

7 Regulated power supply (0 -30V),1A 1

Theory

The circuit shows an inverting comparator with positive feed back. This circuit

converts orbitrary wave forms to a square wave or pulse. The circuit is known as the

Schmitt trigger (or) squaring circuit. The input voltage Vin changes the state of the

output Vo every time it exceeds certain voltage levels called the upper threshold

voltage Vut and lower threshold voltage Vlt.

When Vo= - Vsat, the voltage across R1 is referred to as lower threshold

voltage, Vlt. When Vo=+Vsat, the voltage across R1 is referred to as upper threshold

voltage Vut.

The comparator with positive feed back is said to exhibit hysterisis, a dead

band condition.

Hysteresis width VH = VUT-VLT

Circuit Diagrams

Fig. 1: Schmitt trigger circuit using IC 741



54

Fig. 2: Schmitt trigger circuit using IC 555

Design

Vutp = [R1/(R1+R2 )](+Vsat)

Vltp = [R1/(R1+R2 )](-Vsat)

Vhy = Vutp – Vltp

=[R1/(R1+R2)] [+Vsat – (-Vsat)]

Procedure

1. Connect the circuit as shown in Fig.1 and Fig.2.

2. Apply an arbitrary waveform (sine/triangular) of peak voltage greater than UTP to

the input of a Schmitt trigger.

3. Observe the output at pin6 of the IC 741 and at pin3 of IC 555 Schmitt trigger

circuit by varying the input and note down the readings as shown in Table 1 and

Table 2

4. Find the upper and lower threshold voltages (Vutp, VLtp) from the output wave

form.



55

Wave forms

Fig. 3(a) Schmitt trigger input wave form (b) Schmitt trigger output wave form

Observations

Table 1

Parameter Input Output

741 555 741 555

Voltage( Vp-p)

Time period(ms)

Table 2

Parameter 741 555

Vutp

Vltp

Precautions



Results

Inferences



56

Questions

1. What is the other name for Schmitt trigger circuit?

2. In Schmitt trigger which type of feed back is used?

3. What is meant by hysteresis?

4. What are effects of input signal amplitude and frequency on output?



57

11. IC 565- PLL Applications

Aim: To design a frequency multiplier using IC 565

Apparatus required




3 Resistors 12KΩ,54.5 KΩ Each one

4 Capacitors

0.01µF

0.1 µF

10µF

2

1 1

5 Regulated power supply (0 -30V),1A 1


Theory

The frequency divider is inserted between the VCO and the phase

comparator of PLL. Since the output of the divider is locked to the input frequency fIN,

the VCO is actually running at a multiple of the input frequency .The desired amount

of multiplication can be obtained by selecting a proper divide– by – N network ,where

N is an integer. To obtain the output frequency fOUT=2fIN, N = 2 is chosen. One must

determine the input frequency range and then adjust the free running frequency fOUT

of the VCO by means of R1 and C1 so that the output frequency of the divider is

midway within the predetermined input frequency range. The output of the VCO now

should be 2fIN . The output of the VCO should be adjusted by varying potentiometer

R1. A small capacitor is connected between pin7 and pin8 to eliminate possible

oscillations. Also, capacitor C2 should be large enough to stabilize the VCO

frequency.



58

Circuit diagram

Fig.1: PLL as Frequency Multiplier

Design

If C= 0.01µF and the frequency of input trigger signal is 2KHz, output pulse

width of 555 in monostable mode is given by

1.1RAC = 1.2T =1.2/f

RA= 1.2/(1.1Cf)=54.5KΩ

fIN=fOUT/N

Under locked conditions,

fOUT = NfIN = 2fIN = 4KHz

Procedure

1. The circuit is connected as per the circuit diagram.

2. Apply a square wave input to the pin2 of the 565

3. Observe the output at pin4 of 565 under locked condition.

4. Give the output of 565 to the pin2 of 555 IC.

5. Observe the output of 555 at pin3.

6. Now give the output of 555 as feedback to the pin5 of the 565.

7. Observe the frequency of output signal fo at pin4 of 565 IC.

8. Draw the wave forms.



59

Wave forms

Fig. 2(a): Input

(b): PLL output under locked conditions without 555

(c): Output at pin4 of 565 with 555 connected in the feedback

Observations


Amplitude (Vp-p)

Frequency (KHz)

Precautions



Result

Inferences



60

Questions

1. Out of capture and lock ranges, which is smaller?

2. What is the function of VCO in a PLL?

3. What does happen if frequency divider network -by- 4 is placed in the

feedback?



61

12. IC 566 – VCO Applications

Aim: i) To observe the applications of VCO-IC 566

ii) To generate the frequency modulated wave by using IC 566

Apparatus required

S.No Equipment/Component Name Specifications/Value Quantity

1 IC 566 Refer page no.10 1

2 Resistors 10KΩ

1.5KΩ

2

1

3 Capacitors 0.1 µF

100 pF

1

1

4 Regulated power supply 0-30 V, 1 A 1

5 Cathode Ray Oscilloscope 0-20 MHz 1

6 Function Generator 0.1-1 MHz 1

Theory

The VCO is a free running Multivibrator and operates at a set frequency fo

called free running frequency. This frequency is determined by an external timing

capacitor and an external resistor. It can also be shifted to either side by applying a

d.c control voltage vc to an appropriate terminal of the IC. The frequency deviation is

directly proportional to the dc control voltage and hence it is called a “voltage

controlled oscillator” or, in short, VCO.

The output frequency of the VCO can be changed either by R1, C1 or the

voltage VC at the modulating input terminal (pin 5). The voltage VC can be varied by

connecting a R1R2 circuit. The components R1 and C1 are first selected so that VCO

output frequency lies in the centre of the operating frequency range. Now the

modulating input voltage is usually varied from 0.75 VCC which can produce a

frequency variation of about 10 to 1.



62

Circuit Diagram

Fig.1: Voltage Controlled Oscillator

Design

1. Maximum deviation time period =T.

2. fmin = 1/T.

where fmin can be obtained from the FM wave

3. Maximum deviation, ∆f= fo - fmin

4. Modulation index β = ∆f/fm

5. Band width BW = 2(β+1) fm = 2 (∆f+fm)

6. Free running frequency,fo = 2(VCC -Vc) / R1C1VCC

Procedure

1. The circuit is connected as per the circuit diagram shown in Fig1.

2. Observe the modulating signal on CRO and measure the amplitude and

frequency of the signal.

3. Without giving modulating signal, take output at pin 4, we get the carrier

wave.

4. Measure the maximum frequency deviation of each step and evaluate the

modulating Index.

mf = β = ∆f/fm



63

Waveforms:

Fig. 2 (a): Input wave of VCO (b) Output of VCO at pin3 (c) Output of VCO at pin4

Observations

VCC=+12V; R1=R3=10KΩ; R2=1.5KΩ; fm=1KHz

Free running frequency, fo = 26.1KHz

fmin = 8.33KHz

∆f= 17.77 KHz

β = ∆f/fm = 17.77

Band width BW ≈ 36 KHz

Precautions



Result

Inferences

Questions

1. What are the applications of VCO?

2. What is the effect of C1 on the output?



64

13. Voltage Regulator using IC723

Aim: To design a low voltage variable regulator of 2 to 7V using IC 723.

Apparatus required


1 IC 723

Refer appendix A 1

2 Resistors 3.3KΩ,4.7KΩ,

100 Ω

Each one

3 Variable Resistors 1KΩ, 5.6KΩ Each one

4 Regulated Power supply 0 -30 V,1A 1

5 Multimeter 3 ½

digit display 1

Theory

A voltage regulator is a circuit that supplies a constant voltage regardless of

changes in load current and input voltage variations. Using IC 723, we can design

both low voltage and high voltage regulators with adjustable voltages.

For a low voltage regulator, the output VO can be varied in the range of

voltages Vo < Vref, where as for high voltage regulator, it is VO > Vref. The voltage Vref

is generally about 7.5V. Although voltage regulators can be designed using Op-

amps, it is quicker and easier to use IC voltage Regulators.

IC 723 is a general purpose regulator and is a 14-pin IC with internal short

circuit current limiting, thermal shutdown, current/voltage boosting etc. Furthermore

it is an adjustable voltage regulator which can be varied over both positive and

negative voltage ranges. By simply varying the connections made externally, we can

operate the IC in the required mode of operation. Typical performance parameters

are line and load regulations which determine the precise characteristics of a

regulator. The pin configuration and specifications are shown in the Appendix-A.



65

Circuit Diagram

Fig.1: Voltage Regulator

Design of Low voltage Regulator

Assume Io= 1mA,VR=7.5V

RB = 3.3 KΩ

For given Vo

R1 = ( VR – VO ) / Io

R2 = VO / Io

Procedure

Line Regulation:

1. Connect the circuit as shown in Fig.1.

2. Make Vin=10V and by varying the 5.6 KΩ Potentiometer. Set the output

Voltage to 5V by keeping RL =1KΩ

3. By varying Vn from 2 to 20V, measure the output voltage Vo.

4. Draw the graph between Vn and Vo as shown in model graph (a)

5. Repeat the above steps for Vo=3V

Load Regulation: For Vo=5V

1. Set Vi such that VO= 5 V

2. By varying RL, measure IL and Vo

3. Plot the graph between IL and Vo as shown in model graph (b)

4. Repeat above steps 1 to 3 for VO=3V.



66

Observations

Line Regulation:

Vo set to 5V Vo set to 3V

Load Regulation:

Vo set to 5V Vo set to 3V

Vi(V) Vo(V)

Vi(V) Vo(V)

IL (mA) Vo(V)

IL (mA) Vo(V)



67

Model graphs

Line Regulation Load Regulation

Precautions



Results

Inferences

Questions

1. What is the effect of R1 on the output voltage?

2. What are the applications of voltage regulators?

3. What is the effect of Vi on output?

.



68

14. Three Terminal Voltage Regulators- 7805, 7809, 7912

Aim: To obtain the regulation characteristics of three terminal voltage regulators.

Apparatus required

S.No Equipment/Component Name Specifications/Values Quantity

1 Bread board 1

2 IC7805 Refer appendix A 1



5 Multimeter 3 ½

digit display 1

6 Milli ammeter 0-150 mA 1

7 Regulated power supply 0-30 V 1

8 Connecting wires

9 Resistors pot 100Ω ,1k Ω Each one

Theory

A voltage regulator is a circuit that supplies a constant voltage regardless of

changes in load current and input voltage. IC voltage regulators are versatile,

relatively inexpensive and are available with features such as programmable output,

current/voltage boosting, internal short circuit current limiting, thermal shunt down

and floating operation for high voltage applications.

The 78XX series consists of three-terminal positive voltage regulators with

seven voltage options. These IC’s are designed as fixed voltage regulators and with

adequate heat sinking can deliver output currents in excess of 1A.

The 79XX series of fixed output voltage regulators are complements to the

78XX series devices. These negative regulators are available in same seven voltage

options.

Typical performance parameters for voltage regulators are line regulation,

load regulation, temperature stability and ripple rejection. The pin configurations and

typical parameters at 250C are shown in the Appendix-B.



69

Circuit Diagrams

Fig. 1: Positive Voltage Regulator

Fig. 2: Negative Voltage Regulator

Procedure

Line Regulation

1. Connect the circuit as shown in Fig.1 by keeping S open for 7805.

2. Vary the dc input voltage from 0 to 10V in suitable stages and note down the

output voltage in each case as shown in Table1 and plot the graph between

input voltage and output voltage.

3. Repeat the above steps for negative voltage regulator as shown in Fig.2 for

7912 for an input of 0 to -15V.

4. Note down the dropout voltage whose typical value = 2V and line regulation

typical value = 4mv for Vin =7V to 25V.



70

Load regulation

1. Connect the circuit as shown in the Fig. 1 by keeping S closed for load

regulation.

2. Now vary R1 and measure current IL and note down the output voltage Vo in

each case as shown in Table 2 and plot the graph between current IL and Vo.

3. Repeat the above steps as shown in Fig 2 by keeping switch S closed for

negative voltage regulator 7912.

Output Resistance

Ro= (VNL – VFL) Ω

IFL

VNL - load voltage with no load current

VFL - load voltage with full load current

IFL - full load current.

Observations

Line regulation Load Regulation

1) IC 7805

2) IC 7809

Input Voltage

Vi,(V)

Output Voltage

Vo(V)

Load Current

IL(mA)

Output Voltage

Vo(V)

Load Current

IL(mA)

Output Voltage

Vo(V)

Input Voltage

Vi,(V)

Output

Voltage Vo(V)



71

3) IC 7912

Model Graphs

Fig.3: IC 7805

Fig.4: IC 7809

Input Voltage

Vi,(V)

Output

Voltage Vo(V)

Load Current

IL(mA)

Output Voltage

Vo(V)



72

Fig.5: IC 7912

Precautions



Result

Inferences

Questions

1. Mention the IC number for a negative fixed three terminal voltage regulator of

12V.

2. Explain the significance of IC regulators in power supply

3. What is drop-out voltage?

4. What is the role of C1 and C2?

5. What are C1 and C2 called?



73

15. 4 bit DAC using OP AMP

Aim: To design 1) weighted resistor DAC

2) R-2R ladder Network DAC

Apparatus required

S.No. Equipment/Component name Specifications/Value Quantity


2 Resistors 1KΩ,2KΩ,4KΩ, 8KΩ Each one

3 Regulated Power supply 0-30 V , 1A 1

4 Multimeter (DMM) 3 ½

digit display 1

5 Connecting wires

6 Digital trainer Board 1

Theory: Digital systems are used in ever more applications, because of their

increasingly efficient, reliable, and economical operation with the development of the

microprocessor, data processing has become an integral part of various systems

Data processing involves transfer of data to and from the micro computer via

input/output devices. Since digital systems such as micro computers use a binary

system of ones and zeros, the data to be put into the micro computer must be

converted from analog to digital form. On the other hand, a digital-to-analog

converter is used when a binary output from a digital system must be converted to

some equivalent analog voltage or current. The function of DAC is exactly opposite

to that of an ADC.

A DAC in its simplest form uses an op-amp and either binary weighted

resistors or R-2R ladder resistors. In binary-weighted resistor op-amp is connected

in the inverting mode, it can also be connected in the non inverting mode. Since the

number of inputs used is four, the converter is called a 4-bit binary digital converter.



74

Circuit Diagrams

Fig. 1: Binary weighted resistor DAC

Fig. 2: R – 2R Ladder DAC

Design and Model Calculations

1. Weighted Resistor DAC

Vo = -Rf ]R

b

R

b

R

b

R

b DcBA +++

248

For input 1111, Rf = R = 4.7KΩ

Vo = - ] 512

1

4

1

8

1x

R

R f+++

Vo = - 9.375 V



75

2.R-2R Ladder Network:

Vo = -Rf ]R

b

R

b

R

b

R

b DcBA

24816+++

X 5

For input 1111, Rf = R= 1KΩ

Procedure

1. Connect the circuit as shown in Fig.1.

2. Vary the inputs A, B, C, D from the digital trainer board and note down the output

at pin 6. For logic ‘1’, 5 V is applied and for logic ‘0’, 0 V is applied.

3. Repeat the above two steps for R – 2R ladder DAC shown in Fig.2.

Observations

Weighted resistor DAC

S.No. D

(MSB)

C B A

(LSB)

Theoretical Voltage(V) Practical Voltage(V)



76

R-2R Ladder DAC

S.No. D

(MSB)

C B A

(LSB)

Theoretical Voltage(V) Practical Voltage(V)



77

Model Graph

Decimal Equivalent of Binary inputs

Precautions



Results

Inferences

Questions

1. How do you obtain a positive staircase waveform?

2. What are the drawbacks of binary weighted resistor DAC?

3. What is the effect of number of bits on output ?



78

Additional Experiments

1. Adder - Subtractor

Aim: To design adder-subtractor circuit by using operational amplifier.

Apparatus required



2 Resistor 1kΩ 5



7 Multimeter 3 ½

digit display 1

Theory: The circuit diagram shows an op-amp used as an adder-subtractor. Two

inputs are given for inverting and two for non-inverting terminal of opamp and these

inputs are applied through resistors. The output of the circuit is difference between

sum of non-inverting inputs and sum of inverting inputs.

Circuit Diagram

Fig.1 : Adder-subtractor

Procedure

• Connect the circuit as per the diagram shown in Fig 1.

• Apply the supply voltages of +15V to pin7 and pin4 of IC741 respectively.



79

• Apply the inputs V1, V2 ,V3 and V4 as shown in Fig 1.

• Vary the input voltages and note down the corresponding output at pin 6 of the IC

741 adder circuit.

Notice that the output is equal to the difference between sum of non-inverting inputs

and sum of inverting inputs.

Observations

V1(V)

V2(V)

V3(V)

V4(V)

V0(V)

Model Calculations

Vo = (V1 + V2) - (V3 + V4)

If V1 = 2.5V , V2 = 2.5V, V3 = 2.5V and V4=3V then

Vo = -0.5V

Precautions



Result

Inferences

Questions

1. What is the saturation voltage of 741 in terms of VCC?

2. What is the maximum voltage that can be given at the inputs?



80

2. Voltage- to- Current Converter

Aim: To design voltage to current converter with floating load and grounded load

using op amp

Apparatus required



2 Resistors 10 KΩ

1KΩ

5

1

3 Regulated Power supply (0-30V),1A 1

4 Multimeter 3 ½

digit display 1

5 Ammeter (0 – 30) µA 1


Theory

In many applications we must convert the given voltage into current. The two

types of voltage to current converters are

1. V to I converters with floating load

2. V to I converters with grounded load.

Floating load V – I converters are used as low voltage ac and dc voltmeters, diode

match finders, light emitting diodes and zener diode testers. V to I converters

Grounded load are used in testing such devices as zeners and LEDs forming a

ground load.

Circuit Diagrams

Fig. 1: V – I converter with grounded load



81

Fig. 2: V – I converter with floating load

Design

V – I converter with grounded load

I1+I2=IL

(Vin-V1)/R+(Vo-V1)/R=IL

Vin+Vo-2Vi=ILR

Since op-amp is non inverting

Gain=1+(R/R)=2

Vo=2Vi

Vin=Vo-Vo+ILR

IL=Vin/R

V – I converter with floating load

I1=IL

IL = Vin/R1

Procedure


1. Connect the circuit as per the circuit diagram shown in Fig. 1.

2. Set ac input to any desired value.

3. Switch on the dual trace supply and note down the readings of ammeter

4. Repeat the above procedure for varies values input voltages.


1. Connect the circuit as per the circuit diagram in Fig. 2.

2. Apply input voltage to the non-inverting terminal of 741.



82

3. Observe the output from CRO and note down the ammeter reading for various

values of input voltage.

Observations


Vin(V) Current (mA)

RL=1KΩ RL=10KΩ


Vin Current(mA)

Precautions



Results

Inferences

Questions

1. What is the effect of RL on the output current in V-to-I converter with

floating load?

2. What is the effect of R on the output current in V-to-I converter with

grounded load?

3. For what ranges of currents the circuits are useful?



83

3. Precision Half wave Rectifier

Aim: To obtain a precision rectifier (half wave rectifier using IC 741).

Apparatus required

S.No. Equipment/Component name Specifications/Value Quantity


2 Resistors

10 KΩ

1KΩ

5

1


5 Cathode Ray Oscilloscope (0-20MHz) 1


Theory

There are two types of half wave rectifiers. One is inverting half wave rectifier

and second one is non-inverting half wave rectifier. The below circuit show the non-

inverting half wave rectifier with diode (0A79) in the feed back loop of an op-amp.

Circuit diagram

Fig. 1: Precision Half wave Rectifier

Procedure

1. Connect the circuit as per the circuit diagram.

2. Give the sinusoidal input of 100mVp-p, 1 KHz from function generator.

3. Switch on the dual power supply of + 15V.

4. Note down the output from CRO.



84

Model Graphs

Fig. a) Input waveform to the half wave rectifier

b ) Output waveform

Sample readings


Amplitude (V),Vp-p

Time period (ms)

Precautions



Results

Inferences

Questions

1. What is the output if the diode is reversed?

2. What is a super diode?

3. What is precision rectifier?

4. What modifications you suggest to get negative half cycles at output?



85

4. Clipper Circuits using IC 741

Aim: To obtain the clipped waveforms of the input using IC741.

Apparatus required



2 Resistors 10 KΩ 1


4 Function generator (0-1MHz) 1

5 Diode 0A79 1

6 Cathode Ray Oscilloscope (0-20MHz) 1

Theory

A clipper is a circuit that removes positive or negative parts of the input

signal. In this circuit the op-amp is basically used as a voltage follower with a diode in

the feed back path. The clipping level is determined by the reference voltage Vref

which should be less than input voltage range of op-amp. Additionally +Vref is

derived from the positive supply voltage and -Vref is derived from the negative supply

voltage.

Circuit diagrams

Fig. 1: Positive Clipper



86

Fig. 2: Negative Clipper

Procedure

Positive clipper

1. Connect the circuit as per the circuit diagram shown in Fig 1.

2. Apply the reference voltage of 1V.

3. Apply a 6Vp-p of sine wave as input.

4. Note down the output waveform as shown in Fig 3(a) and 3(b).

Negative clipper

1. Connect the circuit as per the circuit diagram shown in Fig 2.

2. Apply the reference voltage of 1V.

3. Apply a 6Vp-p of sine wave as input.

4. Note down the output waveform as shown in Fig 3(c) and 3(d).

Waveforms

Positive clipper

Fig. 3 (a) : Input wave form (b) : Output wave form



87

Negative clipper

Fig. 3 (c): Input waveform (d): Output waveform

Observations

Positive clipper

Parameter Input Voltage Output Voltage

Amplitude (V),Vp-p

Time period (ms)

Negative clipper

Parameter Input Voltage Output Voltage

Amplitude (V), Vp-p

Time period (ms)

Precautions



Result

Inferences

Questions

1. What is the effect of Vref on the output?

2. How do you change a positive clipper into negative clipper?



88

APPENDIX-A

IC723

Pin Configuration

Specifications of 723

Power dissipation : 1W

Input Voltage : 9.5 to 40V

Output Voltage : 2 to 37V

Output Current : 150mA for Vin-Vo = 3V

10mA for Vin-Vo = 38V

Load regulation : 0.6% Vo

Line regulation : 0.5% Vo



89

APPENDIX-B

Pin Configurations

78XX 79XX

Plastic package

Typical parameters at 25oC

Parameter LM 7805 LM 7809 LM 7912

Vout,V 5 9 -12

Imax,A 1.5 1.5 1.5

Load Reg,mV 10 12 12

Line Reg,mV 3 6 4

Ripple Rej,dB 80 72 72

Dropout 2 2 2

Rout,mΩ 8 16 18

ISL,A 2.1 0.45 1.5



90

REFERENCES

1. D.Roy Choudhury and Shail B.Jain, “Linear Integrated Circuits”, 2nd edition,

New Age International.

2. James M. Fiore, “Operational Amplifiers and Linear Integrated Circuits”:

Theory and Application, WEST.

3. “Malvino, Electronic Principles”, 6th edition, TMH

4. Ramakant A. Gayakwad, “Operational and Linear Integrated Circuits”,4th

edition, PHI.

5. Roy Mancini, “OPAMPs for Everyone”, 2nd edition, Newnes.

6. S. Franco, “Design with Operational Amplifiers and Analog Integrated

Circuits”, 3rd edition, TMH.

7. William D. Stanley, “Operational Amplifiers with Linear Integrated Circuits”, 4th

edition, Pearson.

1. Study of OP AMPs - IC 741, IC 555, IC 565, IC 566, IC ...ece.gecgudlavalleru.ac.in/pdf/manuals/ICA-WITHOUTREADINGSMANU… · Short circuit protection 3. Offset voltage null capability

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