1-GSample/s 6-Bit Time-Interleaved SA-ADC Arrays with Background Digital Calibration Wenbo Liu, Paritosh Bhoraskar, Yuchun Chang and Yun Chiu Illinois Center for Wireless Systems Motivation & Approaches Time Interleaved ADC Arrays • To implement a high-speed ADC with relatively slow circuits. • Static channel mismatches – Offset, gain, linearity mismatch • Dynamic channel mismatches – Timing skew, jitter The Proposed Architecture • Single track/hold amplifier (THA) – Immune to timing skew and jitter • Time-interleaved ADC array – 10 100MSample/s SA-ADC – Adaptive digital filter (ADF) – Correct static channel mismatches • Reference conversion path – Slow but accurate – Provide ADFs with accurate digital codes • A DLL generating all timing signal with desired phases Linear Equalization • Linear equalizer – ADF taps track each bit’s weight and the offset – Taps are updated with the sampling rate of the reference ADC – All calibration is performed in the digital domain Major Circuit Analog Nonidealities • Analog impairments: – Mismatch of small capacitors degrading linearity – Stray capacitor (C p ) causing sampling gain loss – Comparator offset & charge injection (Q) resulting in an input referred offset, V os,input . • Static error model p n i i tot qn input os R i n i tot i in C C C C where V V V d C C V = - = ∑ ∑ - = - = 0 1 0 , 1 0 , ) 1 2 ( Sine-wave Test Performance 600 mW 5.0 / 6.0 1.3GS/s 2003 310 mW 4.7 / 6.0 2GS/s 2005 This work 2006 2004 Year 30 mW >5.5bit 1GS/s 55 mW 5.3 / 6.0 1GS/s 774 mW 7.26 / 8.0 1.6GS/s Power ENOB (bit) F s Note: The performance of this work is estimated based on post-layout simulation. Channel SAR ADC SHA Reference ADC Reference ADC clock generator DLL Bias network Extension to Flash ADC • Modern high-speed communication systems create urgent demands on ADC – Next generation UWB wireless technology – High bit rate optical communication system • The sampling rate versus power consumption – Super linear trade off for high-speed ADC – Solution: Time interleaved architecture • Fabrication technology advancement – Digital circuits: Unprecedented speed, higher integration level – Analog circuits: SCE, low supply voltage, process variation – Solution: Adaptive digital calibration corrects analog impairment • Single channel ADC is simulated with all analog nonidealities • Use pure sine wave as input • Conversion errors are calibrated • Apply the similar idea to a 10GS/s 6-bit flash ADC • Minimal sized comparators – Reduce input capacitance – Reduce power • Large comparator offset – Cancelled by the trimmable voltage sources • ADF – Compare reference ADC and flash ADC output – Generate control codes 0 1 2 3 4 5 x 10 7 -80 -60 -40 -20 0 PSD before Calibration Hz dB(Normalized) SFDR=22.6dB ENOB=3.03bit 0 1 2 3 4 5 x 10 7 -80 -70 -60 -50 -40 -30 -20 -10 0 PSD after Calibration Hz dB(Normalized) SFDR=50.9dB ENOB=5.92bit Ref. A/D M ADF V in Trimmable votage source Full flash ADC