A 6.1mW Dual-Loop DLL with 4.6ps RMS Jitter Paritosh Bhoraskar and Yun Chiu Illinois Center fo Wireless Systems D LL Applications • D elay-variation com pensation in Fiber-O ptic C om m. • Integral partofC lock-D ata R ecovery (C D R )Blocks in W ireline and W ireless C om m unication Solutions • TargetApplication: Interleaved AD C array require m ultiple phases of a clock aligned w ith anotherclock atdifferent frequency W indow Based Phase D etector • R eplica delay line and D A C used to generate tim ing w indow that tracks inputreference • Three state PD w ith U P/D N and H O LD state.D igital control w ord frozen in H O LD state • R elaxed PD design spec due to tim ing w indow • Pow ersaving in D igital C ontrol in H O LD state Q Q SET C LR D Q Q SET C LR D R ef In Window Dn Up R ef O ut Window U P:Low ,D N :H igh (ShiftR ight) UP:High,DN :High ( Lock ) U P:H igh,D N :Low (ShiftLeft) MajorTradeoffs • C ontrol-w ord lim itcycle dom inates Jitter • Fine LSB and high pow er required forlow jitter • W indow -ed PD elim inates lim it cycle based jitter • Low Jitterand low pow er solution • C ost:Largerstatic phase error LSB size Area/Pow erC onsum ption Jitter Pow er Jitter Jitter(w indow PD ) D igital C ontrol Logic • Startup Successive Approxim ation Binary search • Harm onic Lock avoided by starting w ith m in delay using reset. D uty-cycle free harm onic lock detection also im plem ented to elim inate false lock • U nderflow /O verflow based stuck locks corrected by confining delay-line delay s.t. T/2 < D elay <3T/2 • Im plem ented by inverting Phase Detectordecision based on ‘M onitor’ signal 0.5 Tref 1.5 Tref R ef Stuck Lock False Lock Stuck Lock R esolved R ef O ut PD_UP PD_DN Sys_clk U nderflow Monitor Inc D ec Stuck Lock M easurem entResults DAC 2 DAC 1 DAC rep DL 1 DL rep LF DL 2 PD O utput Driver 0.83mm 0.84mm 6.1 5.6 5.1 4.8 Power(m W ) 4.6 4.7 6.1 9.1 RM S Jitter(ps) 1.2 0.8 0.4 0.2 f2(G Hz) 120 80 40 20 f1(M Hz) R esults atVdd = 1.25V,T = 25°C across 5 w orking chips • D LL fabricated in 0.13um process • Active die area 400 X 600 m 2 •Total D ie Area 830x840 m2 •Low RM S jitterattained for low pow er Proposed Architecture • O ne loop com pletely inside anotherapproach as opposed to usual cascaded loop dual-loop architecture • InnerLoop generates 10 uniform outputphases forinterleaved AD C channels • O uterLoop aligns all these phases to faster reference clock used by Sam ple and H old ofthe ADC f outer PD 1 LF 1 DAC 1 PD 2 LF 2 DAC 2 C LK Phase1 Phase 10 Phase 2 R eplica D elay C ell M ain D elay C ell C LK InnerLoop Delay Cell DAC rep Offset f inner