1 FPGA Introduction FPGA Introduction FPGA Introduction FPGA Introduction An FPGA is an digital integrated circuit 015 An FPGA is programmable in the in the field (=outside the factory), hence the name “field programmable” ◦ Design is specified by schematics or with a hardware description o XXX ciclo 20 ◦ Design is specified by schematics or with a hardware description language ◦ Tools compute a programming file for the FPGA ◦ The FPGA is configured with the design Dottorato ◦ The FPGA is configured with the design ◦ Your electronic circuit is ready to use With an FPGA you can build electronic circuits … e dati: FPGA ◦ … without using a soldering iron ◦ … without plugging together existing modules ◦ … without having a chip pr oduced at a factor y a e acquisizion … without having a chip produced at a factory A lot of material taken from H.Sakulin lecture Elettronica
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FPGA IntroductionFPGA IntroductionFPGA IntroductionFPGA Introduction An FPGA is an digital integrated circuit
015
g g An FPGA is programmable in the in the field (=outside the
factory), hence the name “field programmable”◦ Design is specified by schematics or with a hardware description
oX
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cic
lo20 ◦ Design is specified by schematics or with a hardware description
language◦ Tools compute a programming file for the FPGA◦ The FPGA is configured with the design
Dot
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to ◦ The FPGA is configured with the design◦ Your electronic circuit is ready to use
With an FPGA you can build electronic circuits …
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PGA ◦ … without using a soldering iron
◦ … without plugging together existing modules◦ … without having a chip produced at a factory
ae
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ion … without having a chip produced at a factory
A lot of material taken from H.Sakulin lecture
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What’s inside an FPGAWhat’s inside an FPGAWhat s inside an FPGAWhat s inside an FPGA01
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A A LookUpLookUp Table (LUT) based cellTable (LUT) based cellA A LookUpLookUp Table (LUT) based cellTable (LUT) based cell01
Schematic◦ Graphical overview◦ Can draw entire design
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HDL: Verilog, VHDLC bl k l
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◦ (Almost) independent of design tool◦ May use tools used in SW development (CVS, SVN …)
New trends
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◦ C-like languages (handle-C, system-C, …)◦ Labview
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Schematic and HDL are often combined together
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Combining various design entry stylesCombining various design entry stylesCombining various design entry stylesCombining various design entry styles01
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Design FlowDesign FlowDesign FlowDesign Flow01
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First Level Trigger at collidersFirst Level Trigger at collidersFirst Level Trigger at collidersFirst Level Trigger at colliders01
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FPGA used in trigger logic because:FPGA used in trigger logic because:FPGA used in trigger logic because:FPGA used in trigger logic because: They are fast
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They are fast◦ Much faster than discrete electronics (shorter
connections)
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Many parallel inputs◦ Data from many parts of the detector has to be
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PGA All operations are performed in parallel
◦ Can build pipelined logic They can be re programmed
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ion They can be re-programmed◦ Trigger algorithms can be optimized
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FPGA used in data acquisitionFPGA used in data acquisitionFPGA used in data acquisitionFPGA used in data acquisition Frontend Electronics
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Frontend Electronics◦ Pedestal subtraction◦ Zero suppression
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◦ …C d li k
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Several serial LVDS links in parallel Up to 400 MB/s
Interface from custom hardware to commercial l i
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ion electronics◦ PCI bus, VME bus, Myrinet, etc.
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26 Example: Multi Purpose Digitizer (MPD)Example: Multi Purpose Digitizer (MPD) 16 channels, differntial, 12 bit, up to 50 MHz, synchronous ADC, Full-
Scale Range: 2Vpp 4 x HDMI-A front panel connectors for analog inputs
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p g p 2 x HDMI-A front panel connectors for digital controls (clock, fast
commands, I2C) 2 +2 general purpose coaxial (LEMO 00) front panel inputs and outputs,
software selectable NIM or LVTTL levels
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software selectable NIM or LVTTL levels Front panel coaxial (LEMO 00) clock input, 40 MHz, LVTTL, 50
terminated 10-100 RJ-45 copper Ethernet port
SFP f l i i bi i l li k i
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to SFP cage for multigigabit optical link connection 4 general purpose LEDs VXS connector option, 4 RX and 4 TX pairs connected to the FPGA ADC clock phase adjustable to compensate cable delay
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ADC clock phase adjustable to compensate cable delay Logic functions based on Altera ARRIA-GX EP1AGX60F780 FPGA On board real time data processing capabilities VME 64x compliant with up to 2eSST cycles
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VME live insertion capabilities 128 MB DDR2 SDRAM SD-Card interface
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Single +5V power supply Expansion option using PMC compliant connectors VME based or standalone operation