An Overview of Advanced FPGA Verification

An Overview of Advanced

FPGA VerificationAn Overview of Advanced

FPGA Verification

Avinash Keshev| [email protected] | +919019256513

FPGA Design Trends

• Embedded processor cores

❖ 69% of all FPGA projects contain one or more embedded processors, 45% contain two or more processors, 3% include eight or more embedded processors

• Asynchronous clockdomains

❖ 92% of FPGA designs contain two or more asynchronous clock domains.

• Security features❖ 43% of FPGA projects

add security featuresto their designs

• Safety-critical design❖ 40% of all FPGA

projects are following multiple safety-critical standards

Source: 2020 Wilson Research Group functional verification study: FPGA functional verification trend report

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FPGA Verification Adoption Trends

• Verification languages and methodology adoption trends❖ Increasing interest in adoption of

SystemVerilog language to build testbenches.

❖ The Accellera UVM is currently the predominant standard that has been adopted to create FPGA testbenches

❖ SystemVerilog Assertions (SVA) is the predominant assertion language in use today

• Verification technology adoption trends❖ The adoption of formal property

checking on FPGA projects is growing at an impressive 10 percent CAGR, and the adoption of automatic formal applications is growing at a 21 percent CAGR

❖ FPGA project adoption trends for simulation-based techniques like code coverage, functional coverage, assertions, and constrained-random simulation indicates FPGA market has matured its verification processes


Implementation Challenges & Your Hurdles

• FPGA Completion to Original Schedule❖ Majority of FPGA projects

miss schedule

• FPGA Verification Project Time❖ FPGA verification

consumes majority of project time

• Number of FPGA BugEscapes to Production❖ Bugs found late in the

development cycle are exponentially more expensive

• Biggest FPGA Verification Challenges❖ Sufficient testing are the

biggest challenges



Changing Verification MethodologyMoving from Ad Hoc to Structured as Complexity Increases

Ad Hoc StructuredDebug Lab, Limited Simulation Simulation, Selective Lab

TB Language VHDL & Verilog System Verilog & UVM/UVMF

Verification Skillset FPGA Generalist More Verification Engineers

Verification Planning Ad Hoc Plan Driven Management

Coverage Some Code Coverage Code & Functional Coverage

Simulation Models/BFMs Home Grown 3rd Party VIPDesign Rule Checks & CDC Code Review Formal & CDC tools

Failure Modes Manual Analysis, Forces Formal Tools/SLECRegression Management Manual, Local CPU Automated, Server Farm

Requirement TrackingManua

1

Tool Based/Automated

Lab, Limited Simulation Simulation, Selective LabDebug

TB Language VHDL & Verilog System Verilog & UVM/UVMF

Verification Skillset FPGA Generalist More Verification Engineers

Verification Planning Ad Hoc Plan Driven Management

Coverage Some Code Coverage Code & Functional Coverage

Simulation Models/BFMs Home Grown 3rd PartyVIPDesign Rule Checks & CDC Code Review Formal & CDC tools

Failure Modes Manual Analysis, Forces Formal Tools/SLECRegression Management Manual, Local CPU Automated, Server Farm

Requirement Tracking Manual Tool Based/Automated

Increase Accessibility

• Enable FPGA customers to use verification tools quicklyand easily:

• Ease of use

• FPGA centric flows

• Integration with FPGA vendor software

Advanced FPGA Verification

• Improve customer’s efficiency through advanced FPGAverification techniques:

• UVM, VIP, Formal verification & CDC

• Emerging FPGA technologies: FPGA SoC, Cloud, HLS

• Secure foundry/trusted IP

Strategic Vendor Partnerships

• Create strong communication with FPGA vendors to resolve customer issues and align with new FPGA technology:

• Compatibility & performance

• Collaboration on future developments

• Communication channels for issues


Siemens EDA (formerly Mentor Graphics) Initiatives to Help FPGA Verification

Benefits of SystemVerilog and UVM

Improving quality and reducing schedule with SV and UVM

System Verilog

Constrained random

• Tests things you didn’t think of

• Powerful constraints, statistical weighting

Functional coverage

• Provides insight into what is being tested

• Measures testing completeness and quality

Assertions

• Improves debug efficiency

• Clearly identifies problem location

Promotes Reuse

• Reuse within and across projects

• Reduces TB development effort

SystemVerilog Enabler

• Reduces scope of SV

• Enhances SV functionality

Provides Methodology

• Guides how to build a testbench

• Common industry standard


UVM

Siemens EDA (formerly Mentor Graphics) UVM Framework (UVMF) for Easier UVMMaking the transition to UVM possible

UVM Jumpstart

• Immediately productive while learning UVM

• Layer on top of UVM that hides UVM details

• Allows team to focus on verifying product features

• Promotes reuse increasing productivity

UVM Testbench Generators

• Code generators to create a UVM testbench in minutes

• Saves 3-4 weeks of effort on every project

• UVMF is open source and no cost – Delivered in Questa 10.5 & 10.6

Helped over 40 companies adopt UVM

• 75% are FPGA customers

• Over half are in mil-aero industry

• Majority use VHDL for design and have no SystemVerilog experience


Verification IP solutionsProvide broad portfolio coverage, a complete VIP solution, easy automated integration


every Siemens VIP includes:

high-perf computeEthernet up to 800G, MacSec

PCIe5/PCIe6 interconnect

CXL1/2/3 Coherent Fabric

essential protocol AMBA® AXI, AHB, APB

UART, SPI, I2C, JTAG

PCIe®

EthernetAMBA®

Serial

USB

MilAeroMIPI

Flash

Display

DDR

HBM

human interface USB4, USB3.2

HDMI, DisplayPort

fast memory modelDDR5, DIMM5, LPDDR5

High Bandwidth Memory

Flash & SSD standardsspecific application

Mil-Aero, Spacewire, 1553b

MIPI CSI, DSI interconnect

complete verification

• test plans / test suites

• assertions / checks

• coverage models

interoperability

• SystemVerilog language

• UVM methodology base

• all simulators supported

debug productivity

• protocol debug logging

• visual transactions

• transaction linking

automation

• configurator app

• auto generated tb code

• easy setup and usage

Visualizer Debug EnvironmentHigh performance, unified debug to increase overall debug efficiency

• Unified debug environment across entire platform• Powerful RTL and TB debug

• Common debug across simulation, emulation, formal

• Built from ground up for efficient debug• High performance, high capacity

• Powerful automation: find bugs faster

• Full featured UVM/SV post-sim• UVM schematics, SV class-based TB debug

• Powerful transaction and UVM exploring

• Post-sim debug with live-sim visibility• Reconstruction: dump less, see more

• Design comprehension: find root causes


Formal Verification Finds Bugs EarlierBugs found early save money and time

Customer Site

Production

LabTest

Simulation

Design

Requirements

Formal Tools, No Testbench Required!


• Can be use to check design as soon as RTL is ready

• Resolve bugs at design time

• Minimum impact to product schedule

• Automated results, re-run at project milestones

Questa Formal & CDC EnginesAutomated, exhaustive formal solutions when quality matters


• Questa Formal

• Industry-Leading Formal Automation

• Formal tools for every phase of project

• Quick Start with Formal Apps

• Early verification – no testbench required

• Apps automatically generate assertions

• Targets Specific Problems

• Many not addressed by simulation

• Automation enables adoption

• Complements Simulation

• Makes simulation more efficient

• Unified metrics

Questa Verification ManagementUnified metrics for Plan Driven Verification

• Plan driven verification

• Coverage driven verification

• Enables traceability and evidence

• Managing Data

• Unified coverage – code, functional, assertion

• Unified management

• Regression Automation

• Unified Plan Driven

• Electronic closure

• Verification Automation

• Unification across engines

• Throughput efficiency


[email protected]

/company/prolim-solutions-india

8971 55 66 77

/ProlimSolutionsIndia

Avinash Keshev| [email protected] | +919019256513Feel free to contact us:

Plan

Do

Act

Check

Achieve Deming Quality Culture

Create less Rejection

Reduce cost of Quality

An Overview of Advanced FPGA Verification

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