1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 3 CPUs.

1Copyright © 2013 Elsevier Inc. All rights reserved.

Chapter 3

CPUs


Figure 3.1 Structure of a typical I/O device.


Figure 3.2 The interrupt mechanism.


Figure 3.3 Prioritized device interrupts.


Figure 3.4 Using polling to share an interrupt over several devices.


Figure 3.5 Interrupt vectors.


Figure 3.6 The cache in the memory system.


Figure 3.7 A two-level cache system.


Figure 3.8 A direct-mapped cache.


Figure 3.9 A set-associative cache.


Figure 3.10 A virtually addressed memory system.


Figure 3.11 Segments and pages.


Figure 3.12 Address translation for a segment.


Figure 3.13 Address translation for a page.


Figure 3.14 Alternative schemes for organizing page tables.


Figure 3.15 ARM two-stage address translation.


Figure 3.16 Pipelined execution of ARM instructions.


Figure 3.17 Pipelined execution of multicycle ARM instructions.


Figure 3.18 Pipelined execution of a branch in ARM.


Figure 3.19 A power state machine for a processor.


Figure 3.20 UML collaboration diagram for the data compressor.


Figure 3.21 Definition of the data-compressor class.


Figure 3.22 Additional class definitions for the data compressor.


Figure 3.23 Relationships between classes in the data compressor.


Figure 3.24 State diagram for encode behavior.


Figure 3.25 State diagram for insert behavior.


Figure 3.26 A test of the encoder.


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UN Figure 3.12

1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 3 CPUs.

Documents

cpus slide

data compressor

datacompressor class

state diagram

twolevel cache system

memory system

stage address translation

directmapped cache