08-State Machines 2.,

COMP541

State Machines 2Registers and CountersMontek Singh

Feb 8, 2007

TopicsLab previewState machine specification stylesFunctional: State tables/diagrams/graphsStructural: Boolean equationsBehavioral: VerilogBuilding blocks: registers and counters

Lab PreviewDigital lockRecognize sequence of four 4-bit input valuesInput:Use 4 DIP switches on the boardOutput:Indicate yes/no on LED display

Concepts learned:State machine specificationState machine synthesisGenerating/measuring time intervalsSwitch button debouncing

Time intervalsmodule cntr(output out, input clk);

reg [31:0] count;

always @ (posedge clk) count

Button and DebouncingButton normally highMechanical switches can bounceGo 1 and 0 a number of times

Well want toDebounce: Any ideas?Synchronize with clock

Flip-Flop for pushbuttonmodule button_test( output q, input btn, input clk );

reg q;

always @ (posedge clk)beginif(btn == 1)q

Simple Module to Begin Withmodule led_on(output s6, input button, input clk);

wire clkb; //opt

cntr C1(clkb, clk);button_test B1(s6, ~button, clkb);

endmodule clk to board clock, P88 button to pushbutton, P93 Why ~button? s6 to one of LED segments

Things to Think AboutCan I press button and not light LED?What happens if I hold button down for a long time?What effect will changing period of clkb have?On LEDOn button debouncingWhat does it mean to press the button?Think carefully about this

Revisit sequence detector exampleDesign a state machine to detect the pattern 1101In last class: We developed state graph for itToday: Learn how to code this in Verilog

Verilog Case StatementSimilar to sequence of if/then/else case (expression) case: statements; other case: statements; default: statements;// optional endcase

Example in a moment

Parameter = defines constantmodule seq_rec_v(CLK, RESET, X, Z);input CLK, RESET, X;output Z;reg [1:0] state, next_state;

parameter A = 2'b00, B = 2'b01, C = 2 'b10, D = 2'b11;

Notice that weve assigned codes to the states more later

Pitfall: Beware of Unexpected Latches!You can easily specify latches unexpectedlyHangover from programming in C!

always will try to synthesize FF:if (select) out

Comment on Book CodeCould shortenDont need next_state, for exampleCan just set state on clockNote that the two are a little different in functionDont need three always clausesAlthough its easier to have combinational code to set output be separateTemplate helps synthesizerCheck to see whether your state machines were recognized

Registers and Counters: DefinitionsRegister a set of flip-flopsMay include extensive logic to control state transitionMay allow shiftingregister also refers to fast memory for storing data in a computerCounterRegister that goes through sequence of states as it is clocked

Simple RegisterStore D On posedge of ClockClear signal normally highPower-up resetSymbol

ClockingTypically dont want to load every clockCan gate the clockBut added clock skew is a problem

EnableIf load H, then D is gated throughOtherwise, Q is fed backKeep same valueNo clock gating

Did this because D FF doesnt have a no change behavior

CountersCounter is a register has stateAlso goes through sequence of states counts on clock or other pulsesBinary counter Counts through binary sequencen bit counter counts from 0 to 2n

Ripple CounterSimpleSo Q will alternate 1 and 0

Why called ripple counter?

Synchronous CountersRipple counter is easyAsynchronous nature may cause problems, thoughDelay!

Synchronous counter most common

Synchronous CounterDoes have sequence of gatesDelay again

Parallel DesignNow constant delayCan gang these to make long serial-parallel counter

Verilog Counter (simple)module count (CLK, EN, Q);input CLK, EN;output [3:0] Q;

reg [3:0] Q;

always@(posedge CLK)beginif (EN) Q

Verilog Counter (from book)module count_4_r_v (CLK, RESET, EN, Q, CO);input CLK, RESET, EN;output [3:0] Q;output CO;

reg [3:0] Q;assign CO = (count == 4'b1111 && EN == 1b1) ? 1 : 0;always@(posedge CLK or posedge RESET)beginif (RESET) Q

Arbitrary CountOne more type of counter is usefulCount an arbitrary sequenceMaybe you need a sequence of states

Circuit and State Diagram

Shift RegistersCapability to shift bitsIn one or both directionsWhy?Part of standard CPU instruction setCheap multiplicationSerial communicationsJust a chain of flip-flops

Simple 4-Bit Shift RegisterClocked in commonJust serial in and serial outIs this a FIFO?

Parallel LoadCan provide parallel outputs from flip-flopsAnd also parallel inputs

SchematicDetailNext

Detail

Why is this useful?Basis for serial communicationsKeyboardSerial portInitially to connect to terminalsNow mainly for modemUSBFirewire

ExampleClocked 4 timesWhy do this? Maybe these are far apartCould shift data in, or parallel loadWhats on wire at each clock?

Table Showing Shift

Serial vs. Parallel TransferParallel transfer over as many wires as word (for example)Serial transfer over a single wireTrade time for wiresTakes n times longer

Bidirectional Shift RegisterShift either wayNow we have following possible inputsParallel loadShift from leftShift from rightAlso no changeSchematic next

Schematic

Verilog for Shift Registermodule srg_4_r (CLK, SI, Q, SO);input CLK, SI;output [3:0] Q;output SO;

reg [3:0] Q;assign SO = Q[3];

always@(posedge CLK)begin Q

Next TimeHow to generate a VGA signalMore on state machines

Optional Example: One ShotHelp me analyze this one

What does it do?